Patents Issued in September 2, 2003
  • Patent number: 6614095
    Abstract: The invention relates to a component which has a function element arranged on a substrate the function element being electrically contacted in a contact region on its rear side facing the substrate. The substrate has an opening in the contact region and the rear side of the function element is coated with a contact metal.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: September 2, 2003
    Assignee: GFD-Gesellschaft fur Diamantprodukte mbH
    Inventors: Mario Adamschik, Erhard Kohn, Peter Gluche, Alexander Kaiser
  • Patent number: 6614096
    Abstract: Disclosed is a method for manufacturing a semiconductor device, which comprises the steps of forming a first insulating film made of a low dielectric constant material and containing carbon, subjecting the first insulating film to a surface treatment to reduce the carbon concentration of surface layer of the first insulating film, thus turning the surface layer into a low carbon concentration layer, forming a second insulating film on the low carbon concentration layer, forming a groove in the first and second insulating films for burying a metal therein, burying the metal in the groove formed in the first and second insulating films, and polishing a surface of the metal buried in the groove to thereby form a metal wiring.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: September 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Hideshi Miyajima
  • Patent number: 6614097
    Abstract: A method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device is disclosed. A layer of silica precursor material is first deposited on a silicon substrate. Without affecting its structure and porosity, the layer of silica precursor material is then dried; and the layer of silica precursor material becomes porous silica film. Subsequently, a protective layer, such as parylene, is deposited on top of the dried porous silica film. The thickness of the protective layer should be greater than the peak-valley planarization requirements of the silicon substrate surface. As a result, a composite porous silica film, which services as a dielectric layer within an interconnect structure, is formed. This composite porous silica film has a relatively low dielectric constant and is able to withstand damage from a standard CMP procedure.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: September 2, 2003
    Assignee: LSI Logic Corporation
    Inventors: Gayle W. Miller, Gail D. Shelton
  • Patent number: 6614098
    Abstract: A method of fabricating a tungsten contact in a semiconductor device comprises providing an oxide layer on a region of a silicon substrate; depositing a sealing dielectric layer over the oxide layer; and depositing an interlevel dielectric layer over the sealing layer. The interlevel dielectric layer, the sealing dielectric layer and the oxide layer are then etched through as far as the substrate thereby to form a contact hole and to expose the said region. A dopant is implanted into the said region whereby the implanted dopant is self-aligned to the contact hole. The substrate is thermally annealed. Tungsten is selectively deposited in the contact hole and an interconnect layer is deposited over the deposited tungsten contact. The invention also provides a semiconductor device which incorporates a tungsten contact and which can be fabricated by the method.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: September 2, 2003
    Assignee: Inmos Limited
    Inventors: Howard Charles Nicholls, Michael John Norrington, Michael Kevin Thompson
  • Patent number: 6614099
    Abstract: A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are less attractive than copper wires and polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, current techniques cannot realize the promise because copper reacts with the polymer-based insulation to form copper dioxide within the polymer, reducing effectiveness of the copper-polymer combination. Accordingly, the inventor devised a method which uses a non-acid-precursor to form a polymeric layer and then cures, or bakes, it in a non-oxidizing atmosphere, thereby making the layer resistant to copper-dioxidizing reactions. Afterward, the method applies a copper-adhesion material, such as zirconium, to the layer to promote adhesion with a subsequent copper layer.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: September 2, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 6614100
    Abstract: The lead frame has a spring element, which can be compressed during the injection molding of the package by an injection mold. The resultant resilience has the effect that a contact surface of the lead is pressed against an inside wall of the injection mold. The biasing of the contact surface against the inside wall prevents polymer flash from forming on the contact surface. Also, the spring element fixes the lead during the injection operation and anchors the lead in the completed package. Hold-down pins within the injection mold are thus obviated.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: September 2, 2003
    Assignee: Infineon Technologies AG
    Inventors: Christian Hauser, Helge Schmidt, Johann Winderl
  • Patent number: 6614101
    Abstract: A plastic packaged semiconductor device is constructed by sealing, with a sealing plastic, a semiconductor chip which has an electrode pad arranged in a central portion of an upper surface, a die pad to which the semiconductor chip is die-bonded, bonding wires which are connected to the electrode pad, and inner leads which are arranged in close vicinity of the die pad and have tip portions having upper flat surfaces which are positioned at a level equal to or higher than the upper surface of the semiconductor chip and to which the bonding wires are connected. Accordingly, the small thin plastic packaged semiconductor device in which the bonding wires do never come into contact with the edge of the semiconductor chip can be achieved.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: September 2, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyuki Misumi, Kazunari Michii, Manabu Horita
  • Patent number: 6614102
    Abstract: A semiconductor chip package includes a plurality of leadframe portions and a semiconductor die mounted on at least one of the leadframe portions. A shield element is attached to at least one of the leadframe portions. A package mold surrounds the semiconductor die and the shield element. Radiation shielding is thereby provided in a practical manner for a leadframe-based semiconductor chip package.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: September 2, 2003
    Assignee: Amkor Technology, Inc.
    Inventors: Paul Hoffman, Doug Mathews
  • Patent number: 6614103
    Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: September 2, 2003
    Assignee: General Electric Company
    Inventors: Kevin Matthew Durocher, Ernest Wayne Balch, Vikram B. Krishnamurthy, Richard Joseph Saia, Herbert Stanley Cole, Ronald Frank Kolc
  • Patent number: 6614104
    Abstract: A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: September 2, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Mike Brooks
  • Patent number: 6614105
    Abstract: A TRIAC which is one species of chip-type semiconductors includes an element body made of silicon, electrodes provided on one face of the element body, a molybdenum plate provided on one of the electrodes by an alloy plate made of aluminum and silicon, a molybdenum plate provided on the other face of the element body by a similar alloy plate, and nickel layers provided on connection faces of the molybdenum plates to outer electrode plates, so that the electrode and molybdenum plate are firmly connected without conventional high-temperature solder which includes a great amount of lead, and that the alloy plate never melt even when newly developed low-temperature institute is employed, and that the operation of the molybdenum plates is sufficiently realized.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 2, 2003
    Assignees: Powered Co., Ltd., Omron Corporation
    Inventor: Ryoichi Ikuhashi
  • Patent number: 6614106
    Abstract: A stacked circuit device comprises a base substrate having a terminal, an interposer arranged on the base substrate and formed of a semiconductor substrate, the interposer having a first terminal connected to the terminal of the base substrate, a second terminal, and a circuit coupled to the second terminal and including an active element, and an integrated circuit chip arranged on the interposer and having a terminal connected to the second terminal.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: September 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Nobuo Hayasaka
  • Patent number: 6614107
    Abstract: A thin-film heat sink comprises a heat sink film functioning as a heat sink and a bonding film for bonding the heat sink film to a base. The bonding film is an aluminum oxide (Al2O3) film formed using the CVD method and the heat sink film is an aluminum nitride (AlN) film. For the AlN film as the heat sink film, internal stress is compressive stress, whereas for the Al2O3 film as the bonding film, internal stress is tensile stress.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: September 2, 2003
    Assignee: TDK Corporation
    Inventors: Tohru Inoue, Shigeki Tanemura
  • Patent number: 6614108
    Abstract: An electronic package and a method for packaging an electronic component, particularly a shock-sensitive component such as a yaw rate sensor or an accelerometer mounted to a circuit board. The package includes a case having an opening through which the circuit board is placed within the case, so that a peripheral edge of the circuit board is adjacent but spaced apart from a wall of the case. A thixotropic gel is present in the space between the peripheral edge of the circuit board and the wall of the case, so as to separate and control the mechanical decoupling of the circuit board and case. An optional spacer can be used to space the circuit board from the shelf. Alternatively, the gel may be filled with a polymer particulate material. A potting material preferably fills an upper cavity within the case to encapsulate and secure the circuit board within the case.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: September 2, 2003
    Assignee: Delphi Technologies, Inc.
    Inventors: Henry M. Sanftleben, Derek S. Ferraro
  • Patent number: 6614109
    Abstract: Method and apparatus for thermal management of an integrated circuit. A semiconductor device includes an integrated circuit and an integrated thermoelectric cooler formed on a common substrate. A semiconductor device is fabricated by forming an integrated circuit on a front side of the substrate and forming an integrated thermoelectric cooler on a back side of the substrate. A first thermal sink of semiconductor material capable of absorbing heat from the integrated circuit is formed on the back side of the substrate. N-type thermoelectric elements are formed on contacts formed on the first thermal sink. P-type thermoelectric elements are formed on contacts formed on a second thermal sink of semiconductor material capable of dissipating heat. The p-type and n-type thermoelectric elements are bonded to the contacts on the first and second thermal sinks, respectively, by a flip-chip soldering process.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: September 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Michael James Cordes, Steven Alan Cordes, Uttam Shyamalindu Ghoshal, Errol Wayne Robinson, James Louis Speidell
  • Patent number: 6614110
    Abstract: An electronic packaging module for inverted bonding of electronic devicss including semiconductor devices, integrated circuits, application specific integrated circuits, electomechanical devices and MEMS is produced with protuberances on the conductive pattern of the substrate. The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the input/output pads of electronic devices. The input/output pads of the devices may be simultaneously bonded to the protuberances of the packaging module.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: September 2, 2003
    Inventor: Benedict G Pace
  • Patent number: 6614111
    Abstract: A semiconductor device able to maintain a bonding state between a bump and an electrode and having high reliability even under thermal stress, wherein a sealing resin is interposed to bond the electrodes and bumps between a wiring board formed with a plurality of electrodes and an IC chip formed with a plurality of bumps, the bumps being formed under the condition that the following formula is satisfied. 100<((&PHgr;A×F)/H)<125 where &PHgr;A represents the top diameter of a bump bonded with an electrode, H the height of a bump projecting from the IC chip and bonded with an electrode, and F the linear thermal expansion coefficient of the sealing resin.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: September 2, 2003
    Assignee: Sony Corporation
    Inventors: Satoshi Iwatsu, Noriyuki Honda
  • Patent number: 6614112
    Abstract: A semiconductor device includes a substrate; a metal layer formed on the substrate; an insulating layer, which is formed on the metal layer and is provided with a via-hole through it; and a bonding pad formed above the via-hole. The bonding pad comprises an inner portion arranged in the via-hole and an outer portion arranged above the via-hole. The boding pad is made of a conductive resin having a shock absorbing characteristic.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: September 2, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasufumi Uchida
  • Patent number: 6614113
    Abstract: A semiconductor device includes a barrier metal structure which are sandwiched between an electrode provided on a semiconductor chip and a bump. The barrier metal structure has a first through third conductive metal layers, where the third conductive metal layer as an uppermost layer thereof in contact with the bump covers the second conductive metal layer made of a material which is weak in resistance to diffusion and oxidation.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: September 2, 2003
    Assignee: Fujitsu Limited
    Inventors: Eiji Watanabe, Kouichi Murata
  • Patent number: 6614114
    Abstract: The present invention relates to a conductive line on an integrated circuit. The integrated circuit includes an insulating layer in which is formed several grooves of predetermined width. The conductive line includes a first interconnection layer having a first thickness and a second interconnection layer having a second thickness. The predetermined width is greater than twice the greatest of the two thicknesses, and smaller than twice the sum of the thicknesses.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: September 2, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Yvon Gris
  • Patent number: 6614115
    Abstract: A method for cooling an MOVPE deposited, As-containing, P-type contact layer includes cooling the contact layer in an arsine environment to preserve the contact layer during the initial stages of the cooling process until a threshold temperature in the range of 560 to 580° C. is attained. During the cooling process, the arsine flow is reduced with respect to the arsine flow used during the MOVPE deposition. After the threshold temperature is attained, the arsine gas is withdrawn and the contact layer is cooled further. Because of the removal of the arsine gas at the threshold temperature, free carrier concentration within the contact layer is enhanced above the atomic concentration of the P-type dopant, and contact resistance is improved to a suitably low level. A semiconductor optoelectronic device is formed to include such a contact layer, the P-type dopant impurity present in an atomic concentration and the contact layer having a free carrier concentration being greater than the atomic concentration.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: September 2, 2003
    Assignee: Agere Systems Inc.
    Inventors: Marlin Focht, Ronald Eugene Leibenguth, Claude Lewis Reynolds
  • Patent number: 6614116
    Abstract: A process of making a buried digit line stack is disclosed. The process includes forming a silicon-lean metal silicide first film over a polysilicon plug, followed by a silicide compound barrier second film. The silicide compound barrier second film is covered with a refractory metal third film. A salicidation process causes the first film to salicide with the polysilicon plug. In one embodiment, all the aforementioned deposition processes are carried out by physical vapor deposition (“PVD”).
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: September 2, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Y. Jeff Hu
  • Patent number: 6614117
    Abstract: According to one embodiment, an NiV adhesion layer is deposited over the backside surface of a semiconductor substrate. The semiconductor substrate might comprise a group III-V compound semiconductor. The NiV adhesion layer can be deposited over the backside surface of the semiconductor substrate in, for example, a magnetron deposition system. In certain embodiments, the backside surface of the semiconductor surface may be cleaned to remove oxides from the surface prior to deposition of the NiV adhesion layer. After the NiV adhesion layer has been deposited, a gold seed layer is deposited over the NiV adhesion layer. Following deposition of the gold seed layer, a second gold layer is electroplated, or otherwise deposited, over the gold seed layer. In one embodiment, the invention is a structure fabricated according to the process steps described above.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: September 2, 2003
    Assignee: Skyworks Solutions, Inc.
    Inventors: Shiban K. Tiku, Heather L. Knoedler, Richard S. Burton
  • Patent number: 6614118
    Abstract: The invention provides in one embodiment thereof an integrated circuit. The integrated circuit includes a first interconnection metallization layer formed upon a substrate. The integrated circuit further includes a second interconnection metallization layer formed upon the first interconnection metallization layer. The second interconnection metallization layer has formed therein at least one signal line coupled to the first interconnection metallization layer. The second interconnection metallization layer has formed therein at least one protective structure that surrounds the signal line.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: September 2, 2003
    Assignee: Intel Corporation
    Inventors: Eric Selvin, Krishna Seshan
  • Patent number: 6614119
    Abstract: A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300° C. to 550° C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: September 2, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Michio Asahina, Junichi Takeuchi, Naohiro Moriya, Kazuki Matsumoto
  • Patent number: 6614120
    Abstract: A semiconductor device 1000 in accordance with the present invention has a structure having multiple wiring layers, and includes a bonding pad 40a, dummy wiring forming regions 35 including dummy wirings 30, and dummy wiring prohibiting regions 15 where dummy wirings are not formed. The dummy wiring prohibiting regions 15 are provided at least below a region where the bonding pad 40a is formed.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: September 2, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Hisakatsu Sato, Tomoo Takaso
  • Patent number: 6614121
    Abstract: A semiconductor stack is provided. The semiconductor stack is comprised of a first semiconductor device, a second semiconductor device, and a socket. The first semiconductor device has a plurality of pins extending therefrom and arranged in a first preselected pattern. The socket is adapted to receive the plurality of pins. The second semiconductor device is disposed between the socket and the first semiconductor device and includes a die, a casing, and a plurality of electrical connections. The casing extends about the die and defines a plurality of openings extending therethrough. The openings are arranged in a first preselected pattern to receive the pins of the first semiconductor device. The plurality of electrical connections are disposed in at least a portion of the plurality of openings. The electrical connections are adapted to electrically communicate with the pins of the first semiconductor device inserted therein and the die.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: September 2, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Bryan Timothy Heenan
  • Patent number: 6614122
    Abstract: An apparatus, comprising: a substrate having a surface; a die attached to the substrate surface; an underfill material positioned between the substrate surface and the die; and one or more barriers on the substrate surface adjoining the die, wherein the barriers controls flow of the underfill material.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: September 2, 2003
    Assignee: Intel Corporation
    Inventors: Thomas S. Dory, HengGee Lee, David W. Young, Leigh E. Wojewoda
  • Patent number: 6614123
    Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: September 2, 2003
    Assignee: ChipPAC, Inc.
    Inventors: Taekeun Lee, Flynn Carson, Marcos Karnezos
  • Patent number: 6614124
    Abstract: An SRAM memory cell device comprises wordline and bitline inputs for enabling read/write access to memory cell contents, and, a diffusion region for maintaining a voltage to preserve memory cell content when the cell is not being accessed. The device further comprises a transistor device having a gate input for receiving a wordline voltage to turn off the transistor device when not performing memory cell read/write access; and, a gate oxide layer formed under the transistor device gate exhibiting resistance property for leaking current therethrough when the wordline voltage is applied to the gate input and the transistor device is off. The diffusion region receives voltage derived from the wordline voltage applied to said gate input to enable retention of said memory cell content in the absence of applied bitline voltage to thereby reduce power consumption.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: September 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Scott Brown, Chung Hon Lam, Randy William Mann
  • Patent number: 6614125
    Abstract: An apparatus for mounting a wind turbine on the upper end of a wind turbine tower and the method of erecting the same. The tower is provided with a pair of spaced-apart guide rails positioned at one side thereof which extend from the lower end to the upper end of the tower. A carriage is movably mounted on the guide rails and has a platform pivotally mounted thereon adapted to support the wind turbine thereon. The carriage positions the wind turbine so that the spinner/hub and rotor blades may be secured thereto while the wind turbine is at the lower end of the tower and provides a means for slidably moving the wind turbine from the carriage to the upper end of the tower when the carriage has been winched to the upper end of the tower.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: September 2, 2003
    Assignee: Valmont Industries, Inc.
    Inventors: Jeffrey O. Willis, Anthony J. Hansen
  • Patent number: 6614126
    Abstract: A data communication apparatus comprising includes multiple white light emitting diodes or other sources of light which generate environmental lighting for a user of the data communication apparatus. The data communication apparatus also includes a data transmitting device positioned adjacent the white light emitting diodes, the data transmitting device configured to wirelessly transmit data signals to electronic devices used by the user. The data communication apparatus can also include a data receiving device for receiving wirelessly transmitted data signals from the electronic devices used by the user. The data communication device can be used, for example, in an aircraft cabin lighting system.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: September 2, 2003
    Assignee: Rockwell Collins, Inc.
    Inventor: James P. Mitchell
  • Patent number: 6614127
    Abstract: A combined headlight and windshield wiper control switch for a vehicle that activates the parking lights, headlights and windshield wipers. The switch turns on the parking lights and headlights followed by the various windshield wiper settings. When turning the switch off, the switch uses different actuator movement or a locking mechanism to prevent the parking lights and headlights from being turned off when the windshield wipers are being turned off. The first embodiment uses a locking mechanism in the actuator to prevent the actuator from turning past the parking lights and headlights position. The actuator has a release button on the side that must be pressed to allow the actuator to turn to the off position. In the center of the actuator is another button that enables/disables the lighting circuit and the locking mechanism from the switch.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: September 2, 2003
    Inventor: A. Barron Daniels
  • Patent number: 6614128
    Abstract: The wiring harness includes a first electrical cable having a diameter corresponding to a first current rating of a low voltage load and a second electrical cable having a diameter corresponding to a second current rating of a high voltage load. The diameters of the first and second electrical cables are unified to have the same diameter. The second current rating is determined to be smaller than the first current rating, and the cables are unified to the first electrical cable for the low voltage load.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: September 2, 2003
    Assignee: Yazaki Corporation
    Inventors: Yasushi Mizuguchi, Kazushige Shimura
  • Patent number: 6614129
    Abstract: A firing element and a belt operating sensor are connected via a common wiring pair to a control unit. The belt operating sensor is either a mechanical switch, which is activated in response to the snapping of a belt tongue into the buckle, or it is composed of an electrically controllable switch, which is controlled by a magnetic-field-sensitive element, which reacts to a magnetic field that is influenced by a belt tongue that is inserted into the buckle. Only via a wiring pair can the control unit both diagnose the firing element as well as determine the operating state of the belt.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: September 2, 2003
    Assignee: Robert Bosch GmbH
    Inventor: Bernhard Mattes
  • Patent number: 6614130
    Abstract: An electrical distribution system and method has storage battery mechanism of very large equivalent capacitance providing excellent ripple filtering and an ideal path to ground, and filter capacitor mechanism of microfarad size providing DC blocking and limited AC path to ground. The storage battery entity is maintained as to its charge by DC supply, which provides regulated DC power in which switching regulation may be involved. The system and method provides dual voltage capability, both DC and AC, in which circuit breakers may be ganged for simultaneous tripping, and in which intrinsic DC circuit(s) may be looped to increase current-carrying capability. A DC isolation capacitor is connected to a common current path, such as to one of the busses, such as, for example, in series with the neutral circuit, as a means for avoiding undesirable DC current paths as may be encountered due to a multitude of established neutral-line connections to earthing grounds established throughout in AC power supply network.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: September 2, 2003
    Assignee: Nextek Power Systems, Inc.
    Inventor: William George Wilhelm
  • Patent number: 6614131
    Abstract: A switched mode power supply having a first circuit provided with a primary winding of a transformer to which a pulse voltage is applied, a second circuit having a secondary winding of the transformer, a reactor provided with a magnetic core and which has a terminal connected to a terminal of the secondary winding, at least one filter provided with input and output terminals and a first diode connected in parallel to the input terminals of the filter is shown. The other terminal of the reactor is connected to a terminal of the first diode. The power supply includes a second diode that has a first terminal connected to the other terminal of the first diode and a second terminal connected to the other terminal of the secondary winding and a control circuit coupled to an output terminal of the filter and to the other terminal of the secondary winding. The control circuit generates a current able to reset the magnetic core of the reactor.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: September 2, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Franco Lentini, Fabrizio Librizzi
  • Patent number: 6614132
    Abstract: An electrical energy storage system for supplying power to a load comprises a plurality of flywheel energy storage systems, each supplying a power output signal, and a connector circuit. The connector circuit connects the flywheel energy storage systems to the load, but the flywheel energy storage systems are not connected to each other. Each of the flywheel energy storage systems comprises a flywheel turning at an initially predetermined rate, a motor/generator coupled to the flywheel, a bi-directional inverter circuit coupled to the motor/generator and to the load, and a control circuit coupled to the motor/generator and the bi-directional inverter circuit. The control circuit controls the power output signal of the flywheel energy storage system independently of the other flywheel energy storage systems.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: September 2, 2003
    Assignee: Beacon Power Corporation
    Inventors: Richard L. Hockney, Geoff B. Lansberry, Vladislav Davidkovich, William T. Larkins, Emil Muchnik
  • Patent number: 6614133
    Abstract: In a system having multiple power supplies with outputs connected in parallel, the number of supplies providing current is controlled to improve the overall system efficiency. For example, when the output current of individual power supplies falls below a threshold, one or more supplies may be placed into a standby mode. This increases the output current of the supplies that are in an operational mode, improving the efficiency of the supplies that are in an operational mode.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: September 2, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Steve Belson, Shaun L. Harris
  • Patent number: 6614134
    Abstract: A voltage supply circuit for an ECU, of the type which uses a capacitor to hold charge for use in maintaining the supply during temporary supply interruptions, wherein a charge pump is provided for increasing the voltage available for charging the capacitor to a level above that of the supply to enable the stored energy of the capacitor to be boosted.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: September 2, 2003
    Assignee: Lucas Industries plc
    Inventor: Garry Raymond Davies
  • Patent number: 6614135
    Abstract: An apparatus for generating electromagnetic pulses includes circuitry comprising an induction coil having a silver anode projecting into the coil. Moveable silver mass elements are adjustably mounted on the anode. The circuitry is immersed in liquid hydrogen and when energized produces electromagnetic pulses. If is believed that some of the anode material is consumed during the production of EMP converting the anode material into electromagnetic radiation energy. As the consumption continues the elongate anode assembly produces a composite wave form that equates to the size, shape and arrangement of the mass elements.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: September 2, 2003
    Inventor: Thomas Joseph Clapham
  • Patent number: 6614136
    Abstract: A switching regulator includes an inductive element to provide a first voltage across the element and at least one switch to energize and de-energize the inductive element to produce an output voltage. A controller of the regulator constructs an indication of a current from the first voltage and operates the switch(es) to regulate the output voltage in response to the indication.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 2, 2003
    Assignee: Intel Corporation
    Inventor: Ken K. Lee
  • Patent number: 6614137
    Abstract: Leakage of magnetic fluxes passing through the gaps between the magnetic pole teeth of an armature is reduced thereby to reduce a magnetic attraction force between the armature and a mover. A linear motor includes a first member and a second member. The first member is configured with at least a magnetic pole of a first polarity having a first opposed portion and a magnetic pole of a second polarity having a second opposed portion. The second member is held by the first opposed portion, while the second member is held by the second opposed portion and moves relatively. The first member is formed of an iron core and a winding, and the second member is formed of a permanent magnet, a magnetic material, a winding of a single type or a combination of a plurality of types of materials.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: September 2, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kim Houng Joong, Kohji Maki, Yoshitaka Iwaji, Taizou Miyazaki, Tomoyuki Hanyu
  • Patent number: 6614138
    Abstract: A spindle motor incorporates a hollow shaft and a prewound stator having an interconnect ring attached to one end of the stator assembly. The interconnect ring is preferably a printed circuit or flexible printed circuit; it is bonded to the stator stack before the coils are wound, and the start and finish of each phase winding is terminated to the interconnect ring. Once the stator is assembled onto the shaft, connector wires can be fed up through the shaft and terminated at the interconnect ring. Traces on the interconnect ring join the wires to the proper phases and to the commons to control motor operation.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: September 2, 2003
    Assignee: Seagate Technology LLC
    Inventor: Robert Michael Pelstring
  • Patent number: 6614139
    Abstract: A motor having a dynamic pressure bearing apparatus includes a fixed bearing member mounted to a motor frame, a rotating shaft member rotatably inserted with respect to the fixed bearing member and a lubricating fluid injected into a gap portion between the fixed bearing member and the rotating shaft member. The rotating shaft member is supported by a dynamic-pressure caused by the lubricating fluid. In addition, the motor frame is provided with a generally cylindrical bearing hold member that holds and fixes a bearing member. The bearing hold member includes a bearing contacting portion which abuts against the fixed bearing member or one part of the assembly including the fixed bearing member in an axial direction for positioning the fixed bearing member in a normal position in an axial direction.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: September 2, 2003
    Assignee: Sankyo Seiki Mfg. Co., Ltd.
    Inventors: Masayoshi Saichi, Takehiko Yazawa
  • Patent number: 6614140
    Abstract: Power generation efficiency of a magneto generator is improved. A guard ring 13 made of a material of high magnetic permeability such as carbon steel plate is arranged inside a flywheel 11 for the purpose of holding and guarding magnets 12. the guard ring 13 is provided with opening portions 13a at positions where the guard ring 13 coincides with adjacent two end portions of the neighboring magnets 12. Magnetic flux is prevented from flowing into the neighboring magnets 12 through the guard ring 13 at the time of power generation. The magnetic flux flows into an iron core of a magneto coil 16, and generation efficiency is effectively improved.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: September 2, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fumito Uemura, Shinji Baba, Yoshihide Masumoto, Tomokazu Umezaki
  • Patent number: 6614141
    Abstract: Slots are formed in a stator core at a ratio of two per phase per pole and winding phase portions constituted by star-shaped winding units are installed in the stator core so as to line up in six layers radially. An a-phase winding phase portion, a b-phase winding phase portion, and a c-phase winding phase portion constituting a first three-phase alternating-current winding constitute three radially-outer layers, and a d-phase winding phase portion, an e-phase winding phase portion, and an f-phase winding phase portion constituting a second three-phase alternating-current winding constitute three radially-inner layers.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: September 2, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Atsushi Oohashi, Yoshihito Asao, Katsumi Adachi
  • Patent number: 6614142
    Abstract: A rotor is provided for use at high speed. The rotor comprises a stack of laminations held under compression between opposed flanges. The laminations have a plurality of teeth. Some of the laminations have lugs having passages formed therein through which the bolts that hold the stack in compression pass. The laminations serve to hold bolts against radial deformation at high speed.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: September 2, 2003
    Assignee: Goodrich Control Systems Limited
    Inventors: David Bonnieman, Dennise R Hayward
  • Patent number: 6614143
    Abstract: An electro active device for generating a directional beam includes first and second electro active substrates each having first and second opposed continuous planar surfaces wherein each of the first opposed surfaces have a polarity and each of the second opposed surfaces have an opposite polarity. The first opposed surfaces of the first and second electro active substrates are in close contact. A first electrode is coupled to a junction formed by the first opposed surfaces having the same polarity, a second electrode is coupled to the second opposed surface of the first electro active substrate, and a third electrode is coupled to the second opposed surface of the second electro active substrate. A first endcap is joined to the second opposed surface of the first electro active substrate and a second endcap is joined to the second opposed surface of the second electro active substrate.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: September 2, 2003
    Assignee: The Penn State Research Foundation
    Inventors: Jindong Zhang, Robert E. Newnham
  • Patent number: 6614144
    Abstract: A multilayer piezoelectric transformer is provided using a composite vibration modes for step-up voltage conversion applications. An input portion polarized to deform radially is bonded to an output portion via a bondline or constraint layer. The deformation of the central face of the input portion is constrained by the bonded output layer or constraint layer. The output layer is bonded to the input layer or constraint layer and also deforms radially. The differing freedom of motion between the layers creates a gradient of stress and strain in the thickness direction resulting in large shear forces along the input and output layers. The composite radial-shear mode deformation of the output portion piezoelectrically generates an efficient, stepped-up high output voltage.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: September 2, 2003
    Assignee: Force International, Corp.
    Inventor: Alfredo Vazquez Carazo