Abstract: A transparent conductive thin film which can be produced easily by sputtering or the like with a sintered target, needs no post-treatment such as etching or grinding, is low in resistance and excellent in surface smoothness, and has a high transmittance in the low-wavelength region of visible rays; and transparent, electroconductive substrate for a display panel and an organic electroluminescence device excellent in light-emitting characteristics, both including the transparent conductive thin film. More particularly, a transparent conductive thin film comprising indium oxide as the major component and silicon as a dopant, having a substantially amorphous structure, wherein silicon is incorporated at 0.5 to 13% by atom on indium and silicon totaled; and a transparent conductive thin film comprising indium oxide as the major component and tungsten and germanium, wherein tungsten is incorporated at a W/In atomic ratio of 0.003 to 0.047 and germanium is incorporated at a Ge/In atomic ratio of 0.001 to 0.190.

Abstract: A novel optical member is disclosed.

Abstract: The specification describes a mobile jack stand power unit for use with a jack stand that is convertible for use as a load-lifting jack. The power unit comprises a generally rectangular mobile chassis having a forward end and a rearward end with a lift means mounted on the chassis including a pushing means, and a pair of parallel lift arms. The lift arms are pivotal within the chassis and have forward ends and rearward ends, with the forward ends adapted to be raised and lowered by the pushing means for use with the jack stand, and are further adapted for use with a lift bridge. A lift bridge is adapted to be positioned on the forward ends of the lift arms whereby the power unit is operable for use as a load-lifting jack; and the bridge is further adapted to be displaced from the forward ends of the lift arms whereby the power unit is operable for use with the jack stand.

Abstract: The specification describes a mobile jack stand power unit for use with a jack stand that is convertible for use as a load-lifting jack. The power unit comprises a generally rectangular mobile chassis having a forward end and a rearward end with a lift means mounted on the chassis including a pushing means, and a pair of parallel lift arms. The lift arms are pivotal within the chassis and have forward ends and rearward ends, with the forward ends adapted to be raised and lowered by the pushing means for use with the jack stand, and are further adapted for use with a lift bridge. A lift bridge is adapted to be positioned on the forward ends of the lift arms whereby the power unit is operable for use as a load-lifting jack; and the bridge is further adapted to be displaced from the forward ends of the lift arms whereby the power unit is operable for use with the jack stand.

Abstract: The specification describes economical lifting devices. A consumer jack comprising a rectangular base; a pair of connecting arms that are pivotally attached to the front end of the base, and a pair of lift arms that are attached to the connecting arms and attached at the rearward ends thereof to a sliding block. A screw-threaded actuator shaft is engaged with the sliding block to raise and lower a lifting pad attached to the forward ends of the lift arms of the device. The components are stamped from steel sheet and plate, and folded into the desired configuration, and assembled without the need for machining or welding.

Abstract: The specification describes a mobile jack stand power unit for use with a jack stand that is convertible for use as a load-lifting jack. The power unit comprises a generally rectangular mobile chassis having a forward end and a rearward end with a lift means mounted on the chassis including a pushing means, and a pair of parallel lift arms. The lift arms are pivotal within the chassis and have forward ends and rearward ends, with the forward ends adapted to be raised and lowered by the pushing means for use with the jack stand, and are further adapted for use with a lift bridge. A lift bridge is adapted to be positioned on the forward ends of the lift arms whereby the power unit is operable for use as a load-lifting jack; and the bridge is further adapted to be displaced from the forward ends of the lift arms whereby the power unit is operable for use with the jack stand.

Abstract: The specification describes a mobile jack stand power unit for use with a jack stand that is convertible for use as a load-lifting jack. The power unit comprises a generally rectangular mobile chassis having a forward end and a rearward end with a lift means mounted on the chassis including a pushing means, and a pair of parallel lift arms. The lift arms are pivotal within the chassis and have forward ends and rearward ends, with the forward ends adapted to be raised and lowered by the pushing means for use with the jack stand, and are further adapted for use with a lift bridge. A lift bridge is adapted to be positioned on the forward ends of the lift arms whereby the power unit is operable for use as a load-lifting jack; and the bridge is further adapted to be displaced from the forward ends of the lift arms whereby the power unit is operable for use with the jack stand.

Abstract: The specification describes a mobile jack stand power unit for use with a jack stand that is convertible for use as a load-lifting jack. The power unit comprises a generally rectangular mobile chassis having a forward end and a rearward end with a lift means mounted on the chassis including a pushing means, and a pair of parallel lift arms. The lift arms are pivotal within the chassis and have forward ends and rearward ends, with the forward ends adapted to be raised and lowered by the pushing means for use with the jack stand, and are further adapted for use with a lift bridge. A lift bridge is adapted to be positioned on the forward ends of the lift arms whereby the power unit is operable for use as a load-lifting jack; and the bridge is further adapted to be displaced from the forward ends of the lift arms whereby the power unit is operable for use with the jack stand.

Abstract: A process for winching comprising attaching a first line to a jack, connecting a second line to the object to be winched, connecting a third line to the running gear of the jack, immobilizing the jack, connecting the third line to the second line and cranking the jack to move the object, and connecting the first line to the second line to hold the object in its new position. Apparatus for holding an object being winched in a new position including a winch tensioner bracket connected to a grab hook by a chain.

Abstract: A fence spool core member has a slot having an open end to permit straddling of a flexible member. A niche adjacent the core open end receives a flange web to trap the flexible fence member in the slot. Torque couplings on the flanges permit rotational displacement of the core in relation to the flexible member. The end flanges include a plurality of peripheral openings that receive pins to retain any rotational displacement of the core in relation to the flexible fence member trapped in the core slot to remove slack from the flexible fence member.

Abstract: An integrated circuit includes a semiconductor device forming a single photon source, and includes a MOS transistor on a silicon substrate. The MOS transistor has a mushroom shaped gate for outputting a single electron on its drain in a controlled manner in response to a control voltage applied to its gate. The transistor also includes at least one silicon compatible quantum box. The quantum box is electrically coupled to the drain region of the transistor, and is capable of outputting a single photon on reception of a single electron emitted by the transistor.

Abstract: A Josephson junction comprises electrodes and intermediate layer provided between the electrodes wherein the electrodes and the intermediate layer are made of the same material but have different conductive states, a superconductor and a usual state conductor which are produced by changing a composition ratio of niobium of a niobium nitride thin film, and nitrogen, by controlling the quantity of nitrogen gas at the time of thin film creation.

Abstract: An organic semiconductor device (11) can be embedded within a printed wiring board (10). In various embodiments, the embedded device (11) can be accompanied by other organic semiconductor devices (31) and/or passive electrical components (26). When so embedded, conductive vias (41, 42, 43) can be used to facilitate electrical connection to the embedded device. In various embodiments, specific categories of materials and/or processing steps are used to facilitate the making of organic semiconductors and/or passive electrical components, embedded or otherwise.

Abstract: In an organic field effect transistor, including, on a substrate having an insulating surface, at least a gate electrode, a gate insulating film formed in contact with the gate electrode, an organic semiconductor film formed in contact with the gate insulating film, and at least a pair of source-drain electrodes formed in contact with the organic semiconductor film, a carrier generating electrode to which carriers can be injected in response to a gate signal is implanted within the organic semiconductor film.

Abstract: The present invention relates to a carrier module for micro-BGA (&mgr;-BGA) type device which is capable of testing a produced device without damaging to a solder ball thereunder after being rapidly connected to a test socket. A carrier module for a BGA type device according to the present invention comprises: an upper and lower carrier module body formed with protrusions at the upper and lower portions thereof; a device receiving unit inserted to the upper carrier module body for receiving a &mgr;-BGA type device; and a spring secured elastically to the upper and lower protrusions by being inserted thereto.

Abstract: A test pattern used for testing an electrical characteristic of a semiconductor substrate, includes: a first conductive pattern formed on a lower surface of the semiconductor substrate; a second conductive pattern formed on an upper surface of the semiconductor substrate; first and second electrodes formed on the second conductive pattern, the electrodes being connected to test probes; and a first test via-hole formed through the semiconductor substrate to connect the first and second conductive pattern electrically to each other.

Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.

Abstract: A semiconductor element which is capable of operating at a high speed, high in an electric current drive capability, and small in fluctuation among a plurality of elements, and a semiconductor device including the semiconductor element are provided. The semiconductor element has a first crystalline semiconductor region including plural crystal orientations without practically having a grain boundary on an insulating surface, the first crystalline semiconductor region being provided to be jointly connected to a conductive region including the first crystalline semiconductor region and a second crystalline semiconductor region, in which the conductive region is provided astride insulating films extending in a linear stripe pattern.

Abstract: An objective is to provide a method of manufacturing a semiconductor device, and a semiconductor device manufactured by using the manufacturing method, in which a laser crystallization method is used that is capable of preventing the formation of grain boundaries in TFT channel formation regions, and is capable of preventing conspicuous drops in TFT mobility, reduction in the ON current, and increases in the OFF current, all due to grain boundaries. Stripe shape or rectangular shape unevenness or opening is formed. Continuous wave laser light is then irradiated to a semiconductor film formed on an insulating film. Note that although it is most preferable to use continuous wave laser light at this point, pulse wave oscillation laser light may also be used.

Abstract: A high-luminance light emitting element is manufactured by a method comprising: forming a light emitting layer on a first surface of a GaP substrate including the first surface and a second surface opposed to the first surface and having an area smaller than the first area, the light emitting layer emitting light of a wavelength &lgr; permitted to pass through the GaP substrate; forming a plurality of side surfaces on the GaP substrate to be respectively aslant by substantially the same angle to become narrower toward the second surface; and forming a plurality of depressions and protrusions as high as 0.1 &lgr; to 3 &lgr; on the side surfaces.

Abstract: A light emitting element, in which voltages having different polarities are applied alternately in order to prevent the accumulation of electric charge in an organic compound layer of the light emitting element, and in which light is always emitted, no matter whether a positive polarity voltage or a negative polarity voltage is applied, is provided. An opposing electrode is formed between a first electrode and a second electrode, and a first light emitting element having a compound layer that contains a first organic substance between the first electrode and the opposing electrode, and a second light emitting element having a compound layer that contains a second organic substance between the opposing electrode and the second electrode, are formed in the present invention.

Abstract: The disclosure is directed toward an optical excitation/detection device that includes an arrayed plurality of photodetectors and discrete photoemitters, as well as a method for making such a device. A CMOS fabricated photodetector array includes an arrayed plurality of photoreceptor areas and photoemitter areas, wherein each photoreceptor area includes a CMOS integrated photoreceptor and each photoemitter area includes at least two buried electric contact pads. The CMOS array is selectively etched back at the locations of the photoemitter areas for regions to reveal the buried contact pads. A plurality of discrete semiconductor photoemitter devices (such as, for example, light emitting diodes) are inserted into, and mechanically retained within, the regions of the CMOS fabricated photodetector array.

Abstract: An optical semiconductor device of the present invention is equipped with a photo detect element 10 comprising a photo detect part 7 provided with two photodiodes having two photodiodes having peak wavelength sensitivity in a visible light region and an infrared region, respectively and a amplifying operation processing circuit 8 for amplifying and processing outputs of the photodiodes, and characterized in that substrate resistivity R is as follows:

Abstract: A high power, high luminous flux light emitting diode (LED) comprises a substrate, a light-emitting structure, a first electrode and a second electrode. The LED has a top surface layout design in which the first electrode has a number of legs extending in one direction, and the second electrode has a number of legs extending in the opposite direction. At least portions of the legs of the first electrode are interspersed with and spaced apart from portions of the legs of the second electrode. This provides a configuration that enhances current spreading along the length of the legs of both electrodes.

Abstract: A method of manufacturing a semiconductor device with the use of a laser crystallization method is provided which can prevent grain boundaries from being formed in a channel forming region of a TFT and which can avoid substantial reduction in TFT mobility, reduction in on current, and increase in off current due to the grain boundaries, and a semiconductor device manufactured by using the manufacturing method is also provided. Stripe shape or rectangular shape unevenness is formed only in a driver circuit. Continuous wave laser light is irradiated to a semiconductor film formed on an insulating film along the stripe unevenness of the insulating film or along a major axis or minor axis of the rectangular unevenness. Although it is most preferable to use the continuous wave laser light at this point, pulse wave laser light may also be used.

Abstract: There are provided two subpixels opposite each other with respect to each data line. A pair of gate lines are provided for each row of pixels. A plurality of subsidiary signal lines are provided between the adjoining columns of the pixels. The data lines and the subsidiary signal lines are alternately arranged between the adjoining columns of the pixels. A storage wire is provided between the adjoining rows of the pixels.

Abstract: The nitride-based semiconductor light-emitting device and manufacturing method thereof are disclosed: the nitride-based semiconductor light-emitting device includes a reflective layer formed on a support substrate, a p-type nitride-based semiconductor layer, a light-emitting layer and an n-type nitride-based semiconductor layer successively formed on the reflective layer, wherein irregularities are formed on a light extracting surface located above the n-type nitride-based semiconductor layer.

Abstract: An ultraviolet type white color light emitting device (Q) including a 340 nm-400 nm ultraviolet InGaN-LED, a first fluorescence plate of ZnS doped with more than 1×1017 cm−3 Al, In, Ga, Cl, Br or I for absorbing ultraviolet rays and producing blue light (fluorescence), a second fluorescence plate of ZnSSe or ZnSe doped with more than 1×1017 cm−3 Al, In, Ga, Cl, Br or I for absorbing the blue light, producing yellow light (fluorescence) and synthesizing white color light by mixing the yellow light with the blue light.

Abstract: A radiation-emitting semiconductor component has a high p-type conductivity. The semiconductor body of the component includes a substrate, preferably an SiC-based substrate, on which a plurality of GaN-based layers have been formed. The active region of these layers is arranged between at least one n-conducting layer and a p-conducting layer. The p-conducting layer is grown in tensile-stressed form. The p-doping that is used is preferably Mg.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

Abstract: A hetero-bipolar transistor according to the present invention enhances reliability that relates to the breaking of wiring metal. The transistor comprises a semiconductor substrate, a sub-collector layer formed on a (100) surface of the substrate, a collector mesa formed on the sub-collector layer, and an emitter contact layer. The transistor further includes a collector electrode and wiring metal connected to the collector electrode. The edge of the sub-collector layer forms a step S, the angle of which is in obtuse relative to the substrate. Therefore, the wiring metal traversing the step S bends in obtuse angle at the step S, thus reducing the breaking of the wiring metal.

Abstract: A first aspect of the invention is to realize a power amplifier having high power adding efficiency and high power gain at low cost. For that purpose, in a semiconductor device using an emitter top heterojunction bipolar transistor formed above a semiconductor substrate and having a planar shape in a ring-like shape, a structure is provided in which a base electrode is present only on an inner side of a ring-like emitter-base junction region. In this way, as a result of enabling to reduce base/collector junction capacitance per unit emitter area without using a collector top structure having complicated fabricating steps, a semiconductor device having high power adding efficiency and high-power gain and suitable for a power amplifier can be realized.

Abstract: A bootstrap circuit includes at least a chargeable semiconductor element region (D3, 6) and a drift region (Rn, 8) of a high-tension island, and junction between the chargeable semiconductor element region and the high-tension island drift region is isolated, and the high-tension island drift region has n+ layers (11, 12) provided at a high-tension side and at an opening portion in an n− semiconductor layer (106) of a high-tension island, and thus an ON operation of a parasitic transistor can be prevented to thereby reduce a current consumption of the circuits.

Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Abstract: In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type is formed over the substrate. A body region of the first conductivity type is formed in the drift region. A source region of the second conductivity is formed in the body region. A gate extends over a surface portion of the body region and overlaps each of the source region and the body region such that the surface portion of the body region forms a channel region of the transistor. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the source region a first predetermined distance. A first buried layer of the first conductivity type extends into the substrate and the drift region. The first buried layer laterally extends between the source and drain regions.

Abstract: A method to obtain thin (less than 300 nm) strain-relaxed Si1−xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 106 cm2. The approach begins with the growth of a pseudomorphic or nearly pseudomorphic Si1−xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operating with this method is dislocation nucleation at He-induced platelets (not bubbles) that lie below the Si/Si1−xGex interface, parallel to the Si(001) surface.

Abstract: A plurality of lands are arranged in rows. The lands in adjacent rows are disposed in a staggered arrangement. A first interconnecting line is pulled out from each of the lands. Each of the lands is wider than the first interconnecting line in the row direction. A plurality of electrical connection sections are arranged in rows. The electrical connection sections in adjacent rows are disposed in a staggered arrangement. The lands are electrically connected with the electrical connection sections so as to overlap. Each of the electrical connection sections is a part of a second interconnecting line, and an insulating layer is formed between the second interconnecting lineing pattern other than the electrical connection sections and the first interconnecting lineing pattern.

Abstract: In a memory and/or data processing device having at least two stacked layers (L) which are supported by a substrate (2) or forming a sandwiched self-supporting structure, wherein the layers (L) comprise memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate (2), the layers (L) are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor (3) is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack.

Abstract: Disclosed is a polished translucent co-extruded sheet having utility as a light diffusing protective cover or sign face for light emitting diode (LED) light sources and other purposes. The sheet is comprised of (a) a particle layer containing particles having a mean particle size of about 4 to 100 microns and having a particle size distribution of between 1-110 microns, at a loading of 1 to 60% melt blended with a thermoplastic matrix, wherein the particle and matrix have refractive indices that differ by greater than 0.001 units of each other when measured in conformance with ASTM D 542; and (b) at least one substrate layer comprised of thermoplastic compositions, wherein the substrates have a refractive index within 0.2 units of the refractive index of the particle layer matrix when measured in conformance with ASTM D 542.

Abstract: The gate threshold voltage is electronically controlled in an insulated gate transistor formed in a semiconductor thin film, such as fully depleted SOI, that is depleted of carriers between first and second principal surfaces. A third semiconductor region of the opposite conductivity type is placed such that it is in contact with the semiconductor thin film. The amount of carriers in the semiconductor thin film is controlled by supplying the semiconductor thin film with carriers of the opposite conductivity type from the third semiconductor region, or by drawing carriers of the opposite conductivity type from the semiconductor thin film into the third semiconductor region.

Abstract: A SnO2 ISFET device and manufacturing method thereof. The present invention prepares SnO2 as the detection membrane of an ISFET by sol-gel technology to obtain a SnO2 ISFET. The present invention also measures the current-voltage curve for different pH and temperatures by a current measuring system. The temperature parameter of the SnO2 ISFET is calculated according to the relationship between the current-voltage curve and temperature. In addition, the drift rate of the SnO2 ISFET for different pH and hysteresis width of the SnO2 ISFET for different pH loop are calculated by a constant voltage/current circuit and a voltage-time recorder to measure the gate voltage of the SnO2 ISFET.

Abstract: A solid state image sensor has an array of pixels formed on an epitaxial layer on a substrate. Each pixel is relatively large so that it has a high light collecting ability, such as 40-60 &mgr;m, but the pixel photodiode is relatively small so that it has a low capacitance, such as 4-6 &mgr;m. Active elements of the pixel photodiode are formed in wells that are spaced away from the pixel photodiode so that the latter is surrounded by epitaxial material.

Abstract: A thermally-stable ferroelectric memory is provided. The ferroelectric memory includes a lower electrode and a ferroelectric layer formed on the top surface of the lower electrode such that a domain having a dielectric polarization is set as a bit. The thickness of the ferroelectric layer is not greater than the size of the bit. Accordingly, a non-volatile ferroelectric memory which is thermally stable is provided, thereby realizing a reliable memory which can store information at high speed and high density and has improved memory retention.

Abstract: A magnetic random access memory (MRAM) is disclosed, which achieves high integration by forming second word lines that serve as two write lines for one pair of MRAMs. A contact plug is formed by connecting the second word line to a metal wire formed above the bit lines. As a result, the bit lines and the contact plug are used to drive the device, thereby achieving high integration of the device.

Abstract: Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.

Abstract: Structures and method for an open bit line DRAM device are provided. The open bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. In each memory cell a single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions, and a gate opposing the vertical body region and separated therefrom by a gate oxide.

Abstract: A metal-insulator metal (MIM) capacitor structure has a copper layer within a dielectric layer positioned on a substrate, an alloy layer atop the copper layer, a metal oxide layer atop the alloy layer and a top pad layer atop the metal oxide layer.

Abstract: A semiconductor device in which an electrode is not allowed to easily deform even when a heat treatment is performed on a material forming the electrode during a damascene process for forming a stacked capacitor, and a manufacturing method thereof are provided. A conductive film 5 made of the same material as that of a capacitor lower electrode 6 is formed so as to be adhered to a top face of a conductive film 4 by a heat treatment. If the lower electrode 6 is made of a noble metal such as ruthenium, for example, the conductive film 5 is made of the same noble metal. Because of use of the same material for forming the conductive film 5 and the lower electrode 6, connection between the conductive film 5 and the lower electrode 6 is strengthened. Accordingly, it is easy to maintain connection between the conductive film 5 and the lower electrode 6 during a heat treatment on the lower electrode 6, so that the lower electrode is not likely to deform.

Abstract: There are provided a first insulating film formed over a semiconductor substrate, an adhesion layer formed on the first insulating film and made of titanium oxide having grains a width of which is larger than a height, a capacitor lower electrode formed on the adhesion layer and containing a noble metal, a capacitor dielectric film formed on the capacitor lower electrode and made of ferroelectric material, and a capacitor upper electrode formed on the capacitor dielectric film.