Abstract: A system and method are provided for replacing dedicated external termination resistors typically used to implement an asymmetrical unidirectional bus I/O standard with programmable resistances that are dynamically selected by programming output driver circuits having digitally controlled impedances.

Abstract: A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.

Abstract: A domino logic circuit is configured to reduce power consumption. In a first embodiment, a sleep switch grounds the dynamic node during sleep mode. In a second embodiment, a low-swing circuit at the output reduces the output and keeper transistor gate voltage swings. A third embodiment combines those two techniques.

Abstract: In a dynamic circuit, when only between a precharge node and an intermediate node through a plurality of logical-operating MOS transistors is conducted, the potential of the precharge node approximately drops to High*{C1/(C1+C2)} from High, where C1 represents the capacitance of the precharge node and C2 represents the capacitance of the intermediate node. Thereafter, with the charge from a power supply, the precharge node returns to High. At this charge sharing time, the amount of charge supply from the power supply is adjusted to suppress voltage drop of the precharge node, thereby reducing noise.

Abstract: Disclosed is an impedance comparison integrated circuit. The integrated circuit includes a current mirror part, a discharging part, a differential amplification part and a first output part. The current mirror part provides current to a first and second input terminal, respectively, during a first interval of every period. The discharging part provides a discharging path to the first and second input terminals, respectively, during a second interval of every period. The differential amplification part performs a differential amplification on signals input from the first and second input terminals, respectively, during the first interval of every period. The first output part outputs a first output signal to the first output terminal in response to the differential amplification part. Accordingly, parasitic impedance difference between each parasitic impedance of the first and second input terminals is minimized, and input offset error is reduced, so that impedance sensing with high precision is possible.

Abstract: A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.

Abstract: There is provided a clock multiplication circuit simple in configuration, easy to adjust the characteristics thereof, and capable of shortening lockup time. The clock multiplication circuit is a circuit for delivering an output clock signal at a frequency that is a multiple of the frequency of a reference clock signal as inputted. A counter of the circuit counts the number of rising edges of the output clock signal ST existing during a High level period of the reference clock signal SR, thereby delivering a count value CN. A subtracter subtracts the count value CN from a reference value BN, thereby delivering a difference value DN. An adder adds the difference value DN to a preceding integrated value IN, thereby calculating a new integrated value IN. A DA converter delivers the analog control voltage AV corresponding to the integrated value IN. A VCO delivers the output clock signal ST at a frequency corresponding to the analog control voltage AV.

Abstract: A circuit for controlling an initializing circuit in a semiconductor device is described herein. The circuit comprises a first circuit configured to generate a NOP operation command signal, and a second circuit configured to maintain a power-up signal to a LOW state until the NOP operation starts and to shift the power-up signal to a HIGH state based on the NOP operation command signal.

Abstract: In accordance with an embodiment of the disclosed matter, a voltage regulator may supply power to a component within a computer system. A timer may be provided. The voltage regulator may operate synchronously, and when the timer expires the voltage regulator may operate non-synchronously. For one embodiment, the voltage regulator may operate non-synchronously when the timer expires and the component is in a sleep state.

Abstract: A delay locked loop (DLL) clock generator circuit is provided for generating a clock signal Clk according to a pair of input signals to the circuit. One of the input signals is a reference signal, and the second input signal is a feedback signal of a voltage controlled delay line circuit. The DLL circuit includes a phase detector that can be reset to expand the locking range for detecting a phase difference between the reference signal and the feedback signal. Based on the detected phase difference, the phase detector provides an output signal that is further processed by the DLL circuit to generate a number of delayed signals to a frequency multiplier. Using the delayed signals, the frequency multiplier generates a frequency multiplied clock signal having a frequency that is a multiple of the frequency of the reference signal.

Abstract: A phase difference between a feedback clock signal corresponding to an internal clock signal generated via a variable delay line and a buffered clock signal corresponding to an external clock signal is detected by a phase detector, and a result of detection is transferred via a shifting circuit. When a down signal from the shifting circuit is activated by a delay control circuit, the down instruction signal is forcibly maintained to be active for a predetermined clock cycle period. When the down instruction signal becomes inactive from the active state, a count control circuit sets a count unit of the counting circuit to the minimum value. The delay amount of the variable delay line is set according to an output count bit of the counting circuit. Therefore, it is possible to reduce the number of clock cycles required until an internal clock signal is synchronized in phase with the external clock signal.

Abstract: A semiconductor device includes an external resistor for establishing a delay of a signal relative to another signal in the device. The resistor may be external to a buffer, such as a zero-delay buffer, that receives an input signal generates one or more output signals that relate to the input signal. The delay may be introduced either before or after the buffer.

Abstract: A clock extracting part has a first phase comparator circuit, a first up/down counter, a weighting circuit, a charge pump and a low-pass filter forming a voltage value determining part, and a voltage controlled oscillator circuit. A retiming clock generating part has a second up/down counter and a phase switching circuit. Furthermore, a phase adjusting part has a first counter, a second counter, a second phase comparator circuit and a third up/down counter forming a phase adjusting part. A clock data recovery circuit is formed by said clock extracting part, the retiming clock generating part, the phase adjusting part, and a first-in first-out memory part. Thereby, a clock data recovery circuit is obtained, in which jitter transfer characteristics and jitter tolerance satisfy the standards of both the SONET and SDH.

Abstract: According to some embodiments, a reference voltage signal initially increases with increases in a processor voltage signal and then decreases with a further increase in the processor voltage signal. Moreover, according to some embodiments a comparator circuit generates a power indication signal when a substantially scaled processor voltage signal exceeds a reference voltage signal.

Abstract: Provided is a flip-flop capable of operating at high speed by reducing a clock-to-output delay. The flip-flop includes a sense amplifier and a latch circuit. The sense amplifier includes a first node and a second node, precharges the first node and the second node with a supply voltage according to a state of a clock signal, or receives and amplifies differential input signals according to the state of the clock signal, so as to output differential output signals to the first node and the second node. The latch circuit is connected to the first node and the second node, and detects and latches the differential input signals according to the state of the clock signal and the differential output signals. The flip-flop described above does not use a NAND gate, so that a clock-to-output delay can be reduced. Therefore, the flip-flop has an advantage of operating at high speed.

Abstract: An adjustable logic circuit includes a pulse filter and delay circuit, a state machine and combinational logic circuit, and a data strobe generation circuit. The pulse filter and delay circuit is operative to read an adjustable configuration value and, based thereon, to implement a delay between an internal clock and both a data signal and a data strobe signal, the delay being a fraction of a clock period. The state machine and combinational logic circuit are operative to select a data value from a plurality of data values, and to provide a data signal based upon the data value. The data strobe generation circuit is operative to provide the data strobe signal at a time when both the data signal is valid and the delay is compatible with a predetermined external device.

Abstract: In the clamp circuit, the first transistor shifts a target clamp voltage by a gate-source voltage to output the target clamp voltage. The buffer circuit inputs the shifted voltage and output a reference voltage on the inputted shifted voltage. The gate of the second transistor is connected to the output terminal of the buffer circuit. The source of the second transistor is connected to the input terminal of the first transistor. In this structure, the reference voltage is supplied to the gate of the second transistor so that, when a terminal voltage of the input terminal of the IC is not less than a clamp voltage corresponding to the sum of the reference voltage and a threshold voltage of the second transistor, the second transistor turns on, whereby the terminal voltage is clamped to a clamp voltage related to the target clamp voltage.

Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1−M3; M1−M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.

Abstract: A transistor causes fluctuation in the threshold and mobility due to the factor such as fluctuation of the gate length, the gate width, and the gate insulating film thickness generated by the difference of the manufacturing steps and the substrate to be used. As a result, there is caused fluctuation in the current value supplied to the pixel due to the influence of the characteristic fluctuation of the transistor, resulting in generating streaks in the display image. A light emitting device is provided which reduces influence of characteristics of transistors in a current source circuit constituting a signal line driving circuit until the transistor characteristics do not affect the device and which can display a clear image with no irregularities. A signal line driving circuit of the present invention can prevent streaks in a displayed image and uneven luminance.

Abstract: A circuit is provided to make the propagation delay time of each signal path substantially the same without using a low resistance process even when wiring lengths are different. In the circuit, output nodes a to d are individually disposed at the output side of transmission gates TG2, TG4, TG6, and TG8, these output nodes a to d are connected so as to have an equal wiring length, inverters IV11 and IV12 are disposed at the output nodes a and d, and a common node e is disposed at a position where the wiring length from each of the inverters IV11 and IV12 becomes identical.

Abstract: To reduce degradation of image quality when constructing anode line drive circuits in a display panel drive circuit from a plurality of IC chips.

Abstract: A semiconductor integrated circuit with stabilizing capacity has a voltage drop circuit that drops a power supply voltage to a first voltage Vcc1 and supplies the Vcc1 to a plurality of function blocks; a stabilizing capacity that stabilizes the Vcc1; and a plurality of voltage switching circuits each of which is provided in each of the function blocks and selectively switches between the Vcc1 and a base voltage Vss to produce a second voltage Vcc2 and supplies the Vcc2 to each function block, and each of the function blocks forms a capacity for stabilizing an output of the voltage drop circuit by means of its semiconductor structure by the Vcc1 and the Vcc2 applied thereto.

Abstract: A VBB control circuit includes an intermediate potential generation circuit receiving a substrate potential VBB which is a negative potential and outputting a divided potential between a power supply potential INTVDD and a ground potential, and an inverter receiving the divided potential and determining whether the substrate potential is higher or lower than a desired value. A logic threshold value of the inverter is (½)×INTVDD. If a relationship of VBB=VREFB−(½)×INTVDD is satisfied, the divided potential accurately becomes (½)×INTVDD. Thereby, it is possible to realize a semiconductor device including a detection circuit which can arbitrarily select a detected potential of the VBB by changing VREFB and which is less influenced by a change in manufacturing conditions.

Abstract: A voltage regulator with dynamically boosted bias current includes a pass device for providing current to a load; an error circuit responsive to a difference between a predetermined reference voltage and a function of the voltage on the load to produce an error signal, a driver circuit responsive to the error signal for controlling the pass device to adjust the current to the load to reduce the error signal, the driver circuit including an amplifier responsive to the error signal for controlling the pass device, a bias current source for biasing the amplifier, a sensing circuit for sensing a portion of the error signal, a reference current source for providing a reference current, a second error circuit responsive to a difference between the portion of the error signal and the reference current to produce a second error current; and a boost circuit responsive to the second error signal to increase the bias current provided to the amplifier when the load demands more current.

Abstract: A boosting circuit is disclosed.

Abstract: In a power supply circuit, a main transistor, which transmits power from an input terminal to an output terminal, is controlled so that a detected voltage from an input voltage is consistent with a reference voltage indicating a target voltage. An output current is detected and a limited value of the output current is set so that the limited value increases gradually when the output voltage rises up to the target voltage. The main transistor is controlled so that the output current keeps a value less than or equal to the limited value. This configuration is able to suppress an overshoot of the output voltage, thanks to a gradually raised control of the limited value. Additionally, to avoid the influence of a ringing component of the input voltage, a delay control circuit to give a delay to the start of rise of the output voltage can be provided.

Abstract: A reference voltage generator includes an output node, a current supply circuit including a first resistor, a second resistor, and a transistor. The current supply circuit is connected to the output node. The first resistor has a first temperature coefficient. The current supply circuit supplied a current corresponding to a value of resistance of the first resistor to the output node. The second resistor is connected to the output node. The second resistor has a second temperature coefficient that is larger than the first temperature coefficient. The transistor is connected to the second resistor. The transistor is supplied with the current from the output node through the second resistor.

Abstract: The present invention proposes a power amplification under variable envelope excitation, wherein an original input signal at least is converted into a phase modulated signal part, at least the phase modulated signal part is fed to an input port of an amplifier unit, the input signal is amplified by dynamically selecting a fixed power supply (PSU 1, PSU 2, PSU 3) for the amplifier unit, and wherein the amplitude content of the original input signal is reconstructed by changing dependent on the respective provided power supply a further controllable input of the amplifier unit, in particular the input power level (Pin) and/or the biasing voltage (Ug) and/or biasing current at the control input of the amplifier unit, during said step of amplifying.

Abstract: A power amplifier circuit includes a power amplifier responsive to a power mode signal, the power amplifier having a power amplifier output node, and a power amplifier load circuit also responsive to the power mode signal, the power amplifier load circuit having a load circuit input node connected to the power amplifier output node. The power amplifier load circuit has a first transmission line coupled between the load circuit input node and a first node, a harmonic filter coupled between the load circuit input node and a common node, a first capacitor coupled between the first node and the common node, and a first switch coupled between the common node and ground, where the first switch is responsive to the power mode signal.

Abstract: An inline predistortion circuit for producing composite second order (CSO) and composite triple beat (CTB) distortion correction of a laser transmitter is disclosed having an RF input signal, a diode for producing nonlinear current, and a DC voltage bias for controlling the nonlinear current. The predistortion circuit lacks DC blocking capacitors between the RF attenuator and the diode, which results in improved nonlinear current generation across a wide frequency range. A capacitor in parallel with the bias circuit further increases diode's capability for producing nonlinear current. A low resistance resistor in series with the RF signal path and in parallel with the diode provides the voltage necessary for the diode to conduct while minimizing RF signal attenuation. An inductor in series with the RF signal provides improved phase correction of the CSO and CTB predistortion circuit.

Abstract: An operational amplifier has a bias circuit, a differential amplifier, an output stage, and a feed forward circuit. The bias circuit provides a reference. The differential amplifier is coupled to a pair of input terminals and provides a differential output based on the first and second inputs. The output stage responds to the reference and to the differential output so as to supply a current to an output terminal. The feed forward circuit responds to the differential output in order to increase and decrease current to the output terminal. As a result, the feed forward circuit extends the dynamic range of the operational amplifier.

Abstract: In one system embodiment, the system is characterized by: a differential amplifier including but not limited to at least one amplifying transistor having an emitter coupled directly to a ground. In one embodiment of a method of making a system, the method is characterized by: operably coupling at least one amplifying transistor of a differential amplifier directly to a ground. In one embodiment of a method of driving a system, the method is characterized by: driving at least one amplifying transistor of a differential amplifier with an emitter-follower feedback loop. In one system embodiment, the system is characterized by: a differential amplifier including but not limited to a first amplifying transistor having a base operably coupled with a first emitter-follower feedback loop.

Abstract: A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.

Abstract: A clock recovery circuit capable of automatically adjusting the frequency range of a voltage-controlled oscillator (VCO) is proposed. The clock recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency counter, and a frequency control unit. The phase detector receives an input signal, such as EFM clock, and a VCO clock and outputs a control signal according to phase differences between the EFM clock and the VCO clock. The charge pump controls the charge action according to the control signal. The loop filter is connected to the charge pump and cooperates with the charge pump to output a voltage signal. The voltage-controlled oscillator receives the voltage signal from the loop filter and outputs the VCO clock. The frequency counter counts the frequency of the VCO clock and outputs an oscillation frequency.

Abstract: A phase detector for a delay locked loop with a delay unit that delays a periodic clock signal by a settable delay, has a first input for the periodic clock signal, a second input for the delayed clock signal, an UP output and a DOWN output. The phase detector outputs a first pulse signal at the UP output and a second pulse signal at the DOWN output, which signals can respectively assume a first or a second level, for the setting of the delay unit. The first pulse signal changes to the first level in the event of a positive edge of the clock signal and the second pulse signal changes to the first level in the event of a positive edge of the delayed clock signal. In the event that both pulse signals are at the first level, a reset device resets both pulse signals to the second level.

Abstract: An oscillation apparatus has a multi-mode dielectric resonant element; a plurality of oscillation circuits, each including a line coupled to the dielectric resonant element and active devices connected to ends of the line; and a substrate having the lines and the active devices provided thereon. The dielectric resonant element is placed on the substrate. The magnetic fields, occurring in the dielectric resonant element, in a plurality of resonant modes having different resonant frequencies are coupled to the corresponding lines in the plurality of oscillation circuits.

Abstract: An adjustable frequency oscillator circuit includes: an odd number of inverters connected so as to form a loop; a plurality of capacitive elements each connected to an output terminal of a respective inverter; and an output terminal, which supplies a signal oscillating at an oscillating frequency. The oscillator circuit further includes a calibration circuit for calibrating maximum currents which can be delivered by the inverters to the respective capacitive elements.

Abstract: An amplitude control device for a signal output by an oscillator includes a rectification circuit for rectifying the output signal, and a differential amplification circuit for generating a biasing current control signal for the oscillator. The biasing current control signal is based upon the output signal from the rectification circuit and a reference voltage. A dividing bridge and an adder are designed so that only a fraction of the reference voltage is used to define the amplitude of the oscillations. The contribution made to the oscillator phase noise by the reference voltage noise is considerably reduced.

Abstract: A system for generating in-phase and quadrature phase signals is provided. The system includes a first and a second differential output, such as from a sinusoidal oscillator. A first injection-locked frequency divider, such as one that uses an LC oscillator in conjunction with cross-coupled transistors, receives the first differential output and generates a in-phase or in-phase output. A second injection-locked frequency divider receives the second differential output and generates a quadrature phase output.

Abstract: A non-reciprocal circuit element has a yoke including a top yoke component and a bottom yoke component. The yoke includes a magnetic plate, line conductors, capacitor chips disposed around the magnetic plate, and a magnet for applying a bias magnetic field. The line conductors intersect on the main surface of the magnetic plate. Each end of the line conductors is connected to the corresponding capacitor chip. The magnet has a major axis and a minor axis, and further has a convex surface on at least one peripheral portion thereof.

Abstract: An arrangement for bypassing a low-noise amplifier (LNA), intended especially to be used in base stations of mobile networks. For the bypass, a receiver antenna filter (210) has a second output (OUT2) parallel with a first output (OUT1) connected to the LNA. The antenna filter is of the resonator type, and there is a conductive element for each of its outputs in the resonator cavity. Selection between the LNA output signal and signal coming direct from the antenna filter is made by a changeover switch (SW). The noise figure of the receiver front stage (220) will improve as the series switch on the signal path, which most degrades the noise figure, is removed between the filter and LNA, and isolation on the LNA bypass path increases.

Abstract: A constant impedance filter maintains a constant input impedance for frequencies that are both inside the filter passband and outside the filter passband. The constant input impedance appears as a pure resistance. The constant impedance filter includes a plurality of filter poles that are connected in series. Each of the filter poles include an inductor, a capacitor, and a resistor. The value of the inductor, the capacitor, and the resistor are selected to provide a constant input impedance over frequency for each pole of the filter, which produces a constant input impedance for the entire filter over frequency. The constant impedance filter can be implemented as a low pass filter, a high pass filter, or a bandpass filter. Furthermore, the constant impedance filter can be implemented in a single-ended configuration or a differential configuration.

Abstract: An inductor equivalent circuit is disclosed. The circuit comprises a reference current source, a first current mirror, a second current mirror, two operational amplifiers OP1 and OP2, a capacitor, a first transistor, a second transistor, a mirror resistor set, and a bypass current source in parallel with the capacitor. An input signal is through OP1 and second transistor to control the reference current source. The first mirror current is then feed-back a signal to the first transistor through an OP2. The current signal makes the drain current of the first transistor lags the input voltage signal by 90° due to the capacitor coupled with the first mirror current source.

Abstract: This application discloses a microelectromechanical (MEMS) switch apparatus comprising an anchor attached to a substrate and an electrically conductive beam attached to the anchor and in electrical contact therewith. The beam comprises a tapered portion having a proximal end and a distal end, the proximal end being attached to the anchor, an actuation portion attached to the distal end of the tapered portion, a tip attached to the actuation portion, the tip having a contact dimple thereon. The switch apparatus also includes an actuation electrode attached to the substrate and positioned between the actuation portion and the substrate. Additional embodiments are also described and claimed.

Abstract: A circuit breaker includes a switching mechanism, a manual operating handle connected to the switching mechanism, and an instantaneous tripping device for detecting a short circuit current and opening contacts of a main circuit. The instantaneous tripping device and a latch receiver of the switching mechanism are connected with each other via a trip member capable of sliding up and down. Further, the circuit breaker includes a trip indicating member moving along with the trip member, and a trip indicating window formed in a breaker housing and facing the trip indicating member. The trip indicating member moves to an indicating position to visually indicate a tripping state of the circuit breaker through the trip indicating window when the circuit breaker member instantaneously trips.

Abstract: A high life cycle and low voltage MEMS device. In an aspect of the invention, separate support posts are disposed to prevent a suspended switch pad from touching the actuation pad while permitting the switch pad to ground a signal line. In another aspect of the invention, cantilevered support beams are made from a thicker material than the switching pad. Increased thickness material in the cantilever tends to keep the switch flat in its resting position. Features of preferred embodiments include dimples in the switch pad to facilitate contact with a signal line and serpentine cantilevers arranged symmetrically to support the switch pad.

Abstract: An apparatus of the present invention comprises a coupling unit that provides the coupling between a valve element of an opening-closing valve and a moving element of an electromagnetic actuator so as to enable mutual movement of the two elements relative to each other within a predetermined restricted range. Accordingly, it is possible to provide an opening-closing valve driving apparatus that can reduce power consumption of the electromagnetic actuator and is excellent in responsivity.

Abstract: An electromagnetic transducer is described including a magnet assembly (50) and a conductive drive coil (52). The magnet assembly provides an emanating magnetic field within which the drive coil is located. The drive coil is a flat ring coil having a width that is equal to or greater than its height. As assembled, the drive coil is mounted in close proximity to the magnet assembly such that relative axial motion may occur between them during use. In one embodiment, the magnet assembly includes two permanent disc magnets (64), (66) having axial magnetizations and being oriented with like poles facing one another to produce a radially emanating magnetic field. In another embodiment, the magnet assembly includes a pair of axially magnetized permanent ring magnets (64), (66) also oriented with like poles facing one another.

Abstract: A proximity sensor according to the present invention includes protrusions that are provided on a wire-winding drum of a coil spool around which a lead wire of a detection coil is wound, that protrude toward the center from not less than three points distributed in the range exceeding a semi-circle on the circumference of the wire-winding drum and that are elastically brought into contact with the shaft of the core, respectively, thereby coaxially positioning the coil spool and the shaft of the core.

Abstract: A security system including a vehicle based security manager processor and a communications module linked to the security manager processor. The communications module is capable of communicating to a remote call center by way of an internet communication link. If certain security protocols are breached, the call center communicates a shutdown command to the vehicle by way of the internet communications link and the vehicle initiates a shutdown procedure for incapacitating the vehicle.