Abstract: A semiconductor light emitting device gives a large radiation surface with an enhanced light radiating capability. A N-type GaN layer and a P-type GaN layer are stacked to define therebetween an interface where a light is generated upon application of voltage across the interface. A light guide on which the GaN layers are developed is utilized to give a wide radiation surface from which the light is given off. The radiation surface is formed with a refractor layer composed of an array of a first medium and a second medium which have individual refraction indexes different from each other and are arranged alternately across the radiation surface. Thus, the light guide can be best utilized to give a large radiation surface, yet formed with the refractor layer which reduces multiple reflections inside of the light guide for effectively passing or radiating the light transmitted through the light guide.

Abstract: An increased proportion of light projected from a nitride semiconductor light emitting diode enters the area within a specified angle. The nitride semiconductor light emitting diode is provided with an active layer 32 consisting of a nitride semiconductor, and a light projecting face 21. A reflecting mirror 38 is formed only on a side of the active layer 32 opposite the light projecting face 21. The reflecting mirror 38 is formed at a location from the center of the active layer 32 approximately (k·&lgr;/2+&lgr;/4)/n (where &lgr; is the wavelength of light projected from the active layer 32, n is the mean refractive index of an area between the active layer 32 and the reflecting mirror 38, and k is an integer). This light emitting diode allows directivity to be increased sufficiently, and the coupling efficiency thereof with optical fiber consisting of POF or the like can be improved.

Abstract: A light emitting assembly comprising a solid state device coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first, relatively shorter wavelength radiation, and a down-converting luminophoric medium arranged in receiving relationship to said first, relatively shorter wavelength radiation, and which in exposure to said first, relatively shorter wavelength radiation, is excited to responsively emit second, relatively longer wavelength radiation. In a specific embodiment, monochromatic blue or UV light output from a light-emitting diode is down-converted to white light by packaging the diode with fluorescent organic and/or inorganic fluorescers and phosphors in a polymeric matrix.

Abstract: Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

Abstract: A semiconductor device includes a semiconductor substrate, a metal layer formed on a surface of the semiconductor substrate, an electrode formed such that the electrode covers the metal layer, edges of the electrode being in ohmic contact with the semiconductor substrate, a via hole formed right under the metal layer, the via hole having a depth reaching the metal layer from a reverse side of the semiconductor substrate, and a ground electrode formed on an inside surface of the via hole and the reverse side of the semiconductor substrate, the ground electrode being connected to the electrode through the metal layer.

Abstract: This invention provides a hetero-junction bipolar transistor (HBT) having a large base-collector breakdown voltage. The HBT has a collector, a base and an emitter. The emitter is made of a semiconductor material whose band gap energy is greater than that of the base. An passivation layer made of a semiconductor material cover the collector, the base and the emitter and the band gap energy of the passivation layer is greater than that of the collector and the base.

Abstract: A through hole tapered from an opening to the in-depth direction is formed in a semiconductor substrate provided with an integrated circuit. An insulating material is supplied to the through hole through the opening so as to form an insulating layer on the inner surface of the through hole. A conductive material is supplied through the opening to the through hole provided with the insulating layer so as to form a conductive portion inside the insulating layer.

Abstract: A system for writing data to and reading data from a magnetic medium utilizing a spin polarized electron beam.

Abstract: A method for fabricating buried decoupling capacitors in an integrated circuit is disclosed. The method forms decoupling capacitors by creating an opening within a substrate which has fin-like spacers, depositing a dielectric material over the spacers, depositing an electrode material over the dielectric material, depositing an insulative material over the electrode material, and forming integrated circuit components over the insulative material.

Abstract: A P channel vertical conduction Rad Hard MOSFET has a plurality of closely spaced base strips which have respective sources to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base stripes are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. A P type enhancement region is implanted through spaced narrow windows early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) P channel device with very low gate capacitance and very low on resistance.

Abstract: It is an object to provide a semiconductor device in which a structure of a capacitor is simplified. Any electrical connection of a capacitor (CP10) and source-drain regions (11) and (13) is carried out by a contact plug (101) inserted in the capacitor (CP10) and reaching the source-drain regions (11) and (13). The capacitor (CP10) has a capacitor upper electrode (103) provided to be embedded in an upper main surface of an interlayer insulating film (3) and a capacitor dielectric film (102) provided to cover a side surface and a lower surface of the capacitor upper electrode (103). Moreover, the capacitor dielectric film (102) is also provided to cover a side surface of the contact plug (101) formed to penetrate through the capacitor upper electrode (103), and a portion of the contact plug (101) which is covered with the capacitor dielectric film (102) functions as the capacitor lower electrode (101).

Abstract: In accordance with the present invention, a memory cell includes a non-volatile device and a DRAM cell. The DRAM cell further includes an MOS transistor and a capacitor. The non-volatile device include a control gate region and a guiding gate region that may partially overlap. The non-volatile device is erased prior to being programmed. Programming of the non-volatile device may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM is loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile device is restored in the DRAM cell.

Abstract: A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Abstract: A semiconductor device includes: a semiconductor substrate; a bonding pad having an interconnection region that provides for an external electrical contact; a first interlayer insulating layer interposed between the semiconductor substrate and the bonding pad; and a metal wiring layer that is embedded in the first interlayer insulating layer. The metal wiring layer is made of a softer material than that of the first interlayer insulating layer. The metal wiring layer at least partially overlaps with the interconnection region in the stacked direction of the layers, and the area of metal wiring layer overlapping with the interconnection region includes notches that extend through the metal wiring layer in the stacked direction and separate the metal wiring layer in the layer direction. Portions of the first interlayer insulating layer are embedded in the notches.

Abstract: A non-volatile multiple bit memory (10, 50) has electrically isolated storage elements (17, 21, 78, 80) that overlie a channel region having a central area (24, 94) with high impurity concentration. A planar gate (30, 84) overlies the storage elements. The high impurity concentration may be formed by a centrally located region (24) or by two peripheral regions (70, 72) having lower impurity concentration than the central portion of the channel. During a read or program operation, the channel area of high impurity concentration effectively controls a channel depletion region to enhance reading or programming of stored data bits. During a hot carrier program operation, the channel area of high impurity concentration enhances the programming efficiency by decreasing leakage currents in a memory array.

Abstract: A semiconductor device of this invention comprises a semiconductor substrate, a plurality of memory regions provided on the semiconductor substrate, the plurality of memory regions having the same structure, and functional region provided on the semiconductor substrate, the functional region including a different function from the memory.

Abstract: In a method of forming a ferroelectric film according to the present invention, pulsed laser light or pulsed lamp light is applied to an amorphous oxide film formed over a substrate to form microcrystalline nuclei of oxide in the film. Crystallization of the oxide is performed by applying pulsed laser light or pulsed lamp light to the film including the microcrystalline nuclei to form the ferroelectric film.

Abstract: A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

Abstract: A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.

Abstract: The scalable stack-type DRAM memory structure of the present invention comprises a scalable DRAM transistor structure and a scalable DRAM capacitor structure. The scalable DRAM transistor structure comprises a plurality of transistor-stacks, a plurality of common-drain regions, and a plurality of source regions being formed over a shallow-trench-isolation structure without a dummy-transistor structure by using a spacer-formation technique. The scalable DRAM capacitor structure comprises a plurality of rectangular tube-shaped cavities being formed over thin fourth conductive islands to form a high-capacity DRAM capacitor for each of DRAM cells; and a plurality of planarized conductive contact-islands over planarized third conductive islands being patterned and simultaneously etched with a plurality of bit-lines for forming a contactless DRAM memory. The cell size of a DRAM cell is scalable and can be made to be smaller than 6F2.

Abstract: An insulating film with a linear concave portion is formed and a semiconductor film is formed thereon by deposition. The semiconductor film is irradiated with laser light to melt the semiconductor film and the melted semiconductor is poured into the concave portion, where it is crystallized. This makes distortion or stress accompanying crystallization concentrate on other regions than the concave portion. A surface of this crystalline semiconductor film is etched away, thereby forming in the concave portion a crystalline semiconductor film which is covered with side walls of the concave portion from the sides and which has no other grain boundaries than twin crystal. TFTs and memory TFTs having this crystalline semiconductor film as their channel regions are highly reliable, have high field effect mobility, and are less fluctuated in characteristic. Accordingly, a highly reliable semiconductor memory device which can operate at high speed is obtained.

Abstract: A semiconductor device includes: an n+ type drain region; an n type drift region that connects with the n+ type drain region; a p type body region; a n+ type source region that connects with the p type body region; and a gate electrode that is provided, with being covered by a gate insulation film, in a gate trench that penetrates the p type body region. The semiconductor further includes: a p type silicon region that adjoins the n type drift region; and an n type silicon region provided in a region almost including a carrier passage that connects the n type drift region and the p type body region. Here, the p type silicon region and the p type body region directly connect with each other.

Abstract: A capacitor for sensing a substrate voltage in an integrated circuit power device may be implemented by isolating a portion or segment of the metal layer that normally covers the heavily doped perimeter region typically used for electric field equalization. In conjunction, one or more portions of an isolation dielectric layer of silicon oxide are not removed from the surface of the semiconductor substrate, as is commonly done before depositing the metal layer. The portions of isolated silicon oxide which are not removed become the dielectric layer of the capacitor. Moreover, one plate of the capacitor is formed by the heavily doped perimeter region that is electrically connected to the substrate (e.g. a drain or collector region). The other plate is formed by the segment of metal isolated from the remaining metal layer defined directly over the heavily doped perimeter region.

Abstract: A method of manufacturing a semiconductor device, such as a double-diffused metal oxide semiconductor (DMOS) transistor, where a first layer may be formed on a semiconductor substrate, with isolation trenches formed in the first layer and semiconductor substrate, and with the trenches being filled with an isolation layer. A second layer may be formed on the first layer and semiconductor substrate, and a plurality of drain trenches may be formed therein. A pair of plug-type drains may be formed in the trenches, to be separated from the isolation layer by a dielectric spacer. Gates and source areas may be formed on a resultant structure containing the plug-type drains. Accordingly, current may be increased with a reduction in drain-source on resistance, and an area of the isolation layer can be reduced, as compared to an existing isolation layer, potentially resulting in a reduction in chip area.

Abstract: There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowable dielectric layer covering an upper surface of the particulate insulating layer, the insulating particles being stable at the melting point or the softening point of the reflowable dielectric layer.

Abstract: Methods of forming vertical MOSFETs include forming a base region of second conductivity type in a semiconductor substrate having a drift region of first conductivity type therein that forms a P-N junction with the base region. A source region of first conductivity type is formed in the base region and a deep trench, having a first sidewall that extends adjacent the base region, is formed in the substrate. The deep trench is lined with a first electrically insulating layer. The deep trench is then refilled with a trench-based source electrode. The trench-based source electrode is selectively etched to define a shallow trench therein and expose a first portion of the first electrically insulating layer that extends on the first sidewall of the deep trench. The first portion of the first electrically insulating layer is selectively etched to expose an upper portion of the first sidewall of the deep trench and reveal the base region.

Abstract: A plurality of trenches for defining active regions are formed in a semiconductor substrate, using a plurality of trench masks. A gap fill insulating layer is formed on the resulting structure to fill a gap region bounded by the trench and the trench masks. Next, the trench mask and the gap fill insulating layer are patterned to form a trench mask pattern and a gap fill insulating pattern for defining a slit-type opening, extending across and exposes the active region. A gate pattern is formed in the slit-type opening and the trench mask pattern is removed to form a contact opening exposing the active region. Next, a contact plug is formed to fill the contact opening. Here, the contact opening is self-alignedly formed using an etch selectivity between the trench mask and the gap fill insulating layer. The resulting contact opening is a vacancy in a rectangular parallelepiped shape.

Abstract: A field-effect transistor includes a channel layer that is formed on a predetermined semiconductor layer and has an impurity concentration varying from a low value to a high value, and a source region and a drain region each having a bottom face above the predetermined semiconductor layer.

Abstract: The bar-type field effect transistor consists of a substrate, a bar placed above a substrate and a gate and spacer placed above part of the bar.

Abstract: To provide devices relating to a manufacturing method for a semiconductor device using a laser crystallization method, which is capable of reducing a cost involved in a design change, preventing a grain boundary from developing in a channel formation region of a TFT, and preventing a remarkable reduction in mobility of the TFT, a decrease in an ON current, and an increase in an OFF current due to the grain boundary and to a semiconductor device formed by using the manufacturing method. In a semiconductor device according to the present invention, among a plurality of TFTs formed on a base film, some TFTs are electrically connected to form logic elements. The plurality of logic elements are used to form a circuit. The base film has a plurality of projective portions having a rectangular or stripe shape.

Abstract: A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate region extending in the transverse direction, coating the channel region, and insulated from the channel region. The source, channel, and drain regions are formed in a continuous semiconductor layer that is approximately plane and parallel to the upper surface of the substrate. Additionally, the source, drain, and gate regions are coated in an insulating coating so as to provide electrical insulation between the gate region and the source and drain regions, and between the substrate and the source, drain, gate, and channel regions. Also provided is an integrated circuit that includes such a semiconductor device, and a method for manufacturing such a semiconductor device.

Abstract: The present invention is a silicon on insulator (SOI) transistor and its method of fabrication. According to the present invention, an opening is formed in the insulating layer formed on a single crystalline silicon substrate. An amorphous or polycrystalline silicon or silicon alloy is then formed in the opening on the single crystalline silicon substrate and on the insulating layer. The amorphous or polycrystalline silicon or silicon alloy in the opening and at least a portion of the amorphous or polycrystalline silicon or silicon alloy on the insulating layer is crystallized into a single crystalline silicon or silicon alloy film.

Abstract: An ESD protection device coupled between two high power lines. The ESD protection device comprises a N-type well and a P-type well adjacent to each other, and a pair of PN MOS. The N-type well is coupled to a first high power line, and the P-type well is coupled to a low power line. The pair of PN MOS comprises a PMOS and a NMOS, formed respectively in the N-type well and P-type well. The PMOS and the NMOS is connected as an inverter powered by the first high power line and a second power line and to ensure that, in normal operation, either the PMOS or the NMOS is turned off.

Abstract: A PN junction diode has a substrate 1 of a first conductivity type, and first and second stripe diffusion regions 2, 3 which are the first conductivity type and second conductivity type, respectively. The stripe diffusion regions are alternately arranged at a regular interval in a surface layer of the semiconductor substrate. The diode further includes first and second stripe electrodes 7a, 7b connected to the first and second diffusion regions along the longitudinal sides thereof, respectively. The diode further includes a third electrode 7b′ which covers through an insulation film 5, 5′ the neighboring ends of the first and second diffusion regions and of which a potential is equalized to that of the second electrode 7b having a different conductivity type from the substrate.

Abstract: A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

Abstract: CMOS gate dielectric made of high-k metal silicates by reaction of metal with silicon dioxide at the silicon surface. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Abstract: A highly localized diffusion barrier is incorporated into a polysilicon line to allow the doping of the polysilicon layer without sacrificing an underlying material layer. The diffusion barrier is formed by depositing a thin polysilicon layer and exposing the layer to a nitrogen-containing plasma ambient. Thereafter, the deposition is resumed to obtain the required final thickness. Moreover, a polysilicon line is disclosed, having a highly localized barrier layer.

Abstract: The invention is directed to data input/output organization system and method in a semiconductor memory device. The memory device has a plurality of memory arrays, in one embodiment, an odd number of memory arrays. The arrays are divided into blocks, and the blocks are divided into segments. A control circuit provides control signals to the memory arrays such that data is input and/or output to and from the memory device in multiples of nine bits. The data bits are input or output simultaneously without the need for multiplexing circuitry. This results in reduced power consumption and increased memory processing speed.

Abstract: The present invention makes improvements to the peripheral circuits of the electrically programmable three-dimensional memory (EP-3DM). Full-read mode and self-timing are used to improve the speed and lower the power consumption. Cached EP-3DM is disclosed to reduce the latency. Redundancy can be employed to improve the yield of the EP-3DM.

Abstract: A body bias control system allows for independent design of a functional module, thereby reducing the burden of designing the module. The body bias control system provides a switch circuit having an area in which the body bias is controlled independently of its outside portion, for controlling the supply of body bias in the vicinity of the area. Preferably three types of switches are provided for switching the body bias to suitable levels for a standby mode, a mode of normal operation and a mode of high-speed operation.

Abstract: An electrolytic capacitor of the invention includes one type of electrode selected from a group consisting of an electrode of at least one type of alloy selected from a group consisting of niobium alloy, titanium alloy, and tungsten alloy, an electrode of mixed sinter of niobium and aluminum, or a fluorine-doped electrode of niobium or niobium alloy and on a surface of the each electrodes a dielectric layer is formed by anodizing the electrode.

Abstract: A semiconductor device disclosed herein comprises a semiconductor layer which includes a first semiconductor region of a first conductivity type, a base region of a second conductivity type, and a plurality of second semiconductor regions of the first conductivity type; a gate wiring which is formed on the semiconductor layer via a first insulating film; a plurality of main electrodes which are electrically connected to the plurality of second semiconductor regions and which are insulated from the gate wiring, wherein the gate wiring is arranged between the main electrodes and upper surfaces of the main electrodes are higher than an upper surface of the uppermost layer of the gate wiring; and a connecting plate which is directly connected onto uppermost layers of the main electrodes.

Abstract: A semiconductor integrated device includes a first insulating film 407 formed on any one of a conductive layer 406 and an interlayer insulating film 405, a first layer pad 408 which is in a two-layer pad and which is formed on the first insulating film 407, a third insulating film 413 deposited on both of the first insulating film 407 and the first layer pad 408 of the two-layer pad, a conductive plug 411 which is arranged to connect upper and lower pads of the two-layer pad and which is formed in the third insulating film 413, a second layer pad 401 which is in the two-layer pad and which is formed on the third insulating film 413, a second insulating film 409 which is formed on any one of the conductive layer 406 and the interlayer insulating film 405 and which has a film thickness greater than that of the first insulating film 407, and a single-layer pad 421 formed on the second insulating film 409.

Abstract: A semiconductor acceleration sensor is provided, which has the capability of preventing a situation that detection accuracy of acceleration deteriorates due to undesirable thermal stress induced when a metal layer wiring is used in the acceleration sensor. This sensor comprises a frame, a weight, at least one pair of beams made of a semiconductor material, via which said weight is supported in the frame, and at least one resistor element formed on each of the beams to thereby detect acceleration according to piezoelectric effect of the resistor element. The sensor also includes a doped semiconductor layer formed in a top surface of each of the beams as a wiring for electrically connecting with the resistor element.

Abstract: A semiconductor device includes a semiconductor chip with a functional surface, a substrate opposing the functional surface of the semiconductor chip at a space formed between the substrate and the functional surface, a power supplying device electrically connected to a part of the functional surface of the semiconductor chip and separated by a slight gap from the substrate, a fixing member that fixes the semiconductor chip to the substrate, and a sealing member that seals the space formed between the substrate and the functional surface of the semiconductor chip other than a space formed between the substrate and the functional surface of the semiconductor chip that are fixed to each other through the fixing member and other than the gap formed between the power supplying device and the substrate. The sealing member has greater elasticity than the fixing member.

Abstract: The semiconductor device according to this invention is characterized by a package structure of a semiconductor substrate 100 equipped with a photoelectric converting portion, wherein a light-shading means 104 is arranged in an area corresponding to at least the photoelectric converting portion on the side of the rear surface of the semiconductor substrate.

Abstract: The present invention provides a Schottky Structure in gallium arsenide (GaAs) semiconductor device, which comprises a gallium arsenide (GaAs) semiconductor substrate, a titanium (Ti) layer on a surface of said gallium arsenide (GaAs) semiconductor substrate to form Schottky contact, a diffusion barrier layer on a surface of said titanium (Ti) layer to block metal diffusion, and a first copper layer on a surface of said diffusion barrier layer.

Abstract: A circuit arrangement with semiconductor elements arranged in chips is described. The circuit arrangement is characterized by at least one metal body (s1) for electrically contacting the semiconductor elements and for dissipating the heat produced by the semiconductor elements, said metal body (s1) being adapted to simultaneously function as the support for the semiconductor elements and the chips (c1) of the semiconductor elements being fastened on the body (s1).