Abstract: The invention concerns a heterogeneous automation system (10) including a first physical network (15, 17, 20) in which all connected devices can communicate on the basis of a first communication protocol and at least one second physical network (52, 58, 59; 54, 56, 57, 60) which is connected to the first network (15, 17, 20) by way of a first control device (25, 30) functioning as a gateway, and in which all devices (54, 56, 57, 60) connected thereto can communicate on the basis of a second communication protocol, wherein the first and second networks and the first and second communication protocols are different. The object of the present invention is to provide a system and a connecting apparatus, by means of which communication is simplified, in particular upon start-up, configuration and maintenance of the system, in the entire automation system.

Abstract: A system and method for pushing information from a host system to a mobile data communication device upon sensing a triggering event is disclosed. A redirector program operating at the host system enables a user to continuously redirect certain user-selected data items from the host system to the user's mobile data communication device upon detecting that one or more user-defined triggering events has occurred. The redirector program operates in connection with event-generating applications and repackaging systems at the host system to configure and detect a particular user-defined event, and then to repackage the user-selected data items in an electronic wrapper prior to pushing the data items to the mobile device.

Abstract: A method and apparatus for identifying one or more characteristics of a networked device, such as a client modem, is disclosed. Values of one or more components of a signal from an unknown device are compared to values of the same components of signals from known devices. Matches determined by this comparison identify characteristics, such as the manufacturer, of the unknown devices to be the same as characteristics of the matched known devices. The comparison values are determined by receiving signals from known devices, and identifying and cataloging values of the one or more signal components in association with characteristics of the known devices. The identified characteristics are stored and later can be accessed or manipulated to derive additional information, such as statistical information based on the characteristics identified for multiple unknown devices.

Abstract: A method and system for remotely accessing and controlling at least one of a target switch and a target computer using a target controller. The video information captured by the target controller is analyzed and compressed in order to reduce network traffic between the target controller and a controlling computer.

Abstract: A client/server data processing system is developed by a method (20) in which a meta model (21) is transformed by a model generator (24) into an application model (25) which has a layered structure reflecting that of the end-product system. A code generator is associated with each layer of the application model (25). For the client side, an IDL representation (41) is generated and is transformed into client interfaces (46). Client user interfaces (47) are separately generated.

Abstract: The invention relates to a software object, more particularly a software Name Service object providing facilities for supporting transparent container objects. The software container objects contain a group of software objects herein referred to as fine grain objects, the fine grain objects communicating with external objects through the container's interface. This invention permits objects in the distributed system to communicate with specific ones of the fine grain objects within containers without requiring the Name Service to store an entry for each fine grain object. This allows a reduction in the size of the data structures within the Name Service and an improved usage of system resources. The Name Service stores an entry for a given container object including a range of fine grain objects implemented within the given container.

Abstract: A method and system for extending an extensible framework is provided. An extension module for an extensible framework is coupled with an abstraction layer overlaying the extensible framework. The abstraction layer includes a uniform cross-platform interface between the extension module and the extensible framework.

Abstract: Disclosed is an image output system. The image output system comprises input unit for inputting image data, a memory for storing image data input by the input unit, output means for outputting image data stored in the memory, entry means for entering an output condition under which the output means outputs the image data, and an instruction to begin to output the image data, and control unit for controlling an output operation such that the image data is to be output by the output means upon entry of the output condition and the instruction at the entry unit.

Abstract: A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

Abstract: An initiator holds commands corresponding to ORBs issued to a target in an I/O request queue until it receives a completion response from the target. The target has read and write execution agents, and processes commands from the initiator. When a connection between the initiator and target is disconnected, and is connected again, the initiator deletes all ORBs, and generates and issues ORBs again to the target on the basis of the commands held in the I/O request queue. Upon processing an ORB, the target holds an identifier of the ORB whose processing is in progress, and the address of a buffer which is undergoing a read or write. After re-connection, the target compares the held identifier with the identifier of an ORB re-issued by the initiator. If the two identifiers match each other, the target restarts the read or write from the held address.

Abstract: A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.

Abstract: As the digital signal processor has become more flexible, the direct memory access controller has assumed greater computational power to permit the core processing unit to perform its specialized processing without responding to signal transfer requests. Not only does the direct memory access controller control the exchange of signal groups between the memory unit and the core processing unit, but the direct memory access controller is also responsible for the transfer of signal groups within the digital signal processor that originate from the serial port, and the interface unit (the unit that implements the direct transfer of signal groups from the memory unit of one digital signal processor to a second signal processor). The direct memory access controller has programmable channels that permit the signal group source component to be coupled to the signal group destination component. The address unit of the direct memory access unit must be able to accommodate a plurality of addressing modes.

Abstract: A method for dynamically adjusting the flow rate of a plurality of logical pipes that share a common output queue. In accordance with the method of the present invention, a minimum flow rate and a maximum flow rate are set for each of the pipes. Next a determination is made of whether or not excess queue bandwidth exists in accordance with the output flow rate of the shared queue. The determination of whether or not excess bandwidth exists comprises comparing the output flow rate of the shared queue with a pre-determined threshold queue output value. An instantaneous excess bandwidth signal has a value of 1 if there is excess bandwidth and is otherwise 0 if there is no excess bandwidth. In an alternate embodiment, the instantaneous excess bandwidth signal for a particular pipe is logically ANDed with one or more additional excess bandwidth signals to form a composite instantaneous excess bandwidth signal.

Abstract: A first in, first out (FIFO) circular buffer enables high speed streaming data transfer between integrated circuit devices by performing more than one data element transfer unidirectionally by having a plurality of ports to address a memory array. In addition, the multiple transfers are performed during one bus cycle and the number of transfers may be selectable. FIFO control circuitry limits the number of data elements transferred in response to the state of the memory array including almost empty or almost full.

Abstract: A method and apparatus for transferring optical data from a DVD in response to a request from a host. When a data request is issued, a portion of the request containing the target ID for the target data block is used by a comparator circuit to locate the target data block. Another portion of the request containing the number of data blocks requested is used by a monitoring circuit to monitor data block transfer from a DVD to a data buffer once the target data block is located. The monitoring circuit stops data transfer when all of the requested data blocks have been transferred. Each data block is transferred into a data buffer containing areas separated by pointers. In a scratch area of the data buffer, the data block is error corrected, error checked and descrambled.

Abstract: Determining device characteristics includes obtaining a first globally accessible value, if the first globally accessible value corresponds to a stored first value, obtaining device characteristics data from a relatively fast memory, if the first globally accessible value does not correspond to the stored first value, obtaining a second globally accessible value, if the second globally accessible value corresponds to a stored second value, obtaining device characteristics data from a relatively fast memory, if the second globally accessible value does not correspond to the stored second value, obtaining device characteristics data from a relatively slow memory and updating the relatively fast memory, the stored first value, and the stored second value. The globally accessible first value may include device I/O information. The globally accessible values may be stored in global memory that is accessible to a plurality of processors.

Abstract: A device (e.g., a secondary cache device) manages descriptors which correspond to storage locations (e.g., cache blocks). The device includes memory and a control circuit coupled to the memory. The control circuit is configured to arrange the descriptors, which correspond to the storage locations, into multiple queues within the memory based on storage location access frequencies. The control circuit is further configured to determine whether an expiration timer for the particular descriptor has expired in response to a particular descriptor reaching a head of a particular queue. The control circuit is further configured to move the particular descriptor from the head of the particular queue to a different part of the multiple queues, wherein the different part is identified based on access frequency when the expiration timer for the particular descriptor has not expired, and not based on access frequency when the expiration timer for the particular descriptor has expired.

Abstract: An information exchanging device is disclosed. The information exchanging device includes two separate but engagable housings which are mounted thereon two connectors for electrically connecting to two handy personal information processing devices such as PDAs or cellular phones, respectively. The two connectors are electrically connected to each other via an information exchanging circuit after the two housings engages with each other. The information exchanging circuit can be further connected to a personal computer. The information exchanging operation between the two handy personal information processing devices is performed in response to a triggering signal generated by pressing an actuating button or manipulating the personal computer.

Abstract: An integrated circuit including a DMA controller, an ADC having a plurality of conversion channels and address and data ports for connection to external memory means, the DMA controller being arranged to read a channel id from the memory means using the address and data port which channel id is representative of one of the said conversion channels, to pass the read channel id to the ADC, to cause the ADC to perform an analog-to-digital-conversion on the conversion channel represented by the channel id, to receive the conversion result from the ADC and to write the conversion result back to the memory means using the address and data ports.

Abstract: The asynchronous data burst transfer circuit includes a data burst transfer oscillation circuit which outputs n strobe signals of mutually different phases, plural parallel-serial conversion circuits which convert n-bit parallel signals into serial signals, and plural serial-parallel conversion circuits which convert serial signals into n-bit parallel signals. The parallel-serial conversion circuits convert every n-bit parallel signals of data read from a memory into serial signals based on the strobe signals, and transfer the serial signals. The serial-parallel conversion circuits convert the received serial signals into n-bit parallel signals based on the strobe signals, thereby obtaining the parallel signals as the original data.

Abstract: A method and structure for dynamically blocking access of a request signal R to a shared bus such that R originates from a non real-time master and requests access to an address range of an address space. The shared bus manages requests for access to the address space. The non real-time master and a real-time master compete for access to the address space by presenting address access requests to the shared bus. The dynamic blocking of access by R to the shared bus is accomplished by use of a request limiter, which is a device that is coupled to a real-time clock and uses an algorithm to determine when to enable and disable access of R to the shared bus. The algorithm uses a windowing scheme that permits access of R to the shared bus every Nth clock cycle, wherein the value of the integer N may be supplied to the request limiter by the real-time master.

Abstract: An integrated multi-processor system with clusters of processors on a high speed split transaction bus uses a transaction acknowledge (TACK), by a target device in response to receiving a request from a master device on the bus. The master and target devices connect to the bus via a global bus interface with FIFO registers acting as buffers, and the target interface includes a TACK generator that flips the state of the global bus' TACK line upon determining that a broadcast request is addressed to its target device. A bus idle default device (BIDD) generates a TACK signal when no device is on the bus, and also detects the absence of any TACK response by monitoring the state of the TACK line, thereby indicating that a master device bus attempted to address a nonexistent target a device. The BIDD then generates a dummy response for the requesting master device with data flags set to invalid data.

Abstract: A plurality of asynchronous and isochronous transactions on a shared bus are scheduled such that asynchronous latency is minimized while providing a maximum latency for isochronous transactions. This is accomplished by splitting an allocated shared bus time into frames of equal length. When a bus request is received the technique determines whether the bus request in a current frame is for an asynchronous transaction or an isochronous transaction. If an asynchronous transaction bus request exists it is processed, otherwise an isochronous transaction bus request is processed. Bus requests for an isochronous transaction are queued if received while an asynchronous transaction is currently being processed. Asynchronous transactions are given priority until a current frame time has ended. In one embodiment, at the start of a new frame (which becomes the current frame) any queued isochronous transactions are processed before asynchronous transactions of the current frame are given priority.

Abstract: An adaptive card-sensitive bus slot system and method. The method and system include a substantially universal bus slot structure. In one embodiment, the substantially universal bus slot structure includes at least one Peripheral Component Interconnect adaptive key. In another embodiment, the substantially universal bus slot structure includes at least one Peripheral Component Interconnect adaptive key piston. In another embodiment, a data processing system includes the adaptive card-sensitive bus slot system.

Abstract: A method for testing a USB port and the device for the same. The VCC and GND power lines of the USB port and the twisted paired signal lines of D+ and D− are connected with the corresponding terminals on a parallel port so as to test the connection between the USB port and the USB host controller. The invention also discloses the corresponding device.

Abstract: The present invention includes an integrated circuit that is operable to connect a redundant array of inexpensive disks (RAID) or other peripheral device to a disk controller, such as a small computer system interface (SCSI) controller in a host device. The integrated circuit provides the peripheral device with sole access to the disk controller when operating in a straight mode. In straight mode, the peripheral device may communicate with the disk controller through a PCI bus to perform operations, such as retrieving or writing data to the peripheral device. Also, when in straight mode, other controllers, including the host's CPU, may be prevented from using the disk controller to avoid data collisions, data loss and possible system failure. The integrated circuit may also function in standard mode, such that other controllers connected to the host may access the disk controller.

Abstract: Non-volatile memory access, such as firmware access by a service processor, is disclosed. The service processor asserts a controller signal to select either a first non-volatile memory, or a second non-volatile memory. The first non-volatile memory is located behind a first bridge controller and is otherwise accessible by the service processor. The second non-volatile memory is located behind a second bridge controller and is otherwise accessible only by a processor other than the service processor. The service processor then access the selected non-volatile memory, via a bus communicatively coupled to both the non-volatile memories.

Abstract: A dynamic perimeter circular bus method and system includes a serial interconnect and elements connected in a serial loop through the serial interconnect. In operation, a variable sized loop word is transferred between elements along the serial loop. A sync character of the loop word is transferred from element to element along the serial loop. The sync character is indicative of the beginning of the loop word. At least one present character of the loop word after the sync character is then transferred from element to element along the serial loop. A present character is then asserted at an element to indicate that a data word follows the asserted present character in the loop word. The data word from the element is then put on to the loop word after the asserted present character thereby increasing the size of the loop word. The data word of the loop word is then transferred from element to element along the serial loop.

Abstract: A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central processing unit(s) and peripherals. A direct memory access controller (DMAC) is provided with a peripheral-independent interface coupled to the system bus and communicates with the system bus using system bus defined transactions. The DMAC comprises a set of registers. A central processing unit (CPU) configures teh DMAC by loading values into the DMAC registers. The configured DMAC issues an enable signal to a selected system component identified in the DMAC registers. A peripheral request interface is associated with the selected system components and communicates with the system bus using the system bus defined transactions. The selected system component asserts a request signal to the DMAC.

Abstract: A networking interface device for coupling a system host having one of a plurality configurations to a network medium. The networking interface device has a peripheral component interconnect (PCI) interface for coupling the interface device to a system host configured with a PCI based system bus interface; a medium independent interface (MII) for coupling the interface device to a system host configured with a media access controller (MAC) based system bus interface; and a buffer management device (BMU) having an active state for bursting data packet traffic via the PCI interface when the interface device is coupled to a PCI based system bus interface and a passive state for continuously passing data packet traffic via the MII when the interface device is coupled to a MAC based system bus interface.

Abstract: A multiprocessor system includes a plurality of system modules each having a plurality of processors, a transfer controller and a first crossbar, a crossbar module including a second crossbar, a control bus coupling the transfer controller of each of the system modules to the crossbar module, and a data bus coupling the first crossbar of each of the system modules to the crossbar module. Within an arbitrary one of the system modules, the first crossbar outputs a data packet to the data bus in response to a command signal from the transfer controller after the transfer controller outputs a control information packet to the control bus.

Abstract: A device contains a memory that stores a WOM codeword that encodes successive generations of data values. When the codeword must be updated to represent a new data value, the device determines which updates of the dataword can be realized by feasible single bit updates to the WOM codeword. If no feasible single bit update is possible, feasible two-bit updates are considered. Under control of the new data values a connection circuit routes feasibility signals for various updates, that signal the single-bit feasibility of the updates. Routing brings together pairs of feasibility signals for updates that together produce a WOM codeword that encodes the new data value. A pair is selected in which both feasibility signals indicate feasibility and the codeword is updated according to the updates involved in the pair. Preferably, the routing is realized with a connection circuit that comprises a number of layers of subcircuits, each routing the feasibility signals dependent on a respective bit of the new dataword.

Abstract: A method of reading data on a disk drive suited to an operating system that does not support the disk drive. First, the system allocates a free memory space in a memory thereof. Then the system reads the data in all the sectors of the disk with a reading routine, and saves the data in the free memory space. While receiving a disk drive reading command, the system processes the data saved in the free memory space according to the disk drive reading command. Thus, the drawback of the repeatedly turning on and off the disk drive is avoided while reading data with a length larger than a sector.

Abstract: A disk storage system containing a storage device having a record medium for holding the data, a plurality of storage sub-systems having a controller for controlling the storage device, a first interface node coupled to a computer using the data stored in the plurality of storage sub-systems, a plurality of second interface nodes connected to the storage sub-systems, a switch connecting to a first interface node and a plurality of second interface nodes to perform frame transfer therebetween based on node address information added to the frame. The first interface node has a configuration table to store structural information for the memory storage system and in response to the frame sent from the computer, analyzes the applicable frame, converts information relating to the transfer destination of that frame based on structural information held in the configuration table, and transfers that frame to the switch.

Abstract: A disk storage system containing a storage device having a record medium for holding the data, a plurality of storage sub-systems having a controller for controlling the storage device, a first interface node coupled to a computer using the data stored in the plurality of storage sub-systems, a plurality of second interface nodes connected to the storage sub-systems, a switching connecting to a first interface node and a plurality of second interface nodes to perform frame transfer therebetween based on node address information added to the frame. The first interface node has a configuration table to store structural information for the memory storage system and in response to the frame sent from the computer, analyzes the applicable frame, converts information relating to the transfer destination of that frame based on structural information held in the configuration table, and transfers that frame to the switch.

Abstract: One embodiment of the present invention provides a system that facilitates sampling a cache in a computer system, wherein the computer system has multiple central processing units (CPUs), including a measured CPU containing the cache to be sampled, and a sampling CPU that gathers the sample. During operation, the measured CPU receives an interrupt generated by the sampling CPU, wherein the interrupt identifies a portion of the cache to be sampled. In response to receiving this interrupt, the measured CPU copies data from the identified portion of the cache into a shared memory buffer that is accessible by both the measured CPU and the sampling CPU. Next, the measured CPU notifies the sampling CPU that the shared memory buffer contains the data, thereby allowing the sampling CPU to gather and process the data.

Abstract: In a disk drive, a read-ahead operation is prevented from being aborted due to an interrupt such as an error, to prevent the operation of a host device from stopping and to enhance reliability. The disk drive is connected to a host computer, the host device, via an interface, and performs read ahead after reading data in accordance with a data read command received from the host computer. When a read-ahead abort prevention function is provided at the host computer side, if the read ahead is interrupted by detecting an error at the disk drive side during the read ahead, the host device, after receiving an error report, causes the disk drive to resume the read ahead from the address at which the read ahead was interrupted. On the other hand, when the read-ahead abort prevention function is provided at the disk drive side, the disk drive, upon detecting an error, retries the read ahead from the address at which the error occurred.

Abstract: A prefetcher to prefetch data for an instruction based on the distance between cache misses caused by the instruction. In an embodiment, the prefetcher includes a memory to store a prefetch table that contains one or more entries that include the distance between cache misses caused by an instruction. In a further embodiment, the addresses of data elements prefetched are determined based on the distance between cache misses recorded in the prefetch table for the instruction.

Abstract: Methods and systems for handling requests received from a client for information stored on a server. In general, when a request for information is received, cache functions are bypassed or executed based on whether an execution of cache functions in an attempt to access the information from cache is likely to slow processing of a request for the information without at least some compensating reduction in processing time for a request for the information received at a later time. Also described is receiving information that identifies the location of a resource within a domain and selecting a cache based on the information that identifies the location of the resource within the domain.

Abstract: A cache coherency protocol uses a “Tagged” coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars.

Abstract: One embodiment of the present invention provides a multiprocessor system that supports multiple cache line invalidations within the same cycle. This multiprocessor system includes a plurality of processors and a lower-level cache that is configured to support multiple concurrent operations. It also includes a plurality of higher-level caches coupled to the plurality of processors, wherein a given higher-level cache is configured to support multiple concurrent invalidations of lines within the given higher-level cache. In one embodiment of the present invention, the lower-level cache includes a plurality of banks that can be accessed in parallel to support multiple concurrent operations. In a variation on this embodiment, each line in a given higher-level cache includes a valid bit that can be used to invalidate the line. These valid bits are contained in a memory that is organized into a plurality of banks that are associated with the plurality of banks of the lower-level cache.

Abstract: A set of related methods for detecting the existence and exact nature of any rearrangements and/or inversions of address lines and/or data lines to a memory device, relative to a second set of address lines and/or data lines to the same memory, are disclosed. Moreover, a set of related methods for correcting these relative rearrangements and/or inversions are disclosed. These methods allow meaningful access to memory shared by two or more devices using different address and data paths in the case where the relative nature of the address and data paths is unknown a priori. These methods of detecting and correcting such mismatches in separate address and data lines to shared memory may be implemented either in hardware or software or a combination of both.

Abstract: A multipurpose interlaced memory device functions in two different modes, synchronous and asynchronous. The memory uses a circuit for detecting address transitions by acting as a synchronous clock of the system for letting the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of memory cells. The memory device includes a buffer for outputting data. The buffer includes a circuit for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.

Abstract: A memory management system and method that quickly allocates and reuses memory for storage of data, such as display lists in a graphics system. The memory manager allocates memory without information regarding the amount of memory that is to be required while minimizing system-level memory allocation calls and maximizing the contiguity of the allocated memory which is used. The memory manager acquires from system memory a memory block that is of a predetermined size that is significantly larger than the anticipated memory size required to store a display list. The memory manager allocates to the display list that portion of the acquired memory block necessary for storing the display list, maintaining control over the unused portion of the acquired memory in a memory pool of available memory for future allocation to another display list without performing subsequent system-level calls.

Abstract: A method for allocating memory in a data processing system in which a configuration table indicative of the system's physical memory is generated following a boot event. The configuration table is then modified to identify a portion of the system's physical memory thereby hiding the remaining portion from the operating system. Subsequently, a memory allocation request is initiated by an application program. A device driver invoked by the application program then maps physical memory from the hidden portion to the application's virtual address space to satisfy the application request. The application program may be executing on a first node of a multi-node system in which each node is associated with its own local memory, In this embodiment, the node on which the allocated physical memory is located may be derived from the allocation request thereby facilitating application level, allocation of specified portions of physical memory.

Abstract: A memory controller includes an incrementer for predicting a next address to be asserted by a processor. The incrementer, structurally a counter, is configurable to wrap at a wrap boundary and to indicate when a predicted address crosses a page boundary if the memory is in page mode. This incrementer provides accurate predictions even where successor addresses are on different pages or, in the case of address loops, even in some cases in which the successor address is not consecutive. Thus, the number of accurate address predictions is increased, enhancing overall performance. The invention has particular applicability to signal processing applications with instructions loops that cross one or more page boundaries.

Abstract: An address sequencer circuit for generating addresses for accessing a memory device. The address sequencer includes a plurality of address stages that are coupled together, and also includes a first clock generation circuit that receives an input clock and generates a first clock signal that is coupled to a first portion of the address stages. A second clock generation circuit is provided that receives the input clock and a toggle signal and generates a second clock signal that is coupled to a second portion of the address stages, thereby allowing the first and second portions of address stages to be clocked at different rates.

Abstract: A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location identifier indicates a location in the vector where useful data ends. The vector load instruction further includes a value field that indicates a particular constant for use by the load/store unit to set locations in the vector register beyond the useful data with the constant. By embedding the ending location of the useful date in the instruction, bandwidth and memory are saved by only requiring that the useful data in the vector be loaded and stored.

Abstract: A computer system with parallel execution pipelines and a memory access controller has store address queues holding addresses for store operations, store data queues holding a plurality of data for storing in the memory and load address storage holding addresses for load operations, said access controller including comparator circuitry to compare load addresses received by the controller with addresses in the store address queue and locate any addresses which are the same, each of said addresses including a first set of bits representing a word address together with a second set of byte enable bits and said comparator having circuitry to compare the byte enable bits of two addresses as well as said first set of bits.

Abstract: A multiple instruction set processor and method dynamically activates one of a plurality of branch prediction processes depending upon which one of a multiple instruction set is operational. Shared branch history table structures are used and are indexed differently depending upon which instruction set is operational. The apparatus and method also allows switching between instruction set index generators for each of the plurality of instruction sets. Accordingly, different indexes to branch prediction data are used depending upon which of the plurality of instruction sets is operational. Shared memory may be used to contain branch prediction table data for instructions from each of the plurality of instruction sets in response to selection of an instruction set. Shared memory is also used to contain branch target buffer data for instructions from each of the plurality of instruction sets in response to selection of one of the instruction sets.