Abstract: A thin film transistor (TFT) including a polycrystalline active layer and a method for making the same are disclosed. An amorphous silicon layer is deposited on a substrate and is crystallized by using MILC (metal induced lateral crystallization) to provide a poly-silicon active layer of the TFT. Specifically, the amorphous silicon layer is poly-crystallized during a thermal treatment of the active layer. The thermal treatment causes the MILC of the active layer propagating from portions of the source and the drain regions on which MILC source metal is formed through the contact holes of the TFT.

Abstract: A thin film transistor source/drain structure and the manufacturing method thereof are disclosed. The thin film transistor source/drain structure uses a sandwich structure to reduce the resistivity of the source/drain and upgrade the reliability. The sandwich structure preferably comprises a structure of AlNdN alloy/AlNd alloy/AlNdN alloy. The AlNdN alloy is used as a buffer layer or a diffusion barrier to prevent the AlNd alloy and an amorphous silicon layer from diffusing into each other. The other AlNdN alloy is used as a glue layer and to protect the AlNd alloy from being over-etched. The other AlNdN alloy can also prevent the AlNd alloy and the following formed ITO from contact and interaction.

Abstract: There is provided a highly reliable semiconductor device in which electrostatic breakdown can be prevented. A diamond-like carbon (DLC) film is formed on a surface of an insulating substrate, and thereafter, a thin film transistor is formed on the insulating substrate. This DLC film allows charges of static electricity to flow and can prevent electrostatic breakdown of the thin film transistor.

Abstract: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).

Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin film transistors, and outside terminals 20 and outside terminals 30 opposed respectively to the ends of the gate bus lines and the drain bus lines 16, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines 24 for commonly connecting the gate bus lines 14 and drain connection lines 34 for commonly connecting the drain bus lines are formed in regions inner of the outside terminals 20, 30. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.

Abstract: Disclosed is an avalanche phototransistor capable of being used as a photo detector of high performance. The avalanche phototransistor comprises an emitter photoabsorption layer having a function to detect an infrared light, a thin avalanche-gain layered-structure including a charge layer and a multiplication layer having a thickness of 5,000 Å or less, and a hot electron transition layer. The avalanche phototransistor employs a three-terminal structure which consists of an emitter, a base and a collector. Even if a lower voltage than that of an avalanche photodiode is applied to the avalanche phototransistor, high gain can be obtained and sensitivity of the phototransistor can be increased. High current, high output and high operation speed can be accomplished using a hot electron effect. Further, stability of elements and reliance can be increased, and multiple operation functions can be obtained due to the increased number of terminals.

Abstract: A color filter substrate for a liquid crystal display device includes a polarizing substrate, a black matrix positioned on the polarizing substrate, a color filter layer positioned on the black matrix, and a common electrode positioned on the color filter layer.

Abstract: An LED device has an LED mounted on a substrate, and a transparent resin including phosphor particles for changing a color of light emitted from the LED, and sealing the LED. The transparent resin is colored by a dye at least on the surface. The dye is for correcting the changed color to a desired color.

Abstract: A radiation-emitting semiconductor component has an improved radiation efficiency. The semiconductor component has a multilayer structure with an active layer for generating radiation within the multilayer structure and also a window having a first and a second main surface. The multi-layer structure adjoins the first main surface of the window. At least one recess, such as a trench or a pit, is formed in the window from the second main surface for the purpose of increasing the radiation efficiency. The recess preferably has a trapezoidal cross section tapering toward the first main surface and can be produced for example by sawing into the window.

Abstract: A resonant-cavity light-emitting diode includes a semiconductor light-emitting layer sandwiched between an under and an upper semiconductor distributed Bragg reflector mirror layer, which are formed on the substrate, a light extracting section formed on the upper semiconductor distributed Bragg reflector mirror layer and having an opening to extract light from the semiconductor light-emitting layer, and a groove formed by removing portions of the semiconductor light-emitting layer, under and upper semiconductor distributed Bragg reflector mirror layers which lie in a peripheral portion of the opening of the light extraction section and reach the under semiconductor distributed Bragg reflector mirror layer, the inner wall of the groove being formed to reflect part of light emitted from the semiconductor light-emitting layer into the groove.

Abstract: A thyristor structure having a first terminal, formed as a first region with a first conductivity type, is provided. A second region of a second conductivity type adjoins the first region. A third region of the first conductivity type, which adjoins the second region, has a common surface with the latter. A second terminal, as fourth region of the second conductivity type, adjoins the third region. At the common surface of the second region and the third region, an auxiliary electrode is disposed in a manner adjoining at least one of the two regions.

Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.

Abstract: A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a channel stop p-well region and emitter region which are vertically oriented within a semiconductor substrate. The resulting bipolar device is junction isolated from other circuits formed on the substrate by a p-well region.

Abstract: An organic EL display device includes an organic EL light emitting element having the first electrode, an organic EL layer and the second electrode formed on a substrate; and a color conversion filter bonded to the organic EL light emitting element and having a color conversion filter layer formed on a transparent substrate. An outer sealing wall and an internal filling portion are formed between the organic EL light emitting element and the color conversion filter. A partition wall is formed between the outer sealing wall and the internal filling portion.

Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.

Abstract: A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a first conductive type having high impurity concentration, a second collector region of a first conductive type which has high impurity concentration and is formed on the first collector region, a base region of a second conductive type being formed a predetermined portion of the second collector region, and an emitter region of a first conductive type being formed in the base region. The bipolar transistor further includes the third collector region, which has higher impurity concentration than the second collector region, at the bottom of the base region.

Abstract: The bipolar transistor comprises a collector region (1) of a semiconductor material having a first doping type, a base region (2) of a semiconductor material having a second doping type, and an emitter region (3) having the first doping type. A junction is present between the emitter region (3) and the base region (2), and, viewed from the junction (4), a depletion region (5) extends into the emitter region (3). The emitter region (3) comprises a layer (6) of a first semiconductor material and a layer (7) of a second semiconductor material.

Abstract: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Abstract: Provided are a semiconductor device having an etch stopper formed of a nitride film by low temperature atomic layer deposition which can prevent damage to a semiconductor substrate and a method for fabricating the semiconductor device. Damage to the semiconductor substrate under the etch stopper composed of a second nitride film can be prevented by forming a first nitride film using high temperature LPCVD on the semiconductor substrate, forming the etch stopper including the second nitride film by low temperature ALD on the first nitride film, and removing the second nitride film by dry etching, thus taking advantage of the different etch selectivities of the first nitride film and the second nitride film.

Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Abstract: The present invention relates to a semiconductor device including a high withstand voltage MOS transistor and a manufacturing method thereof. The semiconductor device according to the present invention includes a MOS transistor in which a second-conductivity type source region is formed on a first-conductivity type semiconductor region, an offset drain region is interconnected to a second-conductivity type drain region and has a concentration lower than an impurity concentration of a drain region, the offset drain region is composed of a portion that does not overlap a first-conductivity type semiconductor region and a portion that overlaps part of the surface of the first-conductivity type semiconductor region and a gate electrode is formed on the surface extending from a channel region between the source region and the offset drain region to part of the offset drain region through a gate insulating film.

Abstract: Process for fabricating a transistor comprises producing source and drain extension regions, consisting in forming a gate region on a semiconductor substrate and in implanting dopants into the semiconductor substrate on either side of and at a certain distance from the gate of the transistor. The producing of the source and drain extension regions consists in forming an intermediate layer (Cl) on the sidewalls of the gate (GR) and on the surface of the semiconductor substrate. This intermediate layer is formed from a material that is less dense than silicon dioxide. The implantation of dopants (IMP) is carried out through that part of the intermediate layer that is located on the semiconductor substrate.

Abstract: A CMOS image sensor and a method of fabricating the same are provided. The image sensor includes a blocking layer protecting a photodiode at a diode region. The blocking layer is formed to cover a top of the diode region and extended to an active region so as to cover a transfer gate and a floating diffusion layer. Therefore, the floating diffusion layer may not be attacked by an etching during a formation of sidewall spacers of various gates or by ion implantation during a formation of a junction region of a DDD or LDD structure, thus reducing a leakage current and a dark current at the floating diffusion layer.

Abstract: In order to reduce the capacitance of a light-receiving element, the present invention provides a light-receiving element comprises a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, provided on the first semiconductor region, a third semiconductor region of the first conductivity type, provided between the second semiconductor region and an insulating film and an electrode region of the second conductivity type, provided in the second semiconductor region where the third semiconductor region is absent on and above the second semiconductor region, and connected to an anode or cathode electrode consisting of a conductor.

Abstract: In a peripheral circuit region of a DRAM, two connection holes 17a, 17b for connecting a first layer line 14 and a second layer line 26 electrically are opened separately in two processes. After forming the connection holes 17a and 17b, plugs 18a and 215a are formed in the connection holes 17a and 17b, respectively.

Abstract: Ferroelectric capacitors are provided that include an integrated circuit substrate and a supporting insulation layer on the integrated circuit substrate having a face and a trench in the face. An oxidation barrier conductive layer is provided in the trench and a lower electrode is provided on the oxidation barrier conductive layer. A ferroelectric layer is provided on the lower electrode and an upper electrode is provided on the ferroelectric layer. Related methods of fabricating ferroelectric capacitors are also provided.

Abstract: An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.

Abstract: A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.

Abstract: A self-aligned lateral-transistor DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a trench region and a trench-isolation region being formed in a side portion of the trench region and a self-aligned lateral-transistor structure comprises a merged common-source diffusion region, a self-aligned gate-stack region, and a self-aligned common-drain diffusion region being formed in another side portion of the trench region by using spacer-formation techniques. The unit cell size of the self-aligned lateral-transistor DRAM cell structure can be fabricated to be equal to 6F2 or smaller. The self-aligned lateral-transistor DRAM cell structure is used to implement two contactless DRAM arrays for high-speed read and write operations.

Abstract: A vertical DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type STI region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions under a common-drain diffusion region being formed in another side portion of the deep-trench region. The vertical DRAM cell structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common- drain conductive bit-lines.

Abstract: A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying

Abstract: A semiconductor capacitor device has two pairs of first and second MIM capacitors on a semiconductor substrate. The paired first and second MIM capacitors include respective capacitor dielectric films having different compositions. Also, the paired first and second MIM capacitors are connected in inverse parallel fashion, with an upper electrode of the first MIM capacitor being connected with a lower electrode of the second MIM capacitor and with a lower electrode of the first MIM capacitor being connected with an upper electrode of the second MIM capacitor. Furthermore, the two first MIM capacitors are electrically connected in inverse parallel with each other, and the two second MIM capacitors are also electrically connected in inverse parallel with each other. This arrangement facilitates mutual counteraction of the voltage dependences of the two pairs of first and second MIM capacitors so as to make the voltage dependence of the capacitance of the capacitor device small.

Abstract: A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection gate electrode and spaced apart from the selection gate electrode. The non-volatile memory device further comprises a tunnel insulating layer intervening between the active region and each of the selection gate electrode and the floating gate electrode, a separation insulating pattern intervening between the selection gate electrode and the floating gate electrode, an erasing gate electrode disposed over the floating gate electrode and crossing over the active region parallel to the selection gate electrode, and an erasing gate insulating layer intervening between the erasing gate electrode and the floating gate electrode. The selection gate electrode is formed without a photoresist pattern.

Abstract: An EEPROM device and a method of fabricating same. In one aspect, an EEPROM device comprises: a memory transistor including a tunnel insulating layer, first conductive layer patterns, and second conductive layer patterns stacked on a first portion of a semiconductor substrate, and common source regions and floating junction regions arranged at opposite sides of the second conductive layer patterns; and a selection transistor, which is connected to the floating junction regions, and includes a gate insulating layer, the first conductive layer patterns, and the second conductive layer patterns stacked on a second portion of the semiconductor substrate, and drain regions arranged at one side of the second conductive layer patterns opposite the floating junction regions.

Abstract: Gate structures of a non-volatile integrated circuit memory device can include a thermal oxidation layer on a substrate beneath the gate structure that defines a side wall of the gate structure. An oxygen diffusion barrier layer is on the side wall of the gate structure and a floating gate is on the thermal oxidation layer and has a curved side wall portion. Related methods are also discussed.

Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: When n-channel thin film transistors(TFTs) and p-channel TFTs are formed on a polycrystalline silicon film formed on a glass substrate, a process is included in which P-dopant or N-dopant is introduced at the same time to the channel region of a part of the n-channel TFTs and a part of the p-channel TFTs. In one channel doping operation, a set of low-VT and high-VT p-channel TFTs and a set of low-VT and high-VT n-channel TFTs can be formed. This method is used for forming high-VT TFTs, which can reduce the off-current, in logics and switch circuits and for forming low-VT TFTs, which can enlarge the dynamic range, in analog circuits to improve the performance of a thin film semiconductor.

Abstract: Non-volatile memory devices according to embodiments of the invention can include, for example, a semiconductor substrate, a source region, a drain region, an impurity region, a vertical structure, a control gate insulating layer, a control gate electrode, a gate insulating layer, and a gate electrode. The impurity region is in a floating state between the source region and the drain region. The vertical structure is formed of a tunneling layer, a charge trapping layer, and a blocking layer sequentially stacked between the source region and the impurity region. The control gate insulating layer is between the source region and the impurity region and adjacent to the vertical structure. The control gate electrode is formed on the vertical structure and the control gate insulating layer. The gate insulating layer is between the impurity region and the drain region. The gate electrode is formed on the gate insulating layer.

Abstract: A semiconductor device in which electro-thermal conversion elements and switching devices for flowing currents through the elements are integrated on a first conductive type semiconductor substrate. The switching devices are insulated gate type field effect transistors having a second conductive type first semiconductor region on one principal surface of the semiconductor substrate; a first conductive type second semiconductor region for supplying a channel region and for adjoining the first semiconductor region; a second conductive type source region on the surface of the second semiconductor region; a second conductive type drain region on the surface of the first semiconductor region; and gate electrodes on the channel region with a gate insulator film between them. The second semiconductor region is formed by a semiconductor having an impurity concentration higher than that of the first semiconductor region, and is disposed between two adjacent drain regions, separating them in a traverse direction.

Abstract: A gate insulating film is formed in a partial area of the surface of a semiconductor substrate, and on this gate insulating film, a gate electrode is formed. An ONO film is formed on the side wall of the gate electrode and on the surface of the semiconductor substrate on both sides of the gate electrode, conformable to the side wall and the surface. A silicon nitride film of the ONO film traps carriers. A conductive side wall spacer faces the side wall of the gate electrode and the surface of the semiconductor substrate via the ONO film. A conductive connection member electrically connects the side wall spacer and gate electrode. Source and drain regions are formed in the surface layer of the semiconductor substrate in areas sandwiching the gate electrode. A semiconductor device is provided which can store data of two bits in one memory cell and can be driven at a low voltage.

Abstract: There are provided a reference voltage generating method used for reading out operation of a memory cell having amplification ability, and a dummy cell. The memory cell is comprised of a read NMOS transistor, a write transistor, and a coupled-capacitance. The dummy cell is made such that two memory cells are connected in series. The dummy cell is arranged at the most far end of each of the data lines against the sense amplifier. A reference voltage is generated by making a difference in an amount of current flowing in each of the read NMOS transistors of the memory cell and the dummy cell. As a result, DRAM showing a higher speed, a higher integrated and a lower electrical power as compared with those of the prior art device can be realized.

Abstract: An SRAM comprises a memory cell including first and second access nMOS transistors, first and second driver nMOS transistors and first and second load pMOS transistors, polysilicon wires forming gates of the first and second access nMOS transistors and polysilicon wires extending in the same direction as the polysilicon wires for forming gates of the first and second driver nMOS transistors and gates of the first and second load pMOS transistors. The gate widths of the first and second access nMOS transistors and those of the first and second driver nMOS transistors are equalized with each other.

Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

Abstract: To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.

Abstract: The invention offers a highly reliable semiconductor device with high yields. The semiconductor device includes a silicon substrate, a gate insulating film formed on one main plane of a silicon substrate and mainly including zirconium oxide of hafnium oxide, and a gate electrode film formed in contact with the gate insulating film. The gate insulating film contains an additional element for stabilizing the amorphous state.

Abstract: A method of fabricating a semiconductor device is disclosed. A wafer substrate is provided. A first silicon oxide layer is formed over the wafer substrate. A nitride layer is formed over the first silicon oxide layer using a low temperature deposition process. A second silicon oxide layer is formed over the nitride layer. The low temperature process can form a nitride layer for an oxide-nitride-oxide (ONO) dielectric structure at about a temperature of 700° C. By such a process, an ONO dielectric structure can be formed using a low temperature deposition process, which can reduce the thickness of the ONO dielectric structure.

Abstract: A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.

Abstract: The cross-sectional area of polysilicon lines is increased by selectively epitaxially growing an upper portion of the polysilicon line in the presence of a dielectric layer exposing the upper portion. Thus, a substantially T-shaped line is obtained, allowing a minimum bottom-CD while insuring a sufficient high conductivity.