Abstract: A method performs test measurements on electrical components. The components are firstly subjected to an aging process before the actual test measurements are performed on them. In order to be able to handle this in a particularly simple manner, the components are firstly disposed on a carrier with a switching matrix. In this case, the switching matrix is configured in such a way that all the components are switched on for the purpose of carrying out the aging process and exclusively the components to be measured—individually or in subgroups—are switched on for the purpose of carrying out the test measurements.

Abstract: A circuit board coupon testing method and apparatus. A coupon tester uses a linear actuator to carry a test head and probe(s) for an LCR meter. The linear actuator accurately steps the probe(s) over a coupon of components arranged linearly adjacent an edge of the circuit board to measure the parameters of the component. The coupon tester can be integrated with an in-circuit tester to provide further functionality, with the coupon test being carried out simultaneously with a portion of the in-circuit test such as an unpowered portion of the in-circuit test.

Abstract: The integrated circuit test system and method prevent the occurrence of frost under a very low temperature environment during the exchange of integrated circuits under environmental testing and allows for the continuous testing thereof. The integrated circuit test system comprises a test chamber, a portion of which is adapted to interface with a tester having a circuit panel. An auxiliary chamber is adjacent the test chamber, the auxiliary chamber including a first door between the auxiliary chamber and the test chamber, the auxiliary chamber further including a second door between the auxiliary chamber and an external region, the auxiliary chamber for receiving a sample prior to and following a test. A transfer unit is also in the chamber, for transferring the sample between the test chamber and the auxiliary chamber through the first door. Accordingly, the time consumed during the exchange of testing samples is shortened.

Abstract: One embodiment of the present invention provides a system that facilitates fully characterizing propagation delay through an n-input circuit. The system operates by first receiving the n-input circuit. Next, the system establishes programmable voltage sources at each input of the n-input circuit. The system then programs each programmable voltage source to provide a sequence of input patterns to the n-input circuit. This sequence includes the 22n possible transitions between all possible pairs of input patterns. Next, the system measures the propagation delay between the input and the output of the n-input circuit for each transition in the sequence of input patterns and then reports the results.

Abstract: A method for forming a non-contact position sensor having a predetermined stroke length comprises providing a pair of coil assemblies each comprising a primary and secondary coil of a predetermined size; providing a core member of varying magnetic density about its length; and inserting the core member within the coil assemblies, whereby axial movement of the core member relative to the coil assemblies causes a corresponding output signal from the coil assemblies indicative of the position of the core member.

Abstract: A magnetic detection apparatus includes a first block, a second block, and an exterior resin covering the first block and the second block. The first block includes a magnetoresistive element for detecting a change in a magnetic field that varies in accordance with movement of a rotating member, electronic components forming a protection circuit against external noise, a first lead frame electrically connected with the electronic components, and a first base in which the electronic components, the first lead frame and the magnetoresistive element are sealed with a resin. The second block includes a magnet arranged in opposition to an object to be detected for generating a magnetic field, a second lead frame electrically connected with the first lead frame and having a connector terminal for outputting an output signal of the magnetoresistive element to an external member, and a second base in which the second lead frame is sealed with a resin.

Abstract: An object detection portal wherein a video image is obtained of a volume or area being scanned, and location of a threat object is determined and displayed in real time as an indicator overlay on the video image. An individual subject being scanned may be continuously monitored by an operator during an object divesting process, and an operator may view the threat object moving from or remaining with the subject. Object location information is supplied to a video driver to superimpose the overlay on a real time image of a subject. The scanning portal may interact with an exit barrier. The exit barrier may be activated automatically in response to sensing of a threat.

Abstract: According to some embodiments of the present invention, a magnetometer includes at least one sensor for sensing a magnetic field component, a biasing circuit, and a processor. The sensor generates an output signal having a signal characteristic that varies in response to the sensed magnetic field component and in response to an applied bias. The biasing circuit dynamically biases the sensor in response to a bias setting signal. The processor is coupled to receive the output signal from the sensor and coupled to the biasing circuit. The processor is operable to generate the bias setting signal and thereby control the biasing circuit to dynamically bias the sensor such that the signal characteristic of the output signal is maintained in a target range. The processor determines the magnetic field component sensed by the sensor as a function of the bias setting applied to the sensor.

Abstract: A sensor package and method of making the same is disclosed in which the sensor package includes a sensor component for electromagnetic sensing having a holder assembly with the sensor component disposed at one end and sensor terminals in electrical communication with the sensor component extending from an opposite end. A harness assembly having a harness head configured with harness terminals extending therefrom for electrical connection with corresponding sensor terminals. The holder assembly and harness head are configured with a means for snap-fit assembly that provides space to mechanically connect corresponding sensor terminals and harness terminals with each other forming a resultant subassembly for insertion into a sensor housing. The housing further includes a heat-staked interface with the harness head that secures the subassembly relative to the sensor housing.

Abstract: A device for inserting local gradient coils (insert gradient coils) into a magnetic resonance apparatus has movable carrier unit and a boom that is extensible in the horizontal direction, the boom being connected to the movable carrier unit and accepting the gradient coil unit and inserting it into the examination space of the magnetic resonance apparatus.

Abstract: A microcantilever sensor using molecular imprinting polymerization (MIP) technology, and a method of using thereof. The MIP microcantilever sensor is placed into a conduit, where it processes either an aqueous or environmental flow, or else a bodily fluid. The MIP microcantilever sensor provides for continuous on-line monitoring of the flow whereby the sensor monitors for any target analyte in which the MIP has been fabricated to attract. The present invention can be used to detect organic molecules, inorganic molecules, inorganic ions or viruses, pathogens, microorganisms, parasites or any other biological substance in which detection is desired. When the MIP microcantilever sensor detects the target analyte, the microcantilever sends a signal to a microprocessor for.

Abstract: This wrist technology invention uses the latest miniature state of the art electronics to gather, process and display electromagnetic data in order to warn industrial, recreational and environmental health concerned individuals of electric shock, electrocution and biological hazards. It is run by a highly sophisticated custom software controlled microcontroller that is able to quickly measure, process and present data to a user in a form that will allow quick determination of possible surrounding electrical hazards. This technology used is the key in being able to produce this invention in a unique miniature battery operated package the size of a wristwatch.

Abstract: An electrostatic instrument for measuring particle concentrations and possibly sizes in aerosols, such as an Electrostatic Low Pressure Impactor or Differential Mobility Analyser suffers from errors which limit the useful response bandwidth of the device. The invention minimises or eliminates these transient errors which are caused by changing particle concentrations in the aerosol. A system may be added to an otherwise conventional instrument to compensate for the transient effects based on a model of the charge production mechanism. Alternatively, a screening electrode placed over the sense electrodes in the instrument, and held at controlled electrical potential difference, is added to the instrument to eliminate the effect. A third embodiment adds compensating electrodes which provide a direct measurement of the transient effect which can be subtracted from the signal.

Abstract: Interface parameters for a plurality of semiconductor devices, particularly parameters for output drivers (i.e. on chip driver) and terminations (i.e. on die termination) for double data rate dynamic random access memories, are aligned using a calibration reference which is common to the semiconductor devices and is connected to calibration connections on the semiconductor devices. The semiconductor devices are calibrated in succession, in each case individually, and the calibration connection on the respective semiconductor device which is currently performing calibration is connected to an internal calibration unit by an internal switching unit in the process, and the calibration connections on all other semiconductor devices are terminated to a high impedance internally.

Abstract: In the process of estimating attributes of a transmission line from reflectometry measurements, small yet important reflections may be drowned in the immediate reflected signal owing to the mismatch between the reference impedance with respect to which the 1-port scattering parameter of the line has been determined and the characteristic impedance of the line.

Abstract: A radar level gauge for measuring the level of a surface of a product stored in a tank by use of a radar, where said radar transmits microwaves towards said surface and receives microwaves reflected by said surface and wherein said radar is adapted to transmit and receive said microwaves within two widely separated frequency bands. Widely separated frequency bands are chosen to utilize the differences in attenuation due to foam on the surface and the differences in beam-width or other disturbances. The ratio between the center frequencies of the two widely separated frequency bands can be quantified as at least greater than 1.5:1 or preferably greater than 2:1.

Abstract: A capacitive type sensor includes a pair of electrodes disposed on a surface of an insulating substrate to face with each other, and a water vapor sensitive disposed between and in contact with the electrodes. These electrodes are each constituted by an electrically conductive material whose linear thermal expansion coefficient is less than that of the water vapor sensitive film and is substantially the same as that of the insulating substrate, and suppresses a swelling of the water vapor sensitive film caused when the sensor is placed in a high temperature/humidity environment, thus suppressing drift deterioration of the sensor.

Abstract: A device and method for determining the sheet resistance of samples, in particular wafers and other two-dimensional objects, comprising a means for measuring the conductivity of the sample according to the eddy current technique, wherein the sample is introducible into a gap for measurement, and comprising a means for measuring the position of the sample in the gap for measurement and a computing means for determining the sheet resistance on the basis of the measured conductivity and of the position of the sample in the gap for measurement.

Abstract: A measurement circuit and a corresponding method for a three poles monolithic quartz crystal filter. With the first and the second switch connected respectively to the first and the third pole, any terminal electrode of the filter (the second not included) is not only electrically coupled with the impedance matching circuits, but also electrically coupled with the terminal impeders or the measuring instruments according to the status of the switches. Therefore, by controlling the switches, Fo and BW of the filter could be acquired by the measuring instruments. Moreover, applying the conventional two-pole short-circuits bandwidth theorem, A-sym of the filter could also be acquired by separating the 3-poles filter into two 2-poles filter.

Abstract: A probe card for testing an electrical element such as a semiconductor wafer or a printed wiring board includes a substrate with circuitry thereon, an encapsulant layer overlying the substrate and a multiplicity of leads extending upwardly from the substrate through the encapsulant layer to terminals, the terminals projecting above the encapsulant layer. The probe card can be engaged with the electronic element so that the tips of the leads bear on the contact pads of the electronic element, and so that the leads and encapsulant layer deform to accommodate irregularities in the electronic element or probe card. The card can be made by providing the substrate, a sacrificial layer and leads extending between the sacrificial layer and substrate, moving the substrate and sacrificial layer away from one another to deform the leads and injecting a curable material around the leads to form the encapsulant layer.

Abstract: Embodiments of the invention provide a flexible probe head that improves contact force and uniform mechanical contact pressure between the probe feature and an engaged bond pad. Flexible probe head is formed from a plurality of conductive wires embedded in a high frequency elastomer material. During wafer sort, the flexible probe head is in contact communication with die under test. The flexible probe head assumes the natural co-planarity of the surface of the die under test and sort interface unit.

Abstract: One end of an inductor is connected to a drain of a P-channel type MOS transistor. A source of source of MOS transistor is connected to an electric power source which supplies a voltage Vdd. The other end of inductor is connected via a dummy capacitor to a ground. Furthermore, a dummy resistor is connected between a drain of MOS transistor and the ground. The dummy resistor has the same resistance as that of a parasitic resistor existing between the inductor and the MOS transistor. Another dummy capacitor is connected between the dummy resistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground.

Abstract: A method for testing integrated circuits is provided. The method includes providing an excitation voltage to a device, such as a MOSFET. A power supply voltage is also provided to the device, such as a drain to source voltage or VCC. The quiescent power supply current of the device is then measured, such as the IDDQ of the MOSFET. The power supply voltage to the device is then varied, and it is determined whether a change in the IDDQ of the device exceeds a predetermined allowable change.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situi test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy, being cured by pressing the integrated circuit (IC) dice against interconnection bumps on the substrate for electrical connection, while, those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of “known good dice” (KGD) rework procedures during repair is. eliminated.

Abstract: A method and a device for measuring the temperature of windings of a drive motor, especially a three-phase motor, which is supplied by a converter with three controlled half bridges from a direct current intermediate circuit. The method, a corresponding device, and a control system of the invention offers more accurate results with less complicated circuit engineering. To this end, one current flux traversing at least one of the windings of the motor is measured by the converter while approximately knowing at least one cold resistance and other parameters of the motor. A temperature change of the windings is calculated from a change in the current flux based on a change of the temperature-dependent resistance.

Abstract: A fully self-sufficient configurable spare gate cell that has two types of inputs: a functional input bus and an equation input bus, whereby the spare gate cell can be transformed into any sum of product operator by the assertion of certain signals to the equation input bus. In a spare state, the functional input buses are connected to an area of pre-defined logic where the need for bug fixes are high. Thus, the spare cell would be automatically placed close to the bug-fix area during the place-and-route phase of chip design, thereby reducing the need to look for routing channels.

Abstract: A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initialising it.

Abstract: In an output buffer apparatus including a main-buffer circuit including a plurality of first transistors each connected between a first power supply terminal and an output terminal and a plurality of second transistors each connected between a second power supply terminal and the output terminal, and a pre-buffer circuit including a plurality of first pre-drivers each driving one of the first transistors in accordance with a data signal and a plurality of second pre-drivers each driving one of the second transistors in accordance with the data signal, a plurality of first sequential circuits are provided for receiving first impedance adjusting signals in synchronization with the data signal to turn ON the first pre-drivers, and a plurality of second sequential circuits are provided for receiving second impedance adjusting signals in synchronization with the data signal to turn ON the second pre-drivers.

Abstract: The present invention is a decoder for decoding a signal. The decoder includes a discriminator and a threshold generator. The discriminator receives the signal and generates an output voltage equal to a first voltage if the signal is less than a threshold level that is input to the discriminator and equal to a second voltage if the signal is greater than the threshold level. The threshold level depends on the output from the discriminator in a preceding time interval that depends on the impulse response of a transmission link through which the input signal has passed. The threshold generator implements a low-pass analog filter that receives the output voltage during each of the clock periods and generates therefrom a filtered output signal.

Abstract: A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.

Abstract: The distance between a drain contact and gate electrode in a terminating transistor, which couples a termination resistor connected to an output terminal to a power source node, is set shorter than in an output transistor, which drives an output node in accordance with an internal signal. The area of the terminating circuit is reduced while the reliability against the surge is maintained. Thus, an output circuit containing the terminating circuit that occupies a small area and is capable of transmitting a signal/data at high speed is provided.

Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Abstract: An electronic circuit apparatus and integrated circuit device, wherein an arrangement of connection terminals, external connection terminals and input/output interface circuits of a semiconductor chip as a unit circuit device is optimized so as to attain suppression of a power consumption and a shorter signal transmission time, configured that only connection pads are allocated to be arranged on a mutually adjacent side of semiconductor chips 1 and 2, and input/output interface circuits, test pads and external connection pads are arranged along remaining three sides, moreover, the connection pads and the electronic circuits are directly connected not via the input/output interface circuits.

Abstract: A phase-locked loop apparatus includes a ring oscillator including inverters, first and second transistors, a converter, mirror circuits. The first transistors control a current from a first voltage to the inverters. The second transistors control a current from the inverters. The converter converts the voltage output from the filter into a current. The first mirror circuit outputs a current in accordance with the current output from the converters. The second mirror circuit outputs a current according to the current output from the first mirror circuit to control the first transistors. The third mirror circuit outputs a current according to the current output from the second mirror circuit to control the second transistors. The converter, the first and second mirror circuits operate with a second voltage greater than the first voltage, and the ring oscillator and the third mirror circuit operate with the first voltage.

Abstract: A circuit for evaluating characteristics of duration and/or shape of an electric pulse induced in an element of an integrated circuit comprising an assembly of elements, each element being likely to receive an occasional external disturbance generating an electric pulse in the element, and a measurement circuit connected to the elements to determine said characteristics of an electric pulse generated in one of the elements.

Abstract: An apparatus for indicating clock skew within integrated circuits (ICs) of a system. There are first and second IC chips operating on respective clocks in the system. According to the invention, the first IC chip operating on a first clock is configured to provide the first clock as output. The second IC chip operating on a second clock has a detection circuit to receive as input the first and the second clocks and to generate a compare signal as output, where the width of the compare signal is proportional to the amount of skew between the input clocks. The second IC chip also includes a sampling circuit coupled to receive the compare signal. With the sampling circuit, an output signal indicative of skew existing between the first and the second clocks can be asserted according to the compare signal.

Abstract: A differential latch includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation.

Abstract: A chopper comparator has inverters (1,2) in input and output stages including NMOS transistors (M3,M6) to control the connection and disconnection of an inverter circuit forming each inverter (1,2). During a non-operation period of the chopper comparator, circuits formed in the inverters (1,2) are disconnected form the ground based on a PS signal to be supplied to gates of the NMOS transistors (M3,M6).

Abstract: An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.

Abstract: An impedance adjustment circuit generates an internal impedance adjustment signal and an impedance adjustment entry signal based on an externally applied impedance control signal. A data processing circuit decodes the internal impedance adjustment signal in synchronization with an internal clock signal to generate an output buffer drive signal of 5 bits. When the output buffer drive signal is applied to an output circuit of the succeeding stage as well as to an output replica circuit in a DLL circuit, the impedance of the output replica circuit is adjusted following adjustment of the output impedance.

Abstract: A master DLL circuit (3) generates a first delay signal (CKD) by delaying the master clock signal by a first delay time (T0) and generates a first pulse signal (Smp) having a pulse width (T0) of the first delay time, and generates a first control signal (Scp) which is changed in accordance with the first pulse signal (Smp), and adjusts the first delay time (T0) in accordance with the first control signal (Scp). Each slave DLL circuit (D1 to Dm) delays, by a second delay time (td), a delay internal clock signal, and outputs the delayed delay internal clock signals (CK1 to CKm) which form the multiphase clock signals. Each slave DLL circuit generates a second pulse signal (Ssp) having a pulse width (td) of the second delay time, and generates a second control signal (Scp1) which is changed in accordance with the first and second pulse signals (Smp, Ssp), and adjusts the second delay time (td) in accordance with the second control signal (Scp1), thus reducing a skew value of the multiphase clock signal.

Abstract: Circuits for adjusting the duty cycle of a clock(s) signal include a negative feedback loop for applying an offset signal to the uncorrected clock signal(s). The offset signal, which corresponds to a duty cycle error of the corrected clock signal(s), adjusts the slicing level of the uncorrected clock signal(s) to cause the duty cycle error to converge toward a predetermined value, for example, zero. The techniques may be used to adjust the duty cycle error of differential clock signals as well as single-ended clock signals.

Abstract: In a flip-flop circuit which includes an input section using a dynamic circuit and an output section using a static circuit and which captures data during a period of a pulse width shorter than a clock cycle, the number of transistors, circuit area and power consumption are reduced.

Abstract: The clamp circuit clamps an input voltage at prescribed higher and lower clamp voltages which are stabilized under a temperature fluctuation. Transistors Q12 and Q14 are switched on in their linear region. In a lower voltage clamp circuit 18, an Vin detecting circuit 20 outputs Va1 by level-shifting Vin by Q13 and voltage-divides by series resistance circuit 23 the level-shifted Vin, while a reference voltage generating circuit 21 outputs Vr1 by level-shifting 0 V by Q15 and voltage-divides by series resistance circuit 25 the level-shifted voltage. Q11 is switched on, when a comparator 22 determines that Va1 descends and goes across Vr1. Here, Q12 is of the same characteristics as Q14, while Q13 is of the same characteristics as Q15. Further, the resistance of the circuits 23 is the same as that of the circuit 25. The higher voltage clamp circuit 19 is similar to the circuit 18.

Abstract: A circuit implemented in a MOS device for operation with an internally non-linear topology, the circuit including at least first and second voltage ports, at least one voltage comparator for comparing the voltage at at least one of the voltage ports with a reference voltage, at least one of a current source or current sink for selectively sourcing current to or sinking current from the at least one of the voltage ports to maintain the voltage thereat in a voltage frame, thereby providing the circuit with a single stable dc operating point.

Abstract: A one-way switch comprises a metal-oxide semiconductor field-effect transistor (MOSFET) and a driver. Source and drain of the transistor function as P-terminal and N-terminal of the one-way switch. The driver, such as comparator or amplifier, is used to detect the voltage difference between the source and drain of the MOSFET. When the voltage of the P-terminal is higher than that of the N-terminal, the driver 150 outputs a driving voltage to gate of the MOSFET to turn on the MOSFET. If the voltage of P-terminal is lower than that of the N-terminal, the driver 150 cannot output voltage to turn on the MOSFET, and the one-way switch is off. Therefore, the one-way switch has the characteristic of workings in one direction.

Abstract: A negative voltage switch for use in flash memory. The switch has a control end and two voltage output ends, and includes two inverting units for transferring a positive voltage, two driving units for transferring a negative voltage, and two negative voltage pass-gate transistors for respectively transferring the negative voltage to the voltage outputs. Each inverting unit connects to a driving unit at a corresponding node, and each negative voltage pass-gate transistor connects to one of the nodes. According to a voltage at the control end, the switch turns on one inverting unit to transfer the positive voltage at the corresponding node, and the driving unit connected to the other node turns on to transfer the negative voltage to the corresponding negative voltage pass-gate transistor such that the negative voltage pass-gate transistor stops outputting the negative voltage at the other voltage output.

Abstract: A pair of C-shaped gate electrodes may define a pair of transistors and a pair of diodes for forming an input/output signal driver for electrostatic discharge protection. Because of the compact arrangement, silicon real estate may be conserved in silicon-on-insulator substrates.

Abstract: A block parallel efuse apparatus blown with serial data input. The block parallel apparatus includes a high voltage source, efuse circuits, a plurality of multiplex, registers, and an input-output terminal, wherein each efuse circuit includes an efuse, a blown-control terminal, an input terminal, and an output terminal. Each efuse is coupled between the high voltage source and the output terminal of the efuse circuit.

Abstract: A voltage control circuit for a non-volatile memory (NVM) array or other integrated circuit that uses a comparator circuit, a switch control circuit, and a pair of PMOS switches to selectively couple an output node to the greater of two voltage signals. An output gain provided by the comparator circuit is used to control the coupling process such that the voltage difference needed to switch between the first and second voltage signals is minimized. The high or low comparator output signal is transmitted to the switch control circuit, which utilizes a pair of level shifters to control the pair of PMOS switches, which in turn couple one of the first and second voltage sources to the output node.