Abstract: A safety sign and methods are shown for use on an oversized load with advantages such as being more visible in poor conditions such as snow, dust, fog, low light, etc. Safety signs as shown can be seen from farther away than conventional signs. Safety signs as shown eliminate problems associated with point source lighting.

Abstract: A method and apparatus for retrofitting a backlit sign with an LED module. The housing includes sidewalls with translucent portions. The LED module includes linear arrays of LEDs supported by support arms having mounting mechanisms for engaging with the housing sidewalls. The mounting mechanisms include scissor arms rotatably attached together about mid-portions thereof, and a tightening screw that adjusts the distance between the scissor arm ends to press engagement surfaces of the scissor arms against the housing sidewalls. Adjustment screws at the lower ends of the support arm can be adjusted to further extend the engagement surfaces, so that a single LED module can be installed inside a wide range of backlit sign sizes. The retrofit method includes removing the conventional fluorescent lamp from the backlit sign, and installing the LED module using the scissor arm mounting mechanisms.

Abstract: A power supply protecting the electric device circuit when over-voltage is applied, is provided. The power supply has a rectifying unit rectifying AC power externally supplied, into first and second DC power and outputting the first and the second DC power; a main power supply transformer boosting the first DC power and supplying the boosted first DC power to the electric device circuit; a switching controlling unit driven by the second DC power, performing the operation on the main power supply transformer that causes the first DC power to be boosted when the second DC power is received; and a controlling unit determining whether the second DC power is to be supplied to the switching controlling unit, wherein the controlling unit senses the voltage supplied to the electric device circuit and interrupts supplying the second DC power to the switching controlling unit if the sensed voltage exceeds a given value.

Abstract: A system and method for DC/DC conversion are provided in which a high accuracy digital pulse width modulator controller circuit controls a power switch to obtain a desired DC output. The control circuit amplifies the difference of a DC output sample in relation to voltage reference. The amplified difference is then compared with a portion of the DC output. The compared result is used for controlling the power switch. A ripple coming from the DC output side is overlaid upon either one of the inputs to the comparator depending upon the polarity of the ripple signal.

Abstract: A switch mode converter uses the bootstrap capacitor 30 to operate all the way to 100% duty cycle by adding only a very small amount of low-area extra circuitry. The additional circuitry includes a charge pump 40 and a duty cycle detect device 42. When the duty cycle detect device 42 detects that the converter is attempting to operate in 100% duty cycle, the charge pump 40 provides additional charge to the bootstrap capacitor 30 to ensure that the 100% duty cycle is maintained. Performance into dropout (when the input supply is actually lower than the desired output) is improved. A significant advantage in some applications (notably battery operation) is provided.

Abstract: Capacitive voltage multiplier for generating voltage pulses, preferably up to 100 V, that are higher than the supply voltage for displays, non-volatile memories and corresponding units especially in small electronic devices, such as handheld telecommunication terminals or corresponding devices, wherein the multiplier comprises a switching capacitor circuit (21) provided with capacitors and switches for charging the capacitors in parallel and discharging them in series in order to deliver a high voltage pulse. The multiplier further comprises a diode chain circuit (22) consisting of a diode-chain and pumping capacitors for delivering high voltage current. The inventive system allows the output high voltage to be switched on and held with little longtime drop and with small switching losses and able to supply a load current without significant ripple. Additionally switching the high voltage on and off does not result in efficiency loss.

Abstract: A fast transient response converter is disclosed which makes use of stepping inductor in a switching converter to speed up output voltage response under fast transient condition. The inductive element in a switching converter is replaced by two series or parallel inductive elements, one of which has a smaller value of inductance than the other. During the fast transient period, the inductor with larger inductance value will be shorted to a voltage source. The total inductance will be greatly reduced and thus allows rapid current change during the transient change.

Abstract: An active damping arrangement for a power conditioning circuit comprising a converter or an inverter and an electronically driven output line having an output terminal for connecting to an external load, the active damping arrangement comprising an inductor-capacitor low-pass output filter (OPF) for connecting between an output of the inverter/converter (PWMVC or BBHCC) and the output terminal; means for sensing current in or voltage across the capacitor or voltage between one end of the capacitor (C) and an effective neutral point; means for multiplying the sensed voltage or current by a coefficient G to provide a damping signal, and means for feeding back the damping signal to an input of the inverter/converter (PWMVC or BBHCC), thereby to damp the output of the inverter/converter.

Abstract: A method and a device for realizing an effective value of a quantity to be varied in an electrical load connected to a multi-phase switchable DC/AC frequency convertor comprising a plurality of controllable switches. The value is realized by varying a current or a voltage delivered by the DC/AC frequency convertor through suitable switching of the switches thereof, and wherein the quantity exhibits a load angle which, averaged in time, leads or lags the voltage or current being delivered.

Abstract: The invention relates to a method in connection with an inverter, the inverter comprising a direct voltage intermediate circuit, an optimum switching table and output power switches. The method comprises steps where phase currents (iA, iC) of the inverter are converted to a synchronous dq coordinate system in order to achieve vector components (id, iq), the synchronous current vector components (id, iq) are low pass filtered in order to achieve current vector components (id, Ipf, iq, lpf), a current reference (iq, ref) is generated in the direction of the q axis, a current reference (id, ref) is generated, a torque reference (le, ref) is generated, an absolute value reference (|&psgr;|ref) of a flux linkage is generated from the currents and switching commands are formed on the basis of the torque reference (le, ref) and the flux reference (|&psgr;|ref) using the optimum switching table (5).

Abstract: The selection of the dead time in the case of a half-bridge inverter influences the efficiency thereof. The optimal dead time, and thus the optimal switching-on time of a lower half-bridge transistor (T2) is accomplished according to the invention by virtue of the fact that switching on is delayed until the current in a level shift transistor (T3) has dropped below a given threshold. A further aspect of the invention consists in that the delay in switching on the lower half-bridge transistor (T2) is immediately suppressed whenever a charging current flows in a trapezoidal capacitor, and this is accompanied by the rise of the half-bridge output voltage (UHB) after the traversal of a minimum.

Abstract: A transistor region for defining a transistor receiving an address signal at a gate thereof is provided in or near a region below an address interconnection line transmitting a corresponding address signal. The corresponding address signal and the gate electrode of the corresponding transistor are connected together by an intermediate interconnection line extending only in the region having the corresponding address interconnection line arranged. Accordingly, a high speed switching of address signals can be achieved.

Abstract: When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ).

Abstract: An embodiment of the invention is a four transistor SRAM 10 that contains at least one ferroelectric capacitor 20,21.

Abstract: An associative memory carries out a search operation in plural fields. The search data 3-1 through 3-r in fields, r in number, are supplied to the primary associative memories 20-1 through 20-r. The i-th primary associative memory 20-i carries out the search operation, produces the primary match line 17-1-1 through 17-m-r, and maintains the state of logical AND operation by every word of the primary match line 17-j-1 through 17-j-r, the secondary match line 18-j-1 through 18-j-r, and memory means m-j when primary search enabling signal 10-i is in a valid state. Supplied with the states maintained in the stored information in each word and memory means 43, the primary associative memory 20-i provides the intermediate data 93-i. The secondary associative memory 21-i with words, m in number, searches for the intermediate data 93-i and produces the secondary match line 18-i-1 through 18-i-m when secondary search enabling signal 11-l is in a valid state.

Abstract: To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and-a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.

Abstract: A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory. A memory is also described with an array for data storage, a plurality of data input pins, and a separate pin for receiving either additional data or a serial sequence of write enable signals applicable to data received by the plurality of data input pins. The additional data that the separate pin can receive includes, for example, error detection and correction (EDC) information. A method is also described for multiplexing write enable information and error detection and correction information.

Abstract: A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.

Abstract: In magnetic memories it is important to be able to switch the states of the memory elements using minimal power i.e. external fields of minimal intensity. This has been achieved by giving each memory element an easy axis whose direction parallels its minimum surface dimension. Then, when the magnetic state of the element is switched by rotating its direction of magnetization, said rotation is assisted, rather than being opposed, by the crystalline anisotropy. Consequently, relative to the prior art, a lower external field is required to switch the state of the element.

Abstract: A storage magnetic element, which minimizes the power loss in the planar winding due to the fringe magnetic field associated with a discrete air gap, is presented. The invention describes a construction technique wherein the magnetic core is formed by an E section made of high permeability magnetic material and an I section made by a material capable to store energy due to its distributed gap structure. The I section of the magnetic core in one of the embodiments is covered by an electrically conductive shied to force the magnetic flux into the I section and to minimize the component of the fringe magnetic field perpendicular on the planar winding. In another embodiment of this invention the electrically conductive shield is replaced by a high magnetic permeability material to accomplished the same goal of reducing the magnetic field component perpendicular on the planar winding.

Abstract: A memory uses multiple threshold levels in a memory cell that are not a power of two, and further uses a cell mapping technique wherein the read mapping is only a partial function The domain of read states for a single three-level memory cell, for example, has three states, but only two of them can be uniquely mapped to a bit. The domain of read states for two three-level memory cell, for example, has nine states, but only eight of them can be uniquely mapped to three bits. Although the read mapping is only partial, the voltage margin for the three-level memory cells is larger that the voltage margin available in the commonly used four-level memory cells. This increased voltage margin facilitates memory cell threshold voltage sensing, thereby increasing the reliability of the memory.

Abstract: A non-volatile memory device may include a string of serially connected memory cell transistors with each memory cell transistor of the string being connected to a different word line. The non-volatile memory device may be programmed by applying a pass voltage to a first word line connected to a first memory cell transistor of the string, by applying a coupling voltage to a second word line connected to a second memory cell transistor of the string, and by applying a program voltage to a third word line connected to a third memory cell transistor of the string. More particularly, the coupling voltage can be greater than a ground voltage of the memory device, and the pass voltage and the coupling voltage can be different.

Abstract: An electrically erasable programmable read-only memory receives a single supply voltage and a ground voltage, and generates a first voltage higher than both the supply voltage and the ground voltage, and a second voltage lower than both the supply voltage and the ground voltage. Each memory cell in the memory has a nonvolatile storage transistor with a floating gate. To erase the memory cell, the first voltage is applied on a first side of the floating gate and the second voltage is on a second, opposite side of the floating gate. To program the memory cell, the second voltage is applied on the first side of the floating gate, and the first voltage is applied on the second side of the floating gate.

Abstract: A complimentary non-volatile memory (CNVM) cell includes an n-channel transistor and a p-channel transistor that have drains connected like a CMOS inverter, and that are controlled by a shared floating gate and a shared control gate. The CNVM cell is programmed by band-to-band tunneling (BBT) electrons generated in the source of p-channel transistor, and is erased by BBT holes generated in the source of n-channel transistor (or by back tunneling of electrons from the floating gate). Read out is performed using a select transistor connected to the drains of the n-channel and p-channel transistors.

Abstract: In a non-volatile semiconductor memory, a largo current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltage thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate.

Abstract: A non volatile memory includes a plurality of transistors having a non conductive storage medium. The transistors are erased by injecting holes into the storage medium from both the source edge region and drain edge region of the transistor. In one example, the storage medium is made from silicon nitride isolated from the underlying substrate and overlying gate by silicon dioxide. The injection of holes in the storage medium generates two hole distributions having overlapping portions. The combined distribution of the overlapping portions is above at least a level of the highest concentration of program charge in the overlap region of the storage medium. In one example, the transistors are programmed by hot carrier injection. In some examples, the sources of groups of transistors of the memory are decoded.

Abstract: Methods and apparatus for storing erase counts in a non-volatile memory of a non-volatile memory system are disclosed. According to one aspect of the present invention, a data structure in a non-volatile memory includes a first indicator that provides an indication of a number of times a first block of a plurality of blocks in a non-volatile memory has been erased. The data structure also includes a header that is arranged to contain information relating to the blocks in the non-volatile memory.

Abstract: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

Abstract: A leakage control circuit and DRAM equipped therewith. The leakage control circuit includes a differential amplifier, a first voltage divider, a second voltage divider, MOS transistors, and a charge pump. The first voltage generates a first reference voltage. The second voltage divider generates a second reference voltage. The differential amplifier has a first input receiving the first reference voltage, a second input receiving the second reference voltage, and an output coupled to the input of the charge pump. MOS transistors have drains coupled to the first input of the differential amplifier, gates coupled to the output of the charge pump, and sources coupled to a ground potential.

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: A digital storage device mounted in a pen shaped housing has a barrel, a reservoir tube assembly and a memory device with a USB plug. The memory device is held in the barrel and the USB plug can be extended from the barrel to insert into a USB socket of a computer to access digital data from the computer. In addition, the memory device uses a flash memory IC for storing data so that the memory device does not use a battery. Therefore, the digital storage device can be used to store data and to perform other functions such as writing.

Abstract: A ferroelectric memory capable of multi-value memory retention is provided with hardly modifying a circuit of the related art. The period for which a write pulse is applied changes depending upon a value to be stored, so that multi-value storage is attained. Only one voltage is prepared for the write pulse, and a reset or read pulse and the write pulse have the same voltage, thus achieving a ferroelectric memory having a multi-value storage function using only one voltage source.

Abstract: In a method of forming a ferroelectric film according to the present invention, pulsed laser light or pulsed lamp light is applied to an amorphous oxide film formed over a substrate to form microcrystalline nuclei of oxide in the oxide film. A light transmission and/or absorption film is formed over the oxide film. Crystallization of the oxide is performed by applying pulsed laser light or pulsed lamp light from above the light transmission and/or absorption film to form a ferroelectric film.

Abstract: The present invention relates to a disk cartridge in which a disk-like recording medium such as an optical disk, a magneto-optical disk and a magnetic disk is accommodated within a disk compartment of a cartridge housing, a disk recording medium device in which the disk-like recording medium is accommodated in advance within the disk compartment so as to become freely rotatable and a disk recording and/or reproducing apparatus for recording and/or reproducing information by using this disk recording medium device.

Abstract: There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry.

Abstract: In a configuration for checking an address generator, a memory apparatus is configured such that it can store values of address signals that are present on lines of an address bus. The stored values can then be output to at least one access point where the values are provided for further evaluation.

Abstract: A non-volatile flash memory system counts the occurrences of an event, such as the number of times that individual blocks have been erased and rewritten, by updating a compressed count only once for the occurrence of a large number of such events. A random or pseudo-random number generator outputs a new number in response to individual occurrences of the event, and updates the compressed count when an output of the random number generator matches a predetermined number. The probability of the predetermined number being generated by the random number generator in response to a single event may be varied as the function of some other factor, such as the value of the compressed count, when that provides more useful tracking of the number of events. These techniques also have application to monitoring other types of recurring events in flash memory systems or in other types of electronic systems.

Abstract: A system and method for decreasing the memory access time by determining if data will be written directly to the array or be posted through a data buffer on a per command basis is disclosed. A memory controller determines if data to be written to a memory array, such as a DRAM array, is either written directly to the array or posted through a data buffer on a per command basis. If the controller determines that a write command is going to be followed by another write command, the data associated with the first write command will be written directly into the memory array without posting the data in the buffer. If the controller determines that a write command will be followed by a read command, the data associated with the write command will be posted in the data buffer, allowing the read command to occur with minimal delay, and the posted data will then be written into the array when the internal I/O lines are no longer being used to execute the read command.

Abstract: An engine control system stores data indicating a monitor frequency ratio for each failure diagnosis target item in EEPROM and standby RAM being backed up by a battery. The failure diagnosis target items are designated based on Rate Base Monitor Method. A data item of the data indicating a monitor frequency is incremented by one, at one time at the maximum, for one operation period of the system. When the system starts its operation, whether a value S [i] in standby RAM is greater by one than a value E [i] in EEPROM is determined for each data item. When the determination is affirmed for a given data item, it is determined that storing of the given data item is not completed in EEPROM for the preceding operation period. The value S [i] is thereby written in EEPROM.

Abstract: Methods and apparatus for tracking defective blocks such that at least some of the defective blocks may be readily identified and tested for usability when desirable are disclosed. According to one aspect of the present invention, a method for identifying spare blocks within a non-volatile memory includes subjecting at least one defective physical block associated with the non-volatile memory to a test that is arranged to determine if the defective physical block is usable. The method also includes determining when the defective physical block passes the test, and identifying the defective physical block as a usable physical block when it is determined that the defective physical block passes the test.

Abstract: An inexpensive, re-configurable storage device for programmable and application specific logic is disclosed. A configurable storage device comprising a storage circuit including at least one output and at least one input capable of changing said output in a well defined response sequence; and a configuration circuit including at least one memory element to control a portion of said storage circuit; and a programmable means of altering said storage circuit response sequence. This allows the user greater flexibility in picking the most desired flip-flop from a variety of choices. The user programmed flip-flop option converts to an application specific conductive pattern with no change in storage device performance.

Abstract: A tertiary CAM cell with three bits of storage is disclosed. The three bits of storage are arranged to support three stable states which can be read from the CAM cell without requiring a charge restoration operation. The three stables states are those states where one of the three bits is at a first logical state while the remaining two bits are at a second logical state. The three stables states may be used to encode the three logical states used in a ternary CAM.

Abstract: A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell.

Abstract: A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.

Abstract: In a ferroelectric capacitor, two displacements (points b and c) of a remanent polarization correspond to data “1” and one displacement (point a) of the remanent polarization corresponds to data “0”. When the data “1” is written, either of two electric voltage pulses different in potential or in pulse width is applied to the ferroelectric capacitor to position the displacement of the remanent polarization in the ferroelectric capacitor at the point b or at the point c. When the data “0” is written, on the other hand, the displacement of the remanent polarization in the ferroelectric capacitor is positioned at the point a.

Abstract: In an MRAM having main and sub-structures, selecting transistors are arranged so as to meet the arrangement order of main word lines, sub-word lines and the selecting transistors. The selecting transistor is driven to cause a snap back phenomenon to occur. As a result, data can be written to a memory cell using a substrate current, not a channel current. Moreover, a data may be written into a selected memory cell by discharge the charge which is charged in the main and sub word lines corresponding to the memory cell.

Abstract: A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

Abstract: A semiconductor device have memory cell array including a plurality of memory cells, each of which includes first and second transistors and connected in series between a bit line for normal access only and a bit line for refreshing only, and a capacitor connected to a connection node at which the first and second transistors are tied. A word line for normal access only and a word line for refreshing only are connected to control terminals of the first and second transistors, respectively. The semiconductor memory device has a late-write configuration in which writing to a memory cell at an externally input write address is performed, being delayed by a predetermined number of write cycles exceeding at least one, and has at least a circuit for checking whether the write address externally input the predetermined number of write cycles earlier matches the refresh address.

Abstract: The present invention provides a semiconductor memory cell repairing apparatus and method that can effectively repair memory cells although a various type of failures in memory cells are generated when a rule in the failure is detected.

Abstract: A synchronous SRAM includes a register sequentially providing data signals of the burst length in a test mode, and a transfer circuit applying data signals output from the register to a memory array for burst-writing, and providing to an external source via an IO buffer a data signal read out in a burst manner later than the burst writing by 1 clock cycle. It is not necessary to additionally apply a data signal for writing. The required number of address signals can be reduced. Thus, testing can be simplified.