Patents Issued in September 28, 2004
  • Patent number: 6797947
    Abstract: An apparatus and method for calibrating a mass spectrometer by internally introducing calibration masses at a post-source stage of the mass spectrometer is provided. A source of lock mass ions adjacent the ion optics creates lock mass ions within the ion optics. Lock mass ions mix with the analyte ions in the ion optics prior to mass analysis. The source of lock mass ions may include various means for ionizing lock mass molecules including but not limited to photoionization, field desorption-ionization, electron ionization, and thermal ionization means. An apparatus and method of mass calibrating a tandem mass spectrometer is also provided. The mass calibration apparatus includes a collision cell for fragmenting analyte ions and a source of lock mass ions adjacent said collision cell for creating lock mass ions in the collision cell.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: September 28, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Charles W. Russ, IV, Steven M. Fischer
  • Patent number: 6797948
    Abstract: Disclosed is an ion guide for transferring ions from and ion source through vacuum regions in a mass spectrometer. The ion guide includes a housing with insulating holders provided to secure electrode rods of multiple devices in longitudinal alignment for the transmission of ions from the ion source to a mass analyzer. The device comprise a plurality of electrode rods each having at least one connecting leg. The rods are connected to the insulating holders via these connecting legs using connecting plates mounted on either side of and adjacent to each insulating border such that the connecting plates are in electrical contact with connecting legs. The connecting plates also have positioning groves to hold the connecting legs in position such that electrical contact is maintained between groups of the electrode rods.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: September 28, 2004
    Assignee: Bruker Daltonics, Inc.
    Inventor: Houle Wang
  • Patent number: 6797949
    Abstract: There is provided a tandem mass spectrometry that, in a quadrupole ion trap, allows small mass-number product ions to be detected without lowering the sensitivity and the resolution. In the quadrupole ion trap, ions are produced by an ion source. Next, the ions are accumulated within a 3-dimensional quadrupole electric field formed by a pair of endcap electrodes and a ring electrode. Finally, the accumulated ions are isolated and dissociated, then being detected. In this quadrupole ion trap, there are provided a mechanism for introducing a laser light, and a mechanism for generating a supplemental alternating-current electric field at the time of the ion dissociation. Moreover, the direction of the supplemental alternating-current electric field and the introduction direction of the laser light are made identical to each other.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: September 28, 2004
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yuichiro Hashimoto, Hideki Hasegawa, Takashi Baba, Akihiko Okumura, Izumi Waki
  • Patent number: 6797950
    Abstract: A three section linear or two-dimensional (2D) quadrupole ion trap as a high performance mass spectrometer is described. Mass analysis is performed by ejecting ions radically out a slot formed in one of the rods using the mass selective instability mode of operation. The slot geometry is optimized to yield high ejection efficiencies. Resolution can be controlled by using appropriate end section potentials to control the axial spread of the ion cloud. Multiple detectors can be used for enhancing sensitivity and for enabling enhanced ion analysis techniques in the ion trap.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: September 28, 2004
    Assignee: Thermo Finnegan LLC
    Inventors: Jae C. Schwartz, Michael W. Senko
  • Patent number: 6797951
    Abstract: A charged particle analyzer electrode assembly of miniaturized physical size and photolithographic process element fabrication capability. The provided electrode assembly is made of conductive materials including semiconductor materials and metal materials. Individual electrodes in the assembly are made of for example plural layers of semiconductor or metal held in place by discrete insulator layers. Bandpass particle energy selection characteristics are achieved in the analyzer through a combination of analyzer particle path geometry configuration and the particle acceleration electrical potential selection. Selected particles are allowed to pass through the analyzer under these influences and non selected particles are excluded. Assembly of individual analyzer electrode assemblies into a multiple element analyzer array usable for example on an aircraft or spacecraft is included. Both millimeter sized and micrometer sized arrangements of the invention are contemplated.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: September 28, 2004
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Carl L. Enloe
  • Patent number: 6797952
    Abstract: According to the invention, in selecting an analyzed area of a scanning atom probe (SAP), there is adopted a method of using a tip of the lead-out electrode of SAP as a scanning probe of a scanning tunneling microscope (STM) and drawing a surface shape of a sample to thereby select the analyzed area and with regard to the tip of the lead-out electrode of SAP, there is formed an exclusive probe in a needle-like shape by a CVD micromaching technology or a lithographic method using focused ion beam in order to promote accuracy of the scanning probe of STM. Further, a conical dome of a conductive material is formed at the tip of the conical electrode mechanically formed by using a CVD fabricating method using focused ion beam and the tip is shaped by sputter etching to thereby form the lead-out electrode near to an ideal shape.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: September 28, 2004
    Assignees: SII NanoTechnology Inc., Kanazawa Institute of Technology
    Inventors: Takashi Kaito, Osamu Nishikawa, Takaya Yagyu
  • Patent number: 6797953
    Abstract: A charged particle beam system uses multiple electron columns to increase throughput. One or more multiple electron emitters are in one or more vacuum sealable gun chambers to allow the gun chamber to be replaced with electrons guns having emitters that have been previously conditioned so that the system does not need to be out of service to condition the newly installed emitters.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: September 28, 2004
    Assignee: FEI Company
    Inventors: Robert L. Gerlach, Paul P. Tesch, Walter Skoczylas
  • Patent number: 6797954
    Abstract: An electron beam (area beam) having a fixed area is irradiated onto the surface of a semiconductor sample, and reflected electrons from the sample surface are imaged by the imaging lens, and images of a plurality of regions of the surface of the semiconductor sample are obtained and stored in the image storage unit, and the stored images of the plurality of regions are compared with each other, and the existence of a defect in the regions and the defect position are measured. By doing this, in an apparatus for testing a pattern defect of the same design, foreign substances, and residuals on a wafer in the manufacturing process of a semiconductor apparatus by an electron beam, speeding-up of the test can be realized.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: September 28, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Shinada, Yusuke Yajima, Hisaya Murakoshi, Masaki Hasegawa, Mari Nozoe, Atsuko Takafuji, Katsuya Sugiyama, Katsuhiro Kuroda, Kaoru Umemura, Yasutsugu Usami
  • Patent number: 6797955
    Abstract: The disclosure relates to filtered e-beam inspection and review. One embodiment pertains to the filtered inspection or review of a specimen with a high aspect ratio feature. Advantageously, the energy and/or angular filtering improves the information retrievable relating to the high aspect ratio feature on the specimen. Another embodiment pertains to a method for energy-filtered electron beam inspection where a band-pass energy filtered image data is generated by determining the difference between a first high-pass energy-filtered image data set and a second high-pass energy-filtered image data set.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: September 28, 2004
    Assignee: KLA-Tencor Technologies Corporation
    Inventors: David L. Adler, Luca Grella, Gabor D. Toth
  • Patent number: 6797956
    Abstract: In a transmission electron microscope with phase contrast imaging, the illumination of the object to be imaged takes place with an annular illuminating aperture. An annular phase-shifting element with a central aperture is arranged in a plane Fourier transformed with respect to the object plane. The annular phase-shifting element confers a phase shift of &pgr;/2 on a null beam, while the radiation of higher diffraction orders diffracted at the object in the direction of the optical axis passes through the central aperture of the annular phase-shifting element and consequently is not affected, or only slightly affected, by the phase-shifting element. The annular illuminating aperture is preferably produced sequentially in time by a deflecting system, which produces a beam tilt in a plane conjugate to the object plane.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: September 28, 2004
    Assignee: Leo Elektronenmikroskopie GmbH
    Inventor: Gerd Benner
  • Patent number: 6797957
    Abstract: An infrared detection element having a single-crystalline base layer 3 with a thickness of 50 nm to 10 &mgr;m having a principal surface, a first electrode layer 4 formed on the principal surface of the single-crystalline base layer 3, a ferroelectric layer 5 which is formed on the first electrode layer 4 and is composed of a single-crystalline layer or a unidirectionally oriented layer. Distortion of the single-crystalline layer or a unidirectionally oriented layer in a surface parallel to the principal surface of the single-crystalline base layer 3 is elastically constrained by the single-crystalline base layer 3. The infrared detection element further has a second electrode layer 6 formed on the ferroelectric layer 5. An amount of charge varies with changes in temperature caused by irradiation of infrared light to the ferroelectric layer 5.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: September 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Kawakubo, Kazuhide Abe, Kenya Sano
  • Patent number: 6797958
    Abstract: A nondestructive method is provided for efficiently determining thickness of a sol-gel coating formed upon a metallic substrate. A value of infrared energy reflected from the metallic substrate without the sol-gel coating is determined. A value of infrared energy reflected from the metallic substrate with the sol-gel coating is determined. A value of infrared energy absorbed in the sol-gel coating is determined, and a value of the infrared energy absorbed in the sol-gel coating is correlated to a thickness of the sol-gel coating.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: September 28, 2004
    Assignee: The Boeing Company
    Inventors: Paul H. Shelley, Richard G. Wire, Terry C. Tomt
  • Patent number: 6797959
    Abstract: The sensitivity adjusting equipment applied to a photoelectric smoke detector is provided. The photoelectric smoke detector includes a luminous component for providing an input light and a detecting component for receiving an even output light. The sensitivity adjusting equipment includes a light-scattering device having a scattering component and an adjustable hole for scattering the input light evenly and adjusting an intensity of the input light so as to output the even output light to the detecting component. The sensitivity adjusting equipment also includes a movable platform having a first brace connected to the photoelectric smoke detector and a supporting base having a second brace connected to the light-scattering device. The movable platform is moved to make the photoelectric smoke detector and the light-scattering device combined to adjust the sensitivity of the photoelectric smoke detector.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: September 28, 2004
    Assignee: Precision Instrument Development Center, National Science Council
    Inventors: Shenq-Tsong Chang, Ho-Lin Tsay, Tai-Shan Liao, Bih-Chang Wang, Ting-Ming Huang
  • Patent number: 6797960
    Abstract: A semiconductor radiation imaging assembly comprises a semiconductor imaging device including at least one image element detector. The imaging device is arranged to receive a bias for forming the at least one image element detector. The assembly also includes bias monitoring means for monitoring the bias for determining radiation incident on the image element detector. Preferably, the imaging device comprises a plurality of image element detectors the bias for at least some of which is monitored for determining incident radiation. More preferably, the bias for all the detector elements is monitored.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: September 28, 2004
    Assignee: Simage Oy
    Inventors: Konstantinos Evangelos Spartiotis, Stefan Jurthe, Jouni Pyythiä
  • Patent number: 6797961
    Abstract: An X-ray sensing array substrate that includes a storage capacitor having first and second capacitor electrodes and a pixel electrode over the storage capacitor. One of the capacitor electrodes contacts a drain electrode of a thin film transistor through a first contact hole in an insulating layer. The pixel electrode contacts that capacitor electrode through a second contact hole through a second insulting layer. Therefore, the drain electrode is connected to the storage capacitor through only one contact, while the pixel electrode contacts the storage capacitor through only one contact. This reduces the drain electrode to capacitor resistance, reduces the voltage drop, and increases the sensitivity of the array.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: September 28, 2004
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Ky-Seop Choo, June-Ho Park
  • Patent number: 6797962
    Abstract: An electrostatic corrector for eliminating the chromatic aberration of particle lenses, includes a corrector having a straight optical axis and an electrostatic quadrupole for allocating to the objective lens. Two corrector pieces are positioned behind the quadrupole, along the optical axis in the direction of radiation. Each corrector piece has three electrical quadrupole fields with an overlying circular lens field. The quadrupole fields, however, are rotated 90° about the optical axis in relation to each other. This arrangement is adjusted so that the astigmatic first image of one sectional view lies in one corrector piece and the astigmatic first image perpendicular thereto, of the other sectional view, lies in the other corrector piece, with another electrostatic quadrupole being located on the output side.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: September 28, 2004
    Assignee: CEOS Corrected Electron Optical Systems GmbH
    Inventors: Harald Rose, Stephan Uhlemann, Christoph Weissbacker
  • Patent number: 6797963
    Abstract: The present invention relates to a deflector of a micro-column electron beam apparatus and method for fabricating the same, which forms a seed metal layer and a mask layer on both sides of a substrate, and exposes some of the seed metal layer on which deflecting plates, wirings and pads are to be formed by lithography process using a predetermined mask. The wirings and pads are formed by plating metal on the exposed portion, and some of the metal layer is also exposed on which the deflecting plates are to be formed using a predetermined mask, and then the metal is plated with desired thickness, thereby the deflecting plates are completed. Therefore, by forming plurality of deflecting plates on both sides of the substrate at the same time through plating process, alignment between the deflecting plates formed on both sides of the substrate can be exactly made, and by fabricating a deflector integrated with the substrate and deflecting plates in a batch process, productivity and reproducibility is improved.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: September 28, 2004
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Kuk Choi, Dae Yong Kim, Dong Yel Kang
  • Patent number: 6797964
    Abstract: This ion source is set up to satisfy a relation L<3.37B−1(VA)×10−6 where the arc voltage applied between a plasma production vessel 2 and a filament 8 is VA[V], the magnetic flux density of a magnetic field 19 within the plasma production vessel 2 is B[T], and the shortest distance from a most frequent electron emission point 9 located almost at the tip center of the filament 8 to a wall face of the plasma production vessel 2 is L[m].
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: September 28, 2004
    Assignee: Nissin Electric Co., Ltd.
    Inventor: Takatoshi Yamashita
  • Patent number: 6797965
    Abstract: A charged particle beam apparatus includes a charged particle source which generates a charged particle beam, a condenser lens which converges the charged particle beam, a deflector which deflects the charged particle beam to scan a sample with the charged particle beam, an objective lens which converges the charged particle beam on the surface of the sample, a sample position imaginary variation detection part which detects an imaginary variation of a sample position caused by variation of the focal position of the charged particle beam due to variation in the potential of the sample, and a sample position imaginary variation compensation part which compensates for the detected imaginary variation of the sample position.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: September 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideaki Abe
  • Patent number: 6797966
    Abstract: A quick-install irradiation unit for irradiating a surface includes an adapter that accepts a frame for supporting an ultraviolet lamp with a reflector or a lens for focusing the radiation on the surface. The unit may include a housing secured to one end of the frame containing a drive motor and a cam assembly which oscillate the reflector, if the radiation is focused on a predefined area of the surface at any given time. The unit can be quickly installed in any orientation on practically any flat surface.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: September 28, 2004
    Assignee: Engineering Dynamics, Ltd.
    Inventors: George Robert Summers, Forwood Cloud Wiser, III
  • Patent number: 6797967
    Abstract: A method is presented for compensating for the effects of charge neutralization in calculating the ‘true’ ion dose, i.e., the dose assuming no changes of charge state of ions during an implantation process. An ion beam is generated under normal operating conditions, e.g., stable vacuum exists, and no target is being implanted. At least one additional detector would be positioned in the target chamber, and a dose measurement conducted simultaneously with a measurement of the beam current with the Faraday, which is located outside of the charge neutralization region, to establish a reference ratio. A wafer is then placed at the target location, and simultaneous measurements made with the additional detector and Faraday, as before, to determine the ratio between the beam current and the detector during wafer implantation. Any drift from the reference ratio indicates the dose error due to charge neutralization from wafer outgassing during implantation.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: September 28, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tom Tse, Zhiyong Zhao, David M. Hendrix
  • Patent number: 6797968
    Abstract: An ion beam processing apparatus comprises a beam line vacuum chamber from an ion source to a processing chamber. The apparatus further comprises a beam line structure for transporting ion beam from the ion source through the beam line vacuum chamber to the processing chamber. A mass analysis magnet unit is arranged from the outside in a partial section of the beam line vacuum chamber. An effective magnetic field area of the mass analysis magnet unit is disposed in a partial section of the beam line structure. Continuous cusp field forming magnet apparatuses are arranged at the series of beam line vacuum chamber part of the beam line structure to confine ion beam by forming continuous cusp fields.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: September 28, 2004
    Assignee: Sumitomo Eaton Nova Corporation
    Inventors: Mitsukuni Tsukihara, Yoshitaka Amano, Mitsuaki Kabasawa, Michiro Sugitani, Hiroki Murooka, Hiroshi Matsushita
  • Patent number: 6797969
    Abstract: A multi-gun FIB system for nanofabrication provides increased throughput at reduced cost while maintaining resolution. Multiple guns are maintained in modular gun chambers that can be vacuum isolated from the primary vacuum chamber containing the targets. A system can include multiple gun chambers, each of which van include multiple guns, with each gun chamber being capable of being vacuum isolated, so that each gun chamber can be removed and replaced without disturbing the vacuum in other gun chambers or in the main chamber. An optical column is associated with each gun. Optical elements for multiple columns can be formed in a bar that extends into several columns. Some of the optical elements are positioned in the gun chambers and others are positioned in the primary vacuum chamber. A through-the-lens secondary particle collection can be used in connection with each of the individual columns.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: September 28, 2004
    Assignee: FEI Company
    Inventors: Robert L. Gerlach, Paul P. Tesch, Lynwood W. Swanson, Mark W. Utlaut
  • Patent number: 6797970
    Abstract: A device for sterilizing water flowing through a sanitary appliance has a housing, which comprises an inlet and an outlet for the water; a UV lamp, which is disposed inside the housing and the radiation of which is directed towards the water flowing through; and a throughflow chamber for the water, which is disposed in the housing and surrounds the UV lamp.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: September 28, 2004
    Assignee: Hansa Metallwerke AG
    Inventors: Raimond Gatter, Erwin Reich, Horst Kunkel
  • Patent number: 6797971
    Abstract: Apparatus for providing substantially two-dimensionally uniform irradiation of a relatively large planar target surface. Each of at least two substantially identical sources of radiation irradiate the target surface. The longitudinal axes of the sources of radiation are substantially parallel with each other, defining a plane substantially parallel to the target surface. Each of the sources of radiation is within a respective elongated elliptical reflecting trough and is spaced from the focal axis of the respective trough. Each trough terminates in an opening defining a rectangular plane substantially perpendicular to the major axis of the trough and substantially parallel to the longitudinal axis of the bulb.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: September 28, 2004
    Assignee: Fusion UV Systems, Inc.
    Inventors: Miodrag Cekic, Boris Geller
  • Patent number: 6797972
    Abstract: A high-polymer neutron shielding material which scarcely reduces the hydrogen number density when exposed to a high temperature of 150 to 200° C. for a long time period A heat-setting type epoxy resin is employed. The base resin is selected from various epoxy resins such as bisphenol A type epoxy resin. The hardener is selected from alicyclic polyamine, polyamide amine, aromatic polyamine, acid anhydride, and so on. These materials are mixed and hardened at a temperature higher than the room temperature. To give a flame resistance to the hardened resin, a fire retardant such as magnesium hydroxide is added to the mixture. To improve the neutron shielding performance of the hardened resin, a neutron absorbing material is added to the mixture. Further, to increase the moderating performance, hydrogenated bisphenol A epoxy resin is used as the base resin or metal hydride or hydrogen absorbing alloy is added.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: September 28, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Mamoru Kamoshida, Masashi Oda, Takashi Nishi, Kiminori Iga, Masashi Shimizu
  • Patent number: 6797973
    Abstract: An apparatus that acts as a shield for radiopharmaceuticals and protects individuals from radioactivity includes a first body with a first hollow core, a second body with a second hollow core and a third body with a third hollow core. The first hollow core, second hollow core and third hollow core collectively house an insert. The insert houses a hypodermic syringe. A first connection means releasably communicates the first body with the second body. A second connection means releasably communicates the first body with the third body. The second body comprises a piston actuator. The piston actuator can be operated to depress the piston of the hypodermic syringe while the first body is in communication with the second body, and while the third body is removed.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: September 28, 2004
    Inventor: Albert L. Zens
  • Patent number: 6797974
    Abstract: An apparatus for determining the fitness of a bank note by sensing the bank note transported along a transport path by a transport device. The apparatus includes a plurality of identical sensor and illumination units positioned along each side of the transport path whereby the sensor and illumination units are focused at a single predetermined section of the transport path.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: September 28, 2004
    Assignee: Giesecke & Devrient
    Inventors: Achim Philipp, Heinz Hornung
  • Patent number: 6797975
    Abstract: Conventionally, a particle/defect inspection apparatus outputs a total number of detected particles/defects as the result of detection. For taking countermeasures to failures in manufacturing processes, the particles/defects detected by the inspection apparatus are analyzed. Since the inspection apparatus outputs a large number of detected particles/defects, an immense time is required for analyzing the detected particles/defects, resulting in a delay in taking countermeasures to a failure in the manufacturing processes. In the present invention, an apparatus for optically inspecting particles or defects relates a particle or defect size to a cause of failure in an inspection result. A data processing circuit points out a cause of failure from the statistics on the inspection result, and displays information on the inspection result.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: September 28, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hidetoshi Nishiyama, Minori Noguchi, Yoshimasa Ooshima, Akira Hamamatsu, Kenji Watanabe, Tetsuya Watanabe, Takahiro Jingu
  • Patent number: 6797976
    Abstract: For examining defects in sheet material, in particular bank notes, the sheet material is convexly curved and tested in the area of the convex curvature. A detector is disposed tangentially to an apex line of the convex curvature for detecting elevations on the bank note surface due to bank note defects against a light background. A suitable optic is used to image this silhouette onto the detector. The detector is formed as a pixel array, and the number and height of shaded pixels are assessed as measures of defect density and size and nature of defects.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: September 28, 2004
    Assignee: Giesecke & Devrient
    Inventors: Christian Pechan, Bernd Wunderer
  • Patent number: 6797977
    Abstract: Stimulating rays are irradiated linearly along a main scanning direction onto a stimulable phosphor sheet, on which a radiation image has been stored, and light emitted from the linear area of the sheet exposed to the linear stimulating rays is received with a line sensor via a light collecting optical system. The line sensor comprises photoelectric conversion devices arrayed along the main scanning direction. An optical guide member is located between the light collecting optical system and the line sensor. The optical guide member has a reflection surface for reflecting the emitted light, which has been radiated out from the light collecting optical system and has spread over a range wider than a width of each of the photoelectric conversion devices, the width being taken in a sub-scanning direction, such that the photoelectric conversion devices can receive the emitted light.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: September 28, 2004
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Yasuda Hiroaki
  • Patent number: 6797978
    Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: September 28, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Fernando N. M. Gonzalez, Raymond A. Turi
  • Patent number: 6797979
    Abstract: The invention relate to a damascene chalcogenide memory cell structure. The damascene chalcogenide memory cell structure is fabricated under conditions that simplify previous process flows. The damascene chalcogenide memory cell structure also prevents volatilization of the chalcogenide memory material.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: September 28, 2004
    Assignee: Intel Corporation
    Inventors: Chien Chiang, Jong-Won Lee, Patrick Klersy
  • Patent number: 6797980
    Abstract: A metal coordination compound suitable as an organic material for a luminescent device is represented by the following formula (1):
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: September 28, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Takiguchi, Shinjiro Okada, Akira Tsuboyama, Koji Noguchi, Takashi Moriyama, Jun Kamatani, Manabu Furugori
  • Patent number: 6797981
    Abstract: A test wafer is provided, in particular for use in monitoring inspection installations for semiconductor fabrication that are based on the analysis of scattered or reflected radiation. The test wafer is subdivided into a multiplicity of regularly disposed chip fields. The test wafer is characterized in that the test wafer has at least a first type of structures, which are disposed chip-field-periodically, and at least a second type of structures, which are disposed non-chip-field-periodically at predetermined locations on the test wafer.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: September 28, 2004
    Assignee: Infineon Technologies AG
    Inventor: Michael Schmidt
  • Patent number: 6797982
    Abstract: An active matrix substrate includes base substrate, gate lines, data lines, thin-film transistors and pixel electrodes. The gate lines are formed on the base substrate. The data lines are formed over the gate lines. Each of the data lines crosses all of the gate lines with an insulating film interposed therebetween. The thin-film transistors are formed over the base substrate. Each of the thin-film transistors is associated with one of the gate lines and operates responsive to a signal on the associated gate line. Each of the pixel electrodes is associated with one of the data lines and one of the thin-film transistors and is electrically connectable to the associated data line by way of the associated thin-film transistor. Each of the pixel electrodes and the associated thin-film transistor are connected together by way of a conductive member.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: September 28, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Okada, Yuichi Saito, Shinya Yamakawa, Atsushi Ban, Masaya Okamoto, Hiroyuki Ohgami
  • Patent number: 6797983
    Abstract: A method is provided to fabricate a LCOS back plane structure. The present invention utilized a HV device such as HV CMOS transistor (high voltage complementary metal oxide semiconductor transistor) and a HV capacitor layer are applied to the substrate. Furthermore, the HV capacitor layer has a higher dielectric layer and coupling ratio to sustain the higher operating voltage, such that the operating capacitance can be raised. Moreover, the HV CMOS transistor is combined with a mirror layer which has a higher reflective property, such that the LCOS back-plate structure has the better contrast and chrominance output in per area unit, when the operating voltage range is increased.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: September 28, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Ralph Chen, Marcus Yang, Yuan-Li Tsai, Ching-Chun Huang, Sheng-Hsiung Yang
  • Patent number: 6797984
    Abstract: A light emitting diode (LED) packaging structure with built-in rectification circuit is disclosed. The LED packaging structure includes an LED and a rectification circuit is formed inside the LED. Thus, the LED packaging structure is capable to receive an alternate current from an electrical main by the rectification circuit which converts the alternate current into a direct current for the LED whereby the LED can be directly connected to the electrical main and powered thereby without use of additional and external rectification device.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: September 28, 2004
    Assignee: Para Light Electronics Co., Ltd.
    Inventors: Ming-Te Lin, Ming-Yao Lin
  • Patent number: 6797985
    Abstract: An active matrix organic light-emitting diode and manufacturing method thereof is provided. A thin film transistor having a gate, a source and a drain is formed over a substrate. An anode layer is formed over the substrate such that the anode layer connects electrically with the source terminal of the thin film transistor. An organic layer is formed to cover the anode layer and the thin film transistor. The organic layer between the source and the drain serves as a channel region of the thin film transistor. A cathode layer is formed over the organic layer. Since the molecules inside the organic layer are aligned in a direction from the source to the drain and perpendicular to a direction from the anode layer to the cathode layer, electron mobility at the channel region is enhanced and the emitting efficiency of the diode is increased.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: September 28, 2004
    Assignee: Delta Optoelectronics, Inc.
    Inventors: Hsin-Fei Meng, Lai-Cheng Chen, Sheng-fu Horng, Lichi Lin
  • Patent number: 6797986
    Abstract: Is provided a resonant cavity type light emitting diode having excellent humidity durability and a light output unsaturated even several 10 mA., which is suitable for mass production. The semiconductor light emitting element has a resonator formed by one set of multi-layer reflecting films disposed at a constant distance on a GaAs substrate inclined at an angle of not less than 2 degrees in the direction [011] or [0-1-1] from the plane (100) and a light emitting layer disposed at a loop position of a standing wave in the resonator, wherein a multi-layer reflecting film disposed on the GaAs substrate side is composed of plural layers of AlxGa1-xAs (0 ≦x≦1) and a multi-layer reflecting film disposed on the opposite side of the GaAs substrate is composed of plural layers of AlyGazIn1-y-zP (0≦y≦1, 0≦z≦1), thereby achieving an improved humidity durability and an increased reflection factor by increasing the number of the reflection layers.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 28, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takahisa Kurahashi, Hiroshi Nakatsu, Hiroyuki Hosoba, Tetsurou Murakami
  • Patent number: 6797987
    Abstract: A light emitting diode with high efficient reflective metal layer is disclosed. To prevent the reflective metal layer from reacting with the epi-LED layer structure during a thermal annealing process, a transparent electrical-conductive oxide layer such as ITO is formed in between them. Four preferred embodiments are proposed to improve the ohmic contact between the ITO layer and the epi-LED layers. There are: forming ohmic contact grid pattern, or ohmic contact channels in the ITO layer, or thin GaAs layer, or thin transparent metal layer at the interface between the ITO and the epi-LED layers.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: September 28, 2004
    Assignee: United Epitaxy Co., Ltd.
    Inventor: Tzer-Perng Chen
  • Patent number: 6797988
    Abstract: The present invention discloses a light-emitting diode with enhanced light-emitting efficiency, in which the active current is prevented from flowing in the region under the top electrode so that the light-emitting efficiency as well as the brightness can be improved.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: September 28, 2004
    Assignee: Opto Tech Corporation
    Inventors: Ming-Der Lin, Jung-Kuei Hsu, San-Bao Lin, Ching-Shih Ma
  • Patent number: 6797989
    Abstract: A package for opto-electrical components includes a casing having a chamber for at least one board or tile adapted to carry the opto-electrical components. The casing includes a set of electrical connections including at least one radio-frequency differential line between the chamber and the casing exterior.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: September 28, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Giampaolo Bendelli, Enrico Di Mascio, Piero Gambini, Mario Puleo, Marco Scofet, Ian Smith
  • Patent number: 6797990
    Abstract: A boron phosphide-based semiconductor device including a substrate having thereon an oxygen-containing boron phosphide-based semiconductor layer having boron and phosphorus as constituent elements and oxygen, and a production process therefor.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: September 28, 2004
    Assignee: Showa Denko Kabushiki Kaisha
    Inventor: Takashi Udagawa
  • Patent number: 6797991
    Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} surface by an angle in an range of 13° to 90° inclusive.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: September 28, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masahiro Ishida
  • Patent number: 6797992
    Abstract: The present invention provides a high voltage semiconductor device capable of withstanding excessive breakdown and clamping voltages. The device includes a high resistivity substrate, and an epitaxially grown, low resistivity layer having a stress-relieving dopant. During production, the low conductivity region has one surface that is etched before a high conductivity region is diffused into it or epitaxially deposited on it.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: September 28, 2004
    Assignee: FabTech, Inc.
    Inventors: Roman J. Hamerski, Walter R. Buchanan
  • Patent number: 6797993
    Abstract: A monolithic IC package, includes a monolithic IC, a package receiving the monolithic IC, an external connection terminal provided in the package and electrically connected to the monolithic IC by wiring, and protection means for protecting the monolithic IC from the electrostatic discharge, wherein the external connection terminal is used as the protection means.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: September 28, 2004
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Yukihiro Terada
  • Patent number: 6797994
    Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1−xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1−xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1−yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: September 28, 2004
    Assignee: Raytheon Company
    Inventors: William E. Hoke, Katerina Y. Hur
  • Patent number: 6797995
    Abstract: A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: September 28, 2004
    Assignee: Rockwell Scientific Licensing, LLC
    Inventors: Richard L. Pierson, Jr., James Chingwei Li, Berinder P. S. Brar, John A. Higgins
  • Patent number: 6797996
    Abstract: A compound semiconductor device includes an emitter layer, a base layer which is in contact with the emitter layer and formed of a first compound semiconductor, a collector layer which is in contact with the base layer and formed of a second compound semiconductor having a wider bandgap than that of the first compound semiconductor. In the device, a delta doped layer having a higher concentration of an impurity than that of the collector layer is formed at the heterojunction interface between the collector layer and the base layer or in a region of the collector layer located at about 10 nm or less from the heterojunction interface with the base layer.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: September 28, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Hikita, Manabu Yanagihara, Tuyoshi Tanaka