Abstract: A magnetic resonance imaging method comprises application of a pulse sequence which includes one or more pulses. The pulse sequence having an intrinsic scan time based on a full sampling rate in k-space for a predetermined full ‘field-of-view’ and a reference temporal pulse shape of the magnetic gradient pulses. A series of magnetic resonance signals is acquired by means of a receiver antennae system having a spatial sensitivity profile. Undersampled signal acquisition is applied to acquire undersampled magnetic resonance signals at a predetermined reduced sampling rate in k-space, the sampling rate being reduced by a reduction factor relative the full sampling rate. The pulse sequence being is during an actual signal scan time is applied. The actual signal scan time being larger than the intrinsic signal scan time times the reduction factor.

Abstract: The use of a high temperature superconductor self-resonant planar transmit and pickup coil, transmit coil or pickup coil enables the configuration of a small, portable nuclear quadrupole resonance system for detecting contraband.

Abstract: The invention relates to a radio-frequency coil (RF-coil) (19) for use in a magnetic-resonance imaging apparatus. The RF-coil comprises a number of parallel bar-shaped electric conductors (37), which are arranged at regular intervals on an imaginary cylinder (39) and which are surrounded by a radio-frequency shield (RF-shield) (49). The bar-shaped conductors surround a measuring volume (11) of the device and are interconnected at at least one of their end portions (41, 45) by means of an electric end conductor (43, 47) extending in a plane transverse to the bar-shaped conductors.

Abstract: A first room-temperature space is formed penetrating through a cryostat along a center axis of a split-type multi-layer cylindrical superconducting coil system which has a ratio of the maximum empirical magnetic field to the central magnetic filed of not larger than 1.3 and is horizontally arranged such that the center axis of the coil is in the horizontal direction, a room-temperature shim coil system is arranged in said first room-temperature space to improve the homogeneity of the magnetic field, a second room-temperature space is formed penetrating through the cryostat and passing through the center of said split gap in the vertical direction, and a sample to be measured and an NMR probe having a solenoid-type probe coil are inserted in said second room-temperature space. Further, the NMR analyzer has a new function constituted by a system for irradiating and detecting the electromagnetic waves having wavelengths of shorter than 0.1 mm.

Abstract: A resistivity tool for investigating a wall of a borehole drilled with a non-conductive mud includes a tool body adapted to be incorporated in a logging-while-drilling tool assembly; a resistivity sensor disposed on the tool body, wherein the resistivity sensor comprises a sensor pad supporting a current injector electrode, a current return electrode, and an array of measurement electrodes; and a circuitry for controlling current injection from the current injector electrode and for measuring voltage difference between electrodes in the array of measurement electrodes, wherein the current injector electrode and the current return electrode are disposed near opposite ends of the sensor pad and the array of measurement electrodes is disposed between the current injector electrode and the current return electrode, wherein the sensor pad is constructed of an insulating material and includes a conductive shielding member, or wherein the sensor pad is constructed of a conducting material and includes insulating sec

Abstract: A mass spectrometer that includes a tray on the outer housing of the mass spectrometer for receiving a portable user interface. Each of the user interface and the tray has a transceiver port for transmitting and receiving electromagnetic wave radiation as infrared radiation. More specifically, the tray also includes a serial port connector and the portable user interface includes a receptor for receiving the serial port connected when the user interface is mounted on the tray.

Abstract: A sensor having electrodes connectable to an AC or DC voltage for powering an electrical discharge such as a corona, glow, arc, or the like. Additional electrodes connectable to analysis voltage may be proximate to the discharge providing electrodes. The discharge may ionize a sample fluid of varying chemical composition, flowing through a channel where the electrodes are situated. The discharge may be part of a group of sensors sensing the fluid flowing from a particle filter, gas chromatograph (GC) separator, thermal conductivity detector (TCD), optical sensors, photo ionization detector (PID), and to additional micro discharge devices (MDDs) and a mass spectrometer and/or a processor for analysis and processing to obtain results and information about the sample fluid composition.

Abstract: The invention relates to a method for error location in branched low voltage and medium voltage networks and to an evaluation network used therefore.

Abstract: Common path distortion (CPD) is an impairment that afflicts two-way cable systems. Point contact diodes caused by metallic corrosion in the plant mix downstream signals. Some of the mixing products fall into an upstream frequency band where they interfere with upstream signals. A good way to locate the sources of CPD is to use a system that ranges the distance to source of CPD. One prior art system uses custom-built software and hardware, injects test signals into the downstream signal path, and looks for resulting mixing products on the upstream signal path. Unfortunately, some cable systems do not have any available vacant bandwidth for testing. Digital downstream signals, which are already being carried on the plant, can be used for testing by mixing them at the test location to create a local distortion signal. The local distortion signal may be processed with an actual distortion signal using cross-correlation to range a distance to a source of CPD.

Abstract: An apparatus and a method for detecting high impedance failures in system interconnects. The apparatus and method may measure resistance of a connection of one or more representative sets of pins on a partitioned chip to a circuit board and determine if the measured resistance of each of the one or more representative sets of pins is less than a threshold value. The measuring step is executed while the circuit board is operating.

Abstract: A pulsed eddy current sensor probe includes a sensor array board. A number of sensors are arranged on the sensor array board and are operable to sense and generate output signals from the transient electromagnetic flux in a part being inspected. Each of the sensors has a differential output with a positive and a negative output. At least one drive coil is disposed adjacent to the sensors and is operable to transmit transient electromagnetic flux into the part. A first and a second multiplexer are arranged on the sensor array board and are operable to switch between the sensors. The first and second multiplexers are connected to the positive and negative outputs of the sensors, respectively.

Abstract: A method and apparatus includes a signal generator, a power supply, a micro-controller, a transmitter and a receiver for determining the condition of a line. The signal is passed through the line and any reflection is used to determine varying characteristics of the line.

Abstract: This invention teaches an arc detection and arc reduction circuit for use with power supplies for delivering power to a plasma processing system that utilizes a resonant circuit that stores energy and when the voltage drops between the cathode and anode of the processing chamber the stored energy generates a current in a current transformer in response to the voltage change to switch a magnetically coupled inductor in parallel with the cathode and anode causing a reversal of the voltage that reduces arcs in the plasma chamber. In an alternate embodiment the magnetically coupled inductor is replaced by a pulse transformer and the pulse transformer is placed in parallel with the cathode and anode causing a reversal of the voltage that reduces arcs in the plasma chamber.

Abstract: Method for detecting partial discharges and diagnostic system for electrical apparatus.

Abstract: A method and apparatus for establishing a probe configuration comprises displaying a signal icon, a measurement channel icon, and a probe configuration partition interposed therebetween. The probe configuration partition reflects the electrical characteristics of a circuit interposed between a probed signal and a measurement channel of an oscilloscope. The method accepts changes to the probe configuration partition to generate the probe configuration and uses the probe configuration to adapt a probed signal for presentation to a user.

Abstract: A system and device suitable for use in performing a DC parametric test on an external load is provided. The device may be configured to apply a desired voltage or current to the external load. The circuit device receives a forcing parameter signal, at an input and releases at an output a signal approximating the forcing parameter signal to the external load. The circuit device includes a first circuit segment between the input and the output having a search unit, an intermediate voltage point and an internal load between the intermediate voltage point and the output. A second circuit segment connected in a feedback arrangement with the first circuit segment provides the search unit with the voltage at the output. The search unit is adapted for generating a second voltage signal on the basis of the forcing parameter signal and the first voltage signal received and to apply the second voltage signal to the intermediate voltage point.

Abstract: The present invention is directed to an electric circuit test device for testing an electric circuit. The test device is insertable into a receptacle. The receptacle includes electrical terminals coupled to the electrical circuit. The device includes a housing characterized by a longitudinal axis. A plug blade assembly is disposed within the housing and configured to mate with the electrical terminals. Electrical continuity is established between the plug blade assembly and the electric circuit. A fault detection circuit is coupled to the plug blade assembly and disposed within the housing. The fault detection circuit is configured to detect a circuit status condition in the electrical circuit. A circuit status indicator assembly is coupled to the fault detection circuit and disposed normal thereto. The circuit status indicator assembly includes semiconductor light indicators that are connected substantially normal to the circuit status indicator assembly.

Abstract: The invention relates to a method for calibrating a vectorial network analyser having n measurement ports and at least 2n measurement locations (n>1) by successive measurement of the reflection and transmission parameters at different two-port calibration standards, which are connected between the measurement ports in any desired order and must all have a transmission path, and three different n-port calibration standards, which are connected between the measurement ports in any desired order and which are not permitted to show transmission and by calculation of error coefficient and scattering matrix [Sx] with the 10-term or 7-term multiport method. An object of the invention is to propagate a method for calibrating these vectorial network analyser used for multiport measurement which permits a calibration with increased precision and considerable reproducibility of measurement.

Abstract: A method and apparatus includes a signal generator, a power supply, a micro-controller, a transmitter and a receiver for determining the condition of a line. The signal is passed through the line and any reflection is used to determine varying characteristics of the line.

Abstract: Briefly, a system that may be used to provide characteristics of a signal propagation medium.

Abstract: The present invention relates to a fast, high precision, interference tolerant impedance measurement apparatus. The apparatus comprises an oscillator circuit having a characteristic frequency determined by the impedance to be measured. The oscillation voltage is converted by one or more high-gain limiting amplifiers to one or more square waves of the same characteristic frequency. The one or more square waves are down-divided by a frequency division circuit to a second square wave, and afterwards transfered to a time-to-digital converter which converts the period of said second square wave signal to a digital state. The digital state is fed to a digital processing unit, which may perform various functions like mapping the digital state to a digital number, filtering, rejection of scatter values, etc. Finally, a number is output from said digital processing unit which gives a measure for the value of the impedance to be measured.

Abstract: An apparatus and a method for detecting high impedance failures in system interconnects. The apparatus and method may measure resistance of a connection of a representative set of pins on a partitioned chip to a circuit board and determine if the measured resistance is within a certain percentage of a good resistance value. The measuring step is executed while the circuit board is operating.

Abstract: An apparatus for measuring output light intensity from laser chips mounted on respective carriers on a fixture, comprises a control unit for moving the fixture to in turn bring the chips to a measurement station, and a TV camera and a NIR camera both connected to a vision system for determining x and y coordinates of objects viewed by the TV camera and the NIR camera, respectively. The control unit is adapted to move the fixture to bring the respective chip in front of the TV camera to determine the coordinates of the chip on the fixture, move the fixture in response to the coordinates of the chip on the fixture to bring the chip in front of the NIR camera to determine the coordinates of a point of maximum light intensity from the ignited chip, and move the fixture in response to the coordinates of the point of maximum light intensity to bring the chip to the measurement station.

Abstract: A single-sided compliant probe is provided that includes a conductive tip shaped as one or more thin conductive fins having one edge which is positioned on a supporting substrate in a manner that allows the opposing edge to engage a contact pad and to move flexibly with respect to the supporting substrate while in close proximity to adjacent probes in an array. The probe tip is oriented in a direction of wipe of the tip across the contact pad but moves substantially vertically in response to the force of a mating contact pad as it is mechanically biased against the tip. Mechanical compliance of the probe allows electrical contact to be made reliably between the probe and its corresponding contact pad on a microelectronic device, where the mechanical compliance accommodates variations in height of the contact pad and wipe improves reliability of electrical engagement.

Abstract: An apparatus that inspects wire breaking of a semiconductor integrated circuit includes a voltage applying device (12), a light pulse source (14), a scanning device (16), an electromagnetic wave detection device (18), and a wire breaking detection device (20). The voltage applying device (12) maintains a semiconductor integrated circuit in a state where a predetermined voltage is being applied thereto. The light pulse source (14) generates an ultrashort light pulse (2). The scanning device (16) two-dimensionally scans and irradiates the two-dimensional circuit of the semiconductor integrated circuit by using the ultrashort light pulse (2). The electromagnetic wave detection device (18) detects an electromagnetic wave (3) radiated from a position irradiated with the ultrashort light pulse on the semiconductor integrated circuit. The wire breaking detection device (20) detects wire breaking of the irradiated position based on presence and absence or intensity of the electromagnetic wave.

Abstract: A system for controlling an axial movement of an article is presented. The system comprises a support stage assembly and a spring suspension arrangement mounted on the support stage assembly. The spring suspension arrangement comprises first and second assemblies arranged in a coaxial relationship one inside the other. The first assembly is attached to the support stage assembly. The second assembly serves for supporting an article-carrying member and is driven for movement along the axis with respect to the first assembly. The outer one of the first and second assemblies is configured to define two spaced-apart parallel planes perpendicular to said axis. The first and second assemblies are attached to each other by first and second membrane-like members arranged in a spaced-apart parallel relationship along said axis.

Abstract: In an environmental test system for controlling a temperature environment of a member to be tested at least from a low temperature environment to a high temperature environment, an air supplying unit supplies low dew point air to an inside of the test chamber. The low dew point air has a dew point temperature lower than a predetermined cooling temperature. The predetermined cooling temperature is defined by the low temperature environment. A temperature changing unit is operative to change a temperature of the low dew point air supplied from the air supplying unit to the inside of the test chamber to control the temperature environment from the low temperature environment to the high temperature environment.

Abstract: A contact probe includes a probe tip and a damper. The probe tip includes a first barrel, a probe pin, and a first spring. The first barrel has a cavity with a bottom, an opening being disposed in a first end of the first barrel and the bottom being disposed at a second end of the first barrel. The probe pin is mounted in the first barrel so as to be movable forward and backward. The first spring is mounted in the cavity for elastically biasing the probe pin towards the opening. The damper is mounted to the second end of the first barrel, and elastically supports the first barrel.

Abstract: A system and method for detecting a defect in a transistor array includes applying a test signal to the array, monitoring pixel voltages along a gate line of the array, and detecting a defect associated with the gate line based on a variation in the pixel voltages along the gate line during the monitoring step. The system and method can also detect a precise location of the defect based on a rate of change in the variation of the pixel voltages along the gate line.

Abstract: The present invention is directed to a system and method of testing an integrated circuit (IC) device for potential latch-up. The system has a power supply configured to supply a maximum voltage to the integrated circuit device. The system uses a current measuring device for measuring current between the power supply and the circuit device. The system includes an overvoltage source that is operative to apply an overvoltage pulse to one input pin that is designated a test pin while the maximum supply voltage is applied to each other input pin of the integrated circuit device. The current measuring device detects whether a latch up condition exists by detecting an increase in current between the power supply and the device based application of the overvoltage pulse.

Abstract: A method of testing an integrated circuit includes applying a voltage to one of the pins of the integrated circuit. The pin is floated for a predetermined time. A measurement is performed after the predetermined time. The measurement involves sampling the RC time constant of leakage current of the pins.

Abstract: A TFT array inspection device inspects a TFT array substrate having thin film transistors arranged in a matrix pattern. The TFT array inspection device includes a probe frame to be electrically connected to the TFT array substrate. The probe frame includes probe pins contacting array inspection electrodes to be connected to a driving electrode terminal provided in a TFT array on the TFT array substrate through wires. The probe pins are positioned at common locations relative to a layout of the TFT array substrate. Since the probe pins are located at common positions, it is possible to use a single common probe frame for the TFT array substrate with a different layout without providing or changing a prove frame corresponding to a different layout of the TFT array substrate.

Abstract: An inspection method includes an array process of forming a TFT array on a substrate to fabricate an active matrix panel, an inspection process of carrying out a performance test on the fabricated active matrix panel, and a cell process of mounting an OLED on the active matrix panel after the inspection process. In the inspection process, variation in parasitic capacitance through a pixel electrode is measured when driving TFTs constituting the active matrix fabricated in the array process are turned on and when the driving TFTs are turned off, and open/short defects in the driving TFTs are thereby inspected.

Abstract: A differential driver circuit that suppresses current overshoot and allows current switching to proceed at near the maximum speed includes: a differential pair Q5 and Q6 having a tail current source I56; a first buffer Q3 providing a first input to the differential pair; a second buffer Q4 providing a second input to the differential pair; a first current absorbing device Q7 coupled to the tail current source I56 and having a control node SP capacitively coupled to the first buffer Q3; and a second current absorbing device Q8 coupled to the tail current source I56 and having a control node SM capacitively coupled to the second buffer Q4.

Abstract: A terminator circuit for use on a pin of an integrated circuit (IC) is disclosed. A preferred embodiment of the present invention includes a clamp circuit that turns on when the voltage at the pin exceeds a threshold value (either an upper or lower bound). Logic and biasing circuitry are used to allow multiple modes of operation by adjusting the threshold values. A particular mode may be selected at any given time so as to strike an appropriate balance between signal quality and power consumption with respect to a particular terminator or set of terminators. This prevents excessive power consumption due to terminator circuitry at inactive or infrequently active IC pins.

Abstract: A digital logic interface circuit makes use of a logic signal representative of a logic signaling level definition, to determine the logic swing amplitude of signals from a given source adopting the same logic signaling level definition. The digital logic interface circuit generates a threshold level from the logic swing amplitude thus determined, and compares digital logic input signals against the threshold level in order to discriminate different logic levels in the digital logic input signals. The comparison result is provided as digital interface output signals adopting a predetermined logic signaling level definition for use by subsequent system sections. Examples of such representative signals are the digital input logic signals themselves, clock signals or line encoded signals. Other examples can be mode control signals or NRZ signals.

Abstract: A pre-diffused high density array of core memory cells is provided in a metal programmable device. The peripheral logic is made up of gate array cells in the metal programmable device. The peripheral logic may be configured to access the core memory cells as various memory types, widths, depths, and other configurations. If the entire memory is not needed, then the unused memory cells can be used as logic gates. The application-specific circuit, including peripheral logic, memory interface logic, and memory configuration is programmed with a metal layer.

Abstract: A voltage level converter device for the conversion of an input signal, which is at a first voltage level, into an output signal, which is at a second voltage level that differs from the first voltage level, where the voltage level converter device has at least one transistor, and in which an additional transistor, controlled by a control signal at a voltage level corresponding to that of the input signal, is provided in a current path that is to be accordingly switched on or off when the output signal switches over for switching that path on or off.

Abstract: A digital electronic circuit having first and second sections. The first section is adapted to transmit one of N input signals. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. The second section is configured to output either an inverse of the signal transmitted by the first section or a logical 0, or to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable.

Abstract: Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.

Abstract: Several local clock buffers are disclosed, each including an input section and an output section. The input sections are substantially identical, and include control logic and gating logic. The control logic produces a gating signal dependent upon multiple control signals and a time-delayed global clock signal. The gating logic produces an intermediate clock signal dependent upon the global clock signal and the gating signal. The output section produces at least one local clock signal dependent upon the intermediate clock signal. In one embodiment, the output section produces a first local clock signal dependent upon the intermediate clock signal and a second local clock signal dependent upon the first local clock signal. In another embodiment, the gating logic produces the intermediate clock signal dependent upon the global clock and gating signals and a feedback signal. The output section produces the feedback signal and one or more local clock signals.

Abstract: A new reversible element with six lines (three input lines and three output lines) and two states are proposed. This element is computationally universal in the sense that a universal Turing machine can be constructed from it. Two reversible elements, each of which has two input lines, two output lines, and two states. These two elements are related to each other in the sense that their functionalities are each other's inverse, so, one of the elements can be obtained from the other by reversing the operations conducted by the other, and interpreting the other's input lines as output lines and the other's output lines as input lines. Together these two elements form a computationally universal set, i.e., a universal Turing machine can be constructed from them.

Abstract: The present invention comprises a circuit consisting of four transistors (101-104) and an optional clamping Zener (107) arranged such that the current drawn through a load (120) is equal to the lesser of an input current (106) and a reference current (105).

Abstract: A configuration of sub-comparators for use within an analog to digital conversion circuit is disclosed. A number of the sub-comparators are adapted to receive equalization and power down control signals. In one embodiment, several of the sub-comparators are cascaded together in the analog to digital conversion circuit. An equalization signal and a power down control signal are applied to at least some of the sub-comparators enabling the sub-comparators to attenuate or eliminate offset voltage and environmental noise associated with the signal to be sampled. Furthermore, in accordance with another aspect, the analog to digital conversion circuit includes a latch type differential sub-comparator, which can attenuate or eliminate output levels of the sub-comparators from residing in an unstable input region of the digital converter.

Abstract: An Ultra-low power voltage detection circuit is implemented in a digital integrated circuit to device to provide a basic timer, programmable timer and programmable low voltage detection (PLVD) using a single connection of the digital integrated circuit device and a passive component(s) external to the digital integrated circuit device. An internal low current source may be enabled so as to discharge an external timing capacitor connected to the output connection, thus eliminating the need for an external resistor. However, timing accuracy may be improved by adding an external discharging resistor and/or charging resistor. The output connection may be configured as a tri-state output and may be driven high to charge and low to discharge the timing capacitor. A voltage reference may be used in determining a voltage trip point for timing and low voltage detection purposes.

Abstract: A clock shaping device is provided that includes: a first clock signal selection portion that receives an input of a reception clock signal and an input of a back-up clock signal from the outside, and selects either of the clock signals; a quartz crystal oscillation circuit that oscillates at a predetermined frequency; a second clock signal selection portion that receives an input of a clock signal from the first clock signal selection portion and an input of a clock signal from the quartz crystal oscillation circuit, and selects either of the clock signals; a voltage controlled oscillation circuit whose frequency varies with a control voltage being supplied and generates and outputs a feedback loop output signal; a phase comparison portion that generates a phase difference signal based on a result of comparing the feedback loop output signal from the voltage controlled oscillation circuit and a clock signal outputted from the second clock signal selection portion; and a loop filter that smoothes the phase di

Abstract: The invention relates to a process for generating a synchronizer pulse, in particular a clock pulse, as well as a synchronizer signal generator device, which is connected to an electronic system, and which emits a synchronizer signal of a particular frequency, which is transferred to at least one device of the electronic system, whereby at least one device is provided with its impedance selected so that a resonance oscillatory circuit—of which the resonance essentially coincides with the frequency of the synchronizer signal—is created for the synchronizer signal generator device.

Abstract: A reproduced signal waveform processing apparatus is provided. The apparatus includes an A/D converter for sampling a reproduced signal at a reproducing clock having a predetermined oscillation frequency; a first equalizer for equalizing a digital reproduced signal from the A/D converter; a second equalizer connected in series with the first equalizer for further equalizing the digital reproduced signal from the first equalizer; a phase frequency controller for detecting a phase frequency error between the digital reproduced signal from the first equalizer and the reproducing clock signal, and outputting a control signal on the basis of a result of the detection; and a variable frequency oscillator for varying the oscillation frequency in accordance with the control signal.

Abstract: Of synchronous circuit cells such as flip-flops, some are of blocked type and others remain unblocked. In a semiconductor integrated circuit according to the present invention, a clock generating circuit is independently provided for each of a plurality of the unblocked synchronous circuit cells for a clock input thereto, in order to control clock skews and achieve a lower power consumption. The clock generating circuit is independently connected to each of a plurality of functional blocks comprising a plurality of the blocked synchronous circuit cells for the clock input thereto.

Abstract: Provided are a delay stage and a delay circuit that are insensitive to an operating voltage and have a constant delay time irrespective of a time interval between input signal pulses. The delay stage includes a first inverter that inverts an input signal, a first capacitor having one end connected to a first voltage node, a first switch that is connected between the other end of the first capacitor and an output terminal of the first inverter and is turned on in response to a control signal, a second inverter that inverts an output signal of the first inverter, a second capacitor having one end connected to a second voltage node, and a second switch that is connected between the other end of the second capacitor and an output terminal of the second inverter and is turned on in response to an inverted signal of the control signal.