Abstract: Disclosed is a novel method and apparatus for acquiring multiple capacitively sensed measurements from a circuit under test. Multiple digital sources are respectively connected to stimulate multiple respective first ends of multiple respective nets of interest. Respective second ends of the multiple respective nets of interest are capacitively sensed. The respective capacitively coupled signals are digitally sampled and shift correlated with respective expected digital signatures. If a high level of correlation is found for a given net, the net is electrically intact; otherwise, the net is characterized by either an open or some other fault that prevents it from meeting specification.

Abstract: Voltage contrast-based apparatuses, methods and systems for detection of continuity are described for use in evaluation of conducting components of a microcircuit such as a silicon wafer-based semiconductor chip. Two beams are directed to two separate conducting, electrically floating components on the sample, and are timed and delivered to be alternating pulses. One lower energy beam elicits its target to emit secondary electrons that are detected by an electron detector to produce an image. A second high-energy beam creates a virtual ground at its target. Voltage contrast images indicate whether there is continuity between the two conducting components.

Abstract: According to the present invention, a method of controlling the burning in of at least one I/C device in a burn in tool is provided. For high power device, the tool has a heat sink positioned to contact each device being burned in, and has a socket for mounting each device to be burned in, and a power source to supply electrical current to burn in each device. The method includes the steps of continuously monitoring at least one process parameter selected from the group of current, voltage, power and temperature, and varying the voltage to maintain at least one of the parameters at or below a given value. Also, a technique for burning in low power devices without a heat sink is provided. The invention also contemplates a tool for performing the above method.

Abstract: Several embodiments of integrated circuit probe card assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates.

Abstract: The invention relates to a test arrangement for testing semiconductor circuit chips, in which a test signal received via a primary test channel from a driver amplifier of an item of test equipment is distributed via parallel sub-channels to a plurality of inputs of one or more semiconductor circuit chips under test the test arrangement having signal buffering circuits arranged in each sub-channel that receive and buffer the test signal from the driver amplifier before feeding it to the inputs of the semiconductor circuit chip(s).

Abstract: A digital toner/locator employs tone packets using a 455 Khz carrier. Plural packet quanta provide multiple test modes which are advantageously selected from a probe without requiring returning to the tone generator to change mode.

Abstract: The object of the present invention is to provide an inspection apparatus for liquid crystal drive substrates that improves the inspection accuracy of liquid crystal drive substrates, judges defect type more accurately, and does not cause a decrease in throughput.

Abstract: Methods and systems consistent with the present invention provide improved online detection of one or more shorts in rotor turns (18) of a field winding (22) of an electric generator. An initial reference inductance LREF is determined by an impedance-measuring circuit (50). A subsequent inductance L is determined by the impedance measuring circuit (50). A data processing system (54) compares LREF to L to determine whether they differ by a predetermined amount. If LREF and L differ by the predetermined amount, an alarm is provided to operators to indicate the presence of one or more shorted rotor turns.

Abstract: A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability.

Abstract: In a transmission signal correction circuit, a first output circuit outputs a data string to outside. A second output circuit for correction is connected in parallel with the first output circuit. The second output circuit receives the data string to add the data string to an output signal of the first output circuit during a period when a control signal is kept generated. A data string detection circuit generates the control signal when detecting a signal sequence, in the data string, that affects a transmission waveform.

Abstract: The invention relates to bus type connection systems, in particular those for wiring backplanes of electronic systems, when the bus comprises connectors distributed in an irregular manner. It consists in selecting segments (D1, D2) over which the intervals (d1, d2) between the connectors are substantially constant. The structure of all the segments except one is then modified to make the effective impedance of the modified segments coincide with that of the unmodified segment. It produces a bus that is fully matched from end to end and able to operate at a very high frequency with a slight reduction of its propagation constant.

Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

Abstract: The present invention is a converter stage for converting a differential logic input signal and a corresponding common mode differential logic signal each having a first single-ended logic signal and a complementary second single-ended logic signal into a single-ended logic output signal. The converter stage comprises a first and a second differential stage each having a first and a second MOS transistor and a first and second current source for the differential stages. According to the invention the current sources are controlled by the voltage level which is centered between the mid-potentials of the common mode level differential logic signal and the mid-potential of the differential logic input signal.

Abstract: An output device for static random access memory is disclosed, which has a precharger, a charge and discharge path circuit, a voltage hold circuit and an output inverter. The precharger connects to a common output node of a plurality of memory cells. When one of the memory cells is to be read, the common output node is precharged to a high potential. The charge and discharge path circuit connects to the common output node and controls an output voltage on its output node in accordance with an internal first grounding path on or not. The voltage hold circuit connects to both the output node of the path circuit and the common output node and controls a voltage of the common output node in accordance with both the output voltage of the path circuit and an internal second grounding path. When the precharger is precharging, the second grounding path is disconnected.

Abstract: An apparatus comprising a low voltage swing (LVS) circuit having a plurality of alternating LVS pre-charging and evaluation phases and a select logic circuit coupled to the LVS circuit and responsive to a plurality of input data signals to generate a plurality of select signals for the LVS circuit. Each of the select signals occurs during one of the LVS evaluation phases and has a turning-on edge and a turning-off edge. The turning-off edge of each of the select signals is generated independent of the input data signals.

Abstract: The power supply-voltage dependency of a current source current is reduced and the power supply voltage is lowered. The invention includes an emitter-coupled logic circuit 118 and a reference-voltage generating circuit 119 for generating a reference voltage VCSC for controlling a drain current (=current source current ICS) of a constant current-supplying n-type MOS transistor 110. The emitter-coupled logic circuit 118 comprises a current switch made up of a pair of emitter-coupled bipolar transistors 106 and 107, a constant current-supplying n-type MOS transistor 110 that is connected in series with the current switch, and resistor means 108 and 109 connected in series with the bipolar transistors 106 and 107 individually for obtaining an output voltage.

Abstract: Provided is an input buffer whose input capacitance presented to input signals can be reduced. The input buffer includes a first differential amplifier which compares the sizes of a first input signal and a second input signal and outputs an output signal as the result of the comparison; a second differential amplifier which compares the sizes of the first input signal and a reference voltage and outputs a second output signal as the result of the comparison; and a third differential amplifier which compares the sizes of the second input signal and the reference voltage and outputs a third output signal as the result of the comparison, wherein the first differential amplifier shares transistors, to which the first and second input signals are input, with the second and third differential amplifiers. The first differential amplifier operates only in a differential operation mode, and the second and third differential amplifiers operate only in a single operation mode.

Abstract: A differential transistor (10, 25) includes a depletion mode transistor (15,30) that has a source connected to a source of an enhancement mode transistor (11,26). The gates of the depletion mode and enhancement mode transistors are driven differentially.

Abstract: An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.

Abstract: In accordance with an aspect of an input/output device for providing fast translation between differential signals from a core of an integrated circuit and higher voltage signals that are external to the core, an I/O buffer includes low voltage devices for receiving core input signals, a cascode stage for setting a bias between the input devices and an output stage, and an output stage including a current mirror for providing a translated external output. Another aspect of the invention further includes a feedback path to cut off the current mirror to prevent static current and a keeper device to maintain an output level after cut off of the current mirror.

Abstract: An integrated circuit device is discussed that includes a data output driver having two modes of operation for driving a data bus. The output driver includes a circuit to produce a full drive output high signal, a partial drive output high signal, a full drive output low signal and a partial drive output low signal. The output driver is protected against negative voltages on the data bus. The output driver is selectable and adaptable to drive terminated loads and unterminated loads.

Abstract: A current compensation circuit for use with a current mirror circuit is disclosed. The current mirror circuit has a current path defined by a first programmable current mirror stage driving a first fanout current mirror stage. The first programmable current mirror stage includes at least one transistor with a channel length exhibiting a first channel length modulation factor ?1. The first fanout current mirror stage connects to a supply voltage source. The current compensation circuit comprises a supply voltage current mirror coupled to the supply voltage source and has a current output coupled to the current path. The compensation circuit further includes a second programmable current mirror coupled in series to the supply voltage current mirror and including at least one transistor with a channel length exhibiting a channel length modulation factor ?2. The second channel length modulation factor ?2 is larger than the first channel length modulation factor ?1.

Abstract: A PLL/DLL circuit is current self-biased responsive to a current Ild provided from a voltage regulator to a VCO or VCDL. Bias current Ibias, which is proportional to Ild, is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from an interconnect coupled to the voltage regulator. In an embodiment of the present invention, a component of the PLL/DLL includes a bias-generating device, such as a MOSFET p-type transistor having a drain coupled to the interconnect. In an embodiment of the present invention, a voltage regulator includes an AMP having a bias-generating device, such as a p-type transistor, acting as a current source, having a source coupled to Vdd and a drain coupled to the interconnect. The gate of the bias-generating device is coupled to the gate of four other p-type devices. Each of the four p-type devices has a source coupled to Vdd. The drains of the first and second p-type transistors are coupled to an output providing Ild.

Abstract: In one embodiment, a PLL circuit is provided with a plurality of pull-in operation modes for pulling a voltage across a filter capacitor (C1, C2) in a lock-up voltage, and with a register (CRG) for designating one of the plurality of pull-in operation modes. The pull-in operation is performed in accordance with a setting value in the register.

Abstract: A charge pump circuit and method for supplying power. The charge pump circuit includes a first circuit receiving at least one low voltage signal and generating an output voltage signal. The charge pump circuit also includes a second circuit receiving a clock signal and the output voltage signal. The second circuit sends a request signal based on a comparison of the output voltage signal with two reference voltage signals, where the two reference voltage signals are derived from two supply voltage signals having a substantially constant potential difference. The charge pump circuit further includes a high voltage generator receiving the request signal and sending the two supply voltage signals to the first circuit and the second circuit. The high voltage generator adjusts the voltage potentials of the two supply voltage signals such that the voltage potential of the output voltage signal falls between the voltage potentials of the two reference voltage signals.

Abstract: A current compensation circuit for use with a current mirror is disclosed. The current mirror circuit has a current path defined by a first current mirror stage driving a second current mirror stage, the second current mirror stage is coupled to a supply voltage source. The current compensation circuit comprises an impedance divider coupled to the supply voltage and an output node. The impedance divider operates to generate a compensation signal at the node representative of voltage changes in the supply voltage source. The compensation circuit further includes a gain stage having an input coupled to the output node and a current output connected to the current path. The gain stage operates to generate a compensation current for application to the current path in response to the compensation signal.

Abstract: A local bias generator generates forward body bias that tracks variations in a supply voltage of a functional block containing one or more circuits having field-effect transistors. The bias is generated using a single-stage source-follower formed from a pair of matched transistors. In operation, the transistors convert a first bias signal into a second bias signal based on a difference between the supply voltage and a reference voltage. The first bias signal and reference voltage may be generated by a central bias generator.

Abstract: A control circuit receives inputs from first and second field effect sensors. The control circuit produces a control output only if the second field effect sensor senses proximity or touch more than a predetermined time after the first field effect sensor senses proximity or touch.

Abstract: A pulse duty cycle automatic correction device has a pulse width detector for detecting the high, low level pulse widths of the input cycle pulse so as to generate high, low level signals; a comparator encoder for comparing the high, low level signals, calculating out a correction delay time, and generating a correction delay signal and an output selection signal; a delay circuit for generating a delay cycle pulse; a compensation circuit for compensating the input cycle pulse so as to generate an input compensation pulse; a logic circuit for generating two cycle pulses according to the delay cycle pulse and the input compensation pulse; and a multiplexer for receiving the two cycle pulses and the input cycle pulse, and generating the output cycle pulse with duty cycle of 50% according to the output selection signal.

Abstract: A timing-flexible flip-flop element with at least one extra delayed output signal. The timing-flexible flip-flop element includes a flip-flop logic circuit for generating a standard output signal and a delay cell for receiving the standard output signal to generate a delayed output signal. Because the timing-flexible flip-flop element of the invention has at least one extra delayed output signal, the delayed output signal for the flip-flop may be selected for the path that needs longer hold time. Therefore, it is unnecessary to insert any delay cell to the path with insufficient hold time. The timing-flexible flip-flop element can be implemented in the cell-based synthesis design flow.

Abstract: A clock shrink circuit has an inverting first matching stage which is responsive to an input clock signal to generate a first inverted signal having a first matching delay. The first matching delay is a difference between a first rise and a first fall propagation time of the first matching stage. An inverting first pull-up stage is coupled to the first matching stage and is responsive to the first inverted signal to generate a second inverted signal having a first pull-up delay which is substantially reduced by the first matching delay. The first pull-up delay is a difference between a second rise and a second fall propagation time of the first pull-up stage.

Abstract: A method and apparatus for accommodating delay variations among multiple signals are provided. According to one embodiment of the invention, transitions of one or more of a plurality of lines between different levels are detected. The timing of a signal affecting recovery of information from the plurality of lines is adjusted according to the transitions detected. Examples of such a signal include one or more signals carried on one or more of the plurality of lines and a timing signal carried on a line separate from the plurality of lines.

Abstract: A clock input circuit includes a switch circuit, a switching circuit, and a programmable register to provide switching control based on the level of a power supply voltage of a microcomputer. When the power supply voltage of the microcomputer is equal to or higher than a predetermined value, general noise removal is conducted through two Schmitt trigger circuit and a capacitor. When the power supply voltage of the microcomputer is lower than the predetermined value, noise removal is conducted through a Schmitt trigger circuit, and two flip-flops. Thus, noise removal of high accuracy can be realized, independent of the power supply voltage of the microcomputer.

Abstract: A first switch element selectively connects a first node being connected to a capacitor to a second node according to a first control signal. A precharge circuit is connected to the first node for precharging the first node to a precharge voltage for a predetermined time period when the switched capacitor circuit is switched off. The precharge circuit includes a second switch element for selectively connecting a third node to the first node according to a second control signal; a precharge switch element for selectively connecting the precharge voltage to the third node according to the first control signal; and a delay unit for delaying the first control signal to generate the second control signal. In this way, the clock feedthrough effect is minimized and the capacitance of a varactor formed by the first switch element in the off-state is stabilized during the VCO locking period.

Abstract: Hot swappable pulse width modulation power supply circuits preferably realized in integrated circuit form. The hot swap circuits provide for de-bouncing, controlled charging of the input capacitor of the power supply circuit and soft-start of the pulse width modulator after charging the input capacitor. Other features include a low voltage lockout, and an output for coupling to a synchronous rectifier driver to synchronize synchronous rectifiers on the secondary side of a coupling transformer in isolated systems. The hot swap capability may be disabled through an enable pin, or not implemented by not connecting the integrated circuit in a manner to use the hot swap capability.

Abstract: A switched capacitor circuit includes a positive side capacitor coupled to a first positive side node; a first positive side switch element for selectively coupling the first positive side node to a second node according to a first control signal; and precharge circuit coupled to the first positive side node for precharging the first positive side node to a precharge voltage for a predetermined time when the first positive side switch element is switched off according to the first control signal, and then for charging the first positive side node to a charge voltage until the first positive side switch element is switched on according to the first control signal. By rapidly precharging the first positive side node, the clock feedthrough effect is eliminated and the locking period of the VCO is shortened. Afterwards by charging the first positive side node, the phase noise of the VCO is minimized.

Abstract: A first voltage conversion circuit converts first and second reference input voltages into first and second differential output voltage. A second voltage conversion circuit converts the first reference input voltage and a control input voltage into a third differential output voltage. The third differential output voltage is inputted to an exponential conversion element. The first and second differential output voltages are inputted to an active impedance bridge. The active impedance bridge outputs a gain control voltage of the first and second voltage conversion circuits. A balanced condition of the active impedance bridge determines the exponential conversion characteristic of the output current to the control input voltage of the exponential conversion element.

Abstract: A protected dual purpose power/enter switch for an integrated receiver/decoder has a first relay and a second relay adapted for operative communication with a motherboard and with each other. A switch and a processor are in operative communication with the first relay. When the device is off, said switch is configured to activate the first and second relay to power up the device, and when said device is on, the first relay connects the switch to the processor as an enter switch. The switch may power off said device by entering a power off menu item displayed by said processor.

Abstract: A technique for simplifying the control of a switch is presented. In one embodiment, a method of controlling a switch as a function of the voltage across the switch is presented. In one embodiment a method of controlling a switch as a function of the slope of the voltage across the switch is present. In one embodiment a switching is switched on for an on time period that is substantially fixed in response to a voltage across the switch while the switch is off. In one embodiment a switch is switched on for an on time period that is substantially fixed in response to the slope of the voltage across the switch while the switch is off.

Abstract: A high-speed, low-noise charge pump for use in a phase-locked loop. The charge pump is constituted by first and second cascode current mirrors, as well as first and second switching transistors. The first cascode current mirror includes a first output mirror transistor and a first output cascode transistor. The first switching transistor is interposed between the first output mirror and the first output cascode transistors. During assertion of a first control signal, the first switching transistor is turned on so a first mirror current can flow through an output node. Likewise, the second cascode current mirror includes a second output mirror transistor and a second output cascode transistor. The second switching transistor is interposed between the second output mirror and the second output cascode transistors. During assertion of a second control signal, the second switching transistor is turned on so the second mirror current can flow through the output node.

Abstract: A biasing circuit comprising a first switching device having a control terminal, and first and second switching terminals. The first switching terminal being connected to a supply voltage, the second switching terminal being connected through a first resistive element to ground, and the control terminal being supplied by a reference voltage which is determined depending on the mode of operation of the circuit. The circuit further comprising a first branch connected between the control terminal and ground comprising a second resistive element in series with a second switching device. The second switching device forming part of a first current mirror having a second branch for effecting a generated bias value. During a normal mode of operation the reference voltage is dependant on the generated bias value, whereas during a standby mode of operation the reference voltage is connected to a low potential.

Abstract: The present invention provides a voltage regulator capable of causing a large output current to flow during a heavy load operation, and of making a leakage current from output transistors small during a light load operation. The voltage regulator includes a plurality of output transistors and a circuit for changing connection of the output transistors to allow a W/L value of the output transistor to be changed. Moreover, the voltage regulator further includes an output current detection circuit for detecting an output current, and a circuit for changing connection of the output transistors based on the output current to allow a W/L value of the output transistors to be changed based on the output current.

Abstract: The present invention provides a current mirror circuit of which consistency (ratio) of the input current and output current is more improved. This current mirror circuit comprises input side and output side bi-polar transistors of which bases are commonly connected, an input side MOS transistor of which source is connected to a collector of the input side bi-polar transistor and of which drain and gate are connected to the input terminal, output side MOS transistors of which source is connected to the collectors of the output side bi-polar transistors, of which drain is connected to the output terminals, and of which gate is connected to the gate of the input side MOS transistor, and an MOS transistor for supplying base current of which source is connected to the bases of the input side and output side bi-polar transistors, and of which gate is connected to the gate of the input side MOS transistor.

Abstract: A filter circuit has an input terminal which is input with a first current, and which is coupled with a first node, capacitor, of which one terminal is coupled with the first node, of which the other tmrminal is coupled with a second node, and which integrates lhe first current and outputs voltage, a transconductance means, of which one terminal is coupled with the first node, of which another terminal is coupled Nith the second node, of which the other terminal is coupled with a third node, and which outputs a second current being proportional to the voltage to the third node and an output terminal which is coupled with the first node, and which outputs the voltage.

Abstract: A low pass filter includes a differential amplifier including a positive input end, a negative input end, a positive output end, and a negative output end. A first resistive device is coupled between the negative input end and a first node. A second resistive device is coupled between the positive input end and the first node. A third resistive device substantially the same as the second resistive device is coupled between the negative input end and a second node. A fourth resistive device substantially the same as the first resistive device is coupled between the positive input end and the second node. A first capacitive device is coupled between the negative input end and the positive output end. Finally, a second capacitive device substantially the same as the first capacitive device is coupled between the positive input end and the negative output end.

Abstract: An apparatus for continuous phase quadrature amplitude modulation and demodulation to continuously process phases and amplitudes at symbol change points in an M-ary quadrature amplitude modulation method.

Abstract: Feedback for self-calibration of any parameter in an analog and/or digital system is described wherein a system quality factor can be represented by a voltage or current differential. The preferred embodiment is operative to alternately supply two or more optimally equivalent currents or voltages from such a system, detect amplitude and/or phase feedback of resultant output signal at the frequency of the alternation, and use feedback to modify a calibration value, voltage, or current so as to minimize or maximize the feedback, thus effecting self-calibration of the system. Such a method and attendant apparatus enables system self-calibration without need of any high-precision or high-cost components.

Abstract: Apparatus and methods for driving multiple output stages with a single switching amplification modulator reduce system cost and complexity. The technique also addresses applications wherein one or more of several output stages of potentially differing output powers are desired at one time. That is, the switching drivers and loads can be the same or different.

Abstract: A bypass switch topology for a low-noise amplifier is provided. In one aspect of the invention, an amplifier includes at least one signal amplifying transistor, coupled between an input terminal and an output terminal associated with the amplifier, for amplifying a received input signal. The amplifier also includes a bypass switch, coupled to the at least one signal amplifying transistor, for providing a gain (e.g., high-gain) mode operation and a bypass mode operation, the bypass switch including two transistors. In the gain mode operation, the two transistors of the bypass switch are off and the at least one signal amplifying transistor amplifies the received input signal and passes the amplified signal to the output terminal. In the bypass mode operation, the two transistors of the bypass switch are on, the at least one signal amplifying transistor is turned off, and the received input signal is passed directly from the input terminal to the output terminal.

Abstract: There is provided a signal amplifier capable of restraining the influence of an EMI caused by a distortion of a waveform of an output signal.