Abstract: A luminaire including a light source mounted on a base having a plug-in style connector attached to the internal wires of the luminaire for supplying AC power to the light source. The connector is adapted to mate with a plug-in style connector connected to wires of a J-box. The luminaire may include a second connector for connecting to a conditional actuation device. If the conditional actuation device is not used, a continuous actuation device may be connected to the luminaire. A method of installing a luminaire includes connecting an electrical connector to the wires for connection to a J-box, connecting the luminaire connector to the electrical connector, and mounting the luminaire onto the J-box. A method of selling includes providing a choice from among different style luminaires, providing a choice from among different actuation devices to connect with the selected luminaire, and optionally selling the selected luminaire and actuation device.

Abstract: A high conversion efficiency inverter circuit by providing the current-mode resonant type efficient in using a power source.

Abstract: A power supply, including a step-up converter, a resonant converter, and control unit. The step-up converter is connected to the resonant converter; the step-up converter and the resonant converter are each connected to the primary control unit.

Abstract: A power supply device includes two input ports, two output ports, a transformer having primary and secondary windings, switching means, and a controller. The switching means includes a switching element connected in series with the primary winding, and a capacitor. The controller switches the switching element to energize the transformer and charge the capacitor. When an AC power failure such as instantaneous interruption occurs, energy stored in the capacitor is discharged to flow through the primary winding. Accordingly, the transformer is energized to maintain generating an output power from the power supply device for a certain time period. The capacitor is provided on a primary side of the transformer, generally higher voltage side, in the power supply device, so that a smaller capacitance of the capacitor can be used.

Abstract: A DC converter has a transformer with loosely coupled primary and secondary windings, a main switch connected in series with the primary winding of the transformer, and a series circuit connected to ends of one of the primary winding and main switch. The series circuit includes a clamp capacitor and an auxiliary switch. The main and auxiliary switches are alternately turned on/off so that a voltage of the secondary winding of the transformer is synchronously rectified with synchronous rectifiers and is smoothed with smoothing elements, to provide a DC output. The DC converter also includes a tertiary winding tightly coupled with the primary winding of the transformer, a voltage source to supply a voltage lower than a voltage generated by the tertiary winding of the transformer, and clamp diodes to clamp the voltage generated by the tertiary winding with the use of the voltage source. The clamp diodes provide voltage-clamped signals to drive the synchronous rectifiers.

Abstract: A charge pump DC/DC converter circuit of the present invention includes: a monitor circuit that detects a potential difference between terminals of a semiconductor switch that turns on during a first period, so as to output a determining signal corresponding to the potential difference; and each of drive circuits that outputs a drive signal to a semiconductor switch that turns on during a first period, in response to the determining signal. The drive signal increases the on-resistance of the semiconductor switch in proportion to the detected potential difference.

Abstract: A device and method of enhancing the reliability and performance of integrated circuits, e.g., complementary metal-oxide semiconductor integrated circuits (“IC”) is described. The device is an IC (e.g., digital, analog, and mixed-signal circuits) comprising a digital voltage control system (“VCS”) having a temperature-adaptive digital DC-to-DC voltage converter. In one embodiment, the DC-to-DC converter comprises a delay-line-based temperature sensing circuit that continuously monitors temperature changes, and adjusts the frequency and process speed of the IC to compensate for any performance degradation caused by thermal effects by adjusting the voltage supplied to the IC (i.e., Vout) to increase or decrease the frequency and process speed of the IC in proportion to any abnormal temperature changes in the IC.

Abstract: An inverter type AC generator includes an inverter circuit converting a DC output into AC output of a predetermined frequency and supplying the AC output to a load via a load line in order to improve the quality of an AC output waveform at least in parallel operations. The inverter AC generator includes a zero-crossing detection circuit for detecting a timing of zero-crossings of an AC output voltage waveform on the output line. A controller generates a drive signal in synchronization with the timing of the detected zero-crossings, when a predetermined number of zero-crossings have been detected, and drives the inverter to perform a synchronized operation process.

Abstract: A pattern matching system includes, in part, a multitude of databases each configured to store and supply compressed data for matching to the received data. The system divides each data stream into a multitude of segments and optionally computes a data pattern from the data stream prior to the division into a multitude of segments. Segments of the data pattern are used to define an address for one or more memory tables. The memory tables are read such that the outputs of one or more memory tables are used to define the address of another memory table. If during any matching cycle, the data retrieved from any of the successively accessed memory tables include an identifier related to any or all previously accessed memory tables, a matched state is detected. A matched state contains information related to the memory location at which the match occurs as well as information related to the matched pattern, such as the match location in the input data stream.

Abstract: Control clocks of different phases are distributed to a memory array divided into multiple banks, and processing of entries and search keys (read and write operations and search operation) is performed at different phases. The memory array divided into banks is further divided into smaller arrays, that is, sub-arrays, and a sense amplifier in a read-write-search circuit block is shared by the two sub-arrays. In this case, a so-called open bit line structure in which each one bit line is connected from both sub-arrays to a sense amplifier is adopted. The same look-up table is registered to multiple banks, successively inputted search keys are sequentially inputted to the multiple banks, and the search operation is carried out in synchronization with the control clocks of different phases.

Abstract: A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A semiconductor integrated circuit device includes a storage element, program circuit, and sensing circuit. The storage element stores information by electrically irreversibly changing the element characteristics. The program circuit programs the storage element by electrically irreversibly changing its element characteristics. The sensing circuit senses the irreversibly changed element characteristics of the storage element in distinction from an unchanged state. The program circuit includes a high-voltage generator which irreversibly changes the element characteristics of the storage element by applying a high voltage to it, and a current source which supplies an electric current to the storage element having element characteristics changed by the high-voltage generator, thereby stabilizing the element characteristics.

Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus. a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Abstract: A magnetoresistive effect element according to the present invention is comprised of a TMR element that is disposed at an intersection where a bit line and a write word line intersect with each other, in a manner sandwiched between the bit line and the write word line, and is configured such that it includes a sensitive magnetic layer whose magnetization direction is changed by a synthetic magnetic field of magnetic fields generated around the bit line and the write word line, and at the same time such that electric current flows in a direction perpendicular to the laminating surfaces thereof, and a magnetic material individually covering the bit line and the write word line at the intersection, thereby forming an annular magnetic layer associated with the bit line and an annular magnetic layer associated with the write word line. The sensitive magnetic layer comprises a magnetic material portion of the annular magnetic layers of the magnetic material, sandwiched by the bit line and the write word line.

Abstract: The invention considers a non-volatile semiconductor memory device comprising a first and second floating gate transistor, which are coupled in series. Each floating gate transistor comprises a floating gate. Programming means coupled to the first and second floating gate transistor are operable to place a selected electrical charge in one of the floating gates and less than the selected electrical charge in the other floating gate to represent either a first or second binary value.

Abstract: A non-volatile memory (NVM) array is made of NVM cells that have a floating gate transistor and a select transistor in which the floating gate transistor requires only a single layer of polysilicon. Adjacent cells are arranged so that the floating gates are staggered rather than being in the same line. This results in being able to put the cells closer together because of the reduction of the significance of what is commonly called poly-to-poly spacing. In this case, the termination of one floating gate is not lined-up with the floating gate of the adjacent NVM cell in the same row. Adjacent memory cells in the same column are made to have different configurations from each other which results in the floating gates in adjacent columns not being aligned, thus avoiding the poly-to-poly spacing limitation.

Abstract: An integrated semiconductor memory device includes memory cells each with a selection transistor and a storage capacitor. Memory cells of this type are usually read by the potential of the bit line to which the memory cell is connected being compared in a sense amplifier with the potential of a complementary, second bit line and a voltage difference identified being amplified. The semiconductor memory according to the invention provides for that capacitor electrode which is not connected to the selection transistor to be connected to the complementary, second bit line. As a result, for an operating voltage with the same magnitude, larger quantities of charge can be stored in the storage capacitor since now the two mutually spread potentials output by the sense amplifier are used for biasing the storage capacitor.

Abstract: The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the highest threshold voltage. The remaining cells on the wordline are programmed to their respective logical states in order of decreasing threshold voltage levels.

Abstract: An electro-optical device includes first and second substrates that are bonded to each other, the first substrate having an extended portion extended from the second substrate on a first side thereof in plan view, a plurality of pixel units that are disposed in a pixel region on the first substrate and individually have pixel electrodes, a data line driving circuit that is disposed along the first side in a peripheral region around the pixel region so as to supply an image signal to the pixel units, a plurality of external circuit connecting terminals that are arranged along the first side in a region of the peripheral region on the extended portion, an image signal line that is relayed around the data line driving circuit from the plurality of external circuit connecting terminals and has a first wiring line portion wired in a direction along the first side between the data line driving circuit and the pixel region, and a sealant that bonds the first and second substrates to each other in a sealing region ar

Abstract: A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.

Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

Abstract: In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage in allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate.

Abstract: A memory cell structure includes non-volatile as well as SRAM memory cells that share the same bitline and operate differentially. The SRAM cell includes first and second MOS transistors that are coupled to the same true and complementary bit lines that the non-volatile memory cells are coupled to. The non-volatile memory cells are erased prior to being programmed. Programming of the non-volatile memory cells may be carried out via hot-electron injection or Fowler-Nordheim tunneling. Data stored in the non-volatile memory cells may be transferred to the SRAM cell. The differential reading and writing of data reduces over-erase of the non-volatile devices.

Abstract: The nonvolatile memory device includes a semiconductor substrate on which a source, a drain, and a channel region are formed, a tunneling oxide film formed on the channel region, a floating gate formed of a transition metal oxide (TMO) on the tunneling oxide, a blocking oxide film formed on the floating gate, a gate electrode formed on the blocking oxide film.

Abstract: The programming method of the present invention minimizes program disturb in a non-volatile memory device by initially programming a lower page of a memory block. The upper page of the memory block is then programmed.

Abstract: The location of a cell to be erase verified is determined. The erase verification threshold voltage is then set. The threshold voltage is changed in response to the cell's location with respect to array ground. A cell in the middle of a row of cells between array grounds is verified to a lower voltage than a cell that is closer to an array ground.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to erase the non-volatile memory cells and perform erase verification operations. The memory can be arranged in numerous erasable blocks and/or sub-blocks. An erase register stores data indicating an erase state of corresponding memory sub-blocks. During erase verification, the memory programs the erase register when a non-erased memory cell is located in a corresponding sub-block. Additional erase pulses can be selectively applied to sub-blocks based upon the erase register data. Likewise, erase verification operations can be selectively performed on sub-blocks based upon the erase register data. An address register is provided to store an address of a non-erased memory cell identified during verification. The address from the register is used as a start address for subsequent verification operations on the same array location.

Abstract: A method, computer program product, and apparatus for obtaining the geometric correspondence between at least two 3D range data sets obtained using a 3D rangefinder device. First and second 3D range data sets are provided. The first 3D range data set is displayed as a 2D displayed image. The second 3D range data set is displayed as one of a second 2D displayed image and a 3D displayed image. Corresponding features within the first 2D displayed image and within the second displayed image are respectively specified. A 3D transformation between the first 3D range data set and the second 3D range data set is computed based on the geometry of the specified corresponding features. As such, that the geometric correspondence between the two 3D range data sets may be determined.

Abstract: Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.

Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

Abstract: A memory control device for writing to a memory data input via a port section and for reading from the memory data output via the port section includes setting means for setting, in accordance with a transfer speed of first input data input via the port section, a write-enable time for enabling writing of the first input data for each predetermined period and for setting, in accordance with a transfer speed of first output data output via the port section, a read-enable time for enabling reading of the first output data for the predetermined period; and write/read control means for controlling data writing/reading to/from the memory such that second input data input via the port section is written or second output data output via the port section is read within a time other than the write-enable and read-enable times within the predetermined period.

Abstract: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance is disclosed. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, a methodology according to the present disclosure allows selective activation and deactivation of tuning transistors in the ODT and non-ODT legs. During a default operational state of the electronic device (e.g., when no data read operation is taking place), the tuning transistors in the non-ODT legs may be maintained “turned off” or “disabled” to reduce DQ pin capacitance contributed by these tuning transistors had they been active during this default state. These non-ODT leg tuning transistors may be turned on, for example, when a data read operation is to be performed. Similarly, the tuning transistors in the ODT legs also may be selectively enabled/disabled to further control or reduce DQ pin capacitance as desired.

Abstract: The invention relates to a hub module for connecting one or more memory chips, said module having an address input for connection to an address bus in order to receive an address of the memory area to be addressed and having an address output for connection to a further address bus, and having an address decoder unit in order to address one of the connected memory chips using an address that is applied to the address input or to apply the applied address to the address output, characterized in that the address decoder unit has a redundancy unit in order to address a redundant memory area instead of the addressed memory area in the event of a defect being detected in a memory area of the one or more connected memory chips.

Abstract: A device and method for programming the semiconductor device that includes a plurality of first fuse-sets which store first information, wherein each of the first fuse-sets includes at least one first fuse element and the first information has been compressed, a second fuse-set including at least one second fuse element which stores data modification information used to modify the first information and an information creation circuit which modifies the first information based on the data modification information, expands the modified first information and thereby creates second information.

Abstract: Upon designing a standard cell type semiconductor chip, there are prepared a plurality of types of standard cells and a plurality of types of yield improvement standard cells having the same function as the standard cells and having a layout which is changed to improve yield. A priority order list to be used upon replacing the plurality of types of first standard cells is generated. Automatic placement is performed by using the plurality of types of first standard cells. A certain type of a first standard cell is selected from the plurality of types of first standard cells according to a priority order in the generated list. The selected type of a first standard cell is replaced with a corresponding type of a second standard cell.

Abstract: A disk drive unit for a disk, e.g. for use in a mobile device, comprises a spindle (1) positioned within the disk drive unit and adapted to support the disk rotatably in an operating position. An electric motor (2) is operatively coupled to the spindle (1) to rotate it. An auxiliary electric motor (3) is connectable to the spindle to accelerate the spindle during start-up. This auxiliary motor can be selected to work efficiently at zero speed. The electric motor may be a low-power motor, resulting in a reduced power consumption.

Abstract: Memory interface methods and apparatus for processing source synchronous data from a memory device (DRAM). The methods and apparatus synchronously transfer data from the memory device to a memory controller even though the time variability of read return strobe signals is greater than one clock cycle.

Abstract: A multi-memory chip and data transfer method are capable of directly transferring data between internal memory devices. The multi-memory chip of the present invention includes a first memory device, a second memory device, and a data transmission bus that is shared by the memory devices. Furthermore, the second memory device includes a mode register set for setting an internal transfer mode. In accordance with the data transfer method according to the present invention, the transfer of data between the memory devices included in the multi-memory chip is performed through the data transmission bus shared by the memory devices. Accordingly, the multi-memory chip and the data transfer method can considerably improve data transfer rates between devices, as compared to conventional approaches in which data are transferred the DMA controller of an external system.

Abstract: A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed.

Abstract: A contactless memory architecture has a column of bidirectional multi-bit memory cells between each adjacent pair of diffused lines in a bank. The architecture includes about half as many metal lines as diffused lines, and bank select cells at both ends of the bank. Most bank select cells connect respective metal lines to respective pairs of diffused lines. For a memory access, metal lines on one side of a selected bidirectional memory cell are biased to a first voltage, and metal lines on the other side of the selected bidirectional memory cell are biased to a second voltage. The first voltage is made higher than the second voltage to select one of the storage locations in the selected cell, and the second voltage is made higher than the first voltage to select the other of the storage locations in the selected cell.

Abstract: A method for identifying memory bit cells and connections. The method includes defining a bit pattern for each bit cell node in a bit cell; defining a node pattern for each node in a circuit block; and matching the node patterns with the bit patterns, wherein bit cells and corresponding bit line connections and word line connections in the circuit block are determined based on matches found during the matching.

Abstract: The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.

Abstract: Methods and apparatus that determine, at a device (e.g., a DRAM device), a phase difference between two externally supplied timing signals such as a clock signal (CLK) and a data strobe signal (DQS) are provided. Adjustments may be made to timing of one of the signals itself or other internal memory signals that are, perhaps, utilized in circuits controlled by the DQS signal.

Abstract: An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a predetermined frequency. The operation clock controller includes a clock buffer for buffering an external clock to output an internal clock; a unit delaying set for sequentially delaying the internal clock to output a plurality of delayed clocks; a phase detecting block for detecting logic levels of the delayed clocks at a rising edge of the internal clock to output phase detecting signals; a sampling pulse generator for outputting a sampling signal generated at a predetermined point of the internal clock; a latching block for outputting a phase detection latch signal by sampling and latching the phase detection signal at a point of the sampling signal being inputted; and a frequency detection block for outputting the frequency detection signal by logically combining the phase detection latch signal.

Abstract: We describe a semiconductor memory device having a precharge control circuit and an associated method for precharging the same. A semiconductor memory device having a series of circuits for writing data to memory cells includes an input and output line for transferring data to be written to each of the memory cells. A precharge control circuit is adapted to generate a precharge control signal for controlling a precharge disable state of the input and output line after application of a first write command. The disable state of the precharge control signal is maintained even after application of a second write command when performing a continuous write operation responsive to the second write command application without other commands applied subsequent to the first write command application. Avoiding precharging the input and output line in a continuous write operation, reduces current consumption.

Abstract: A method for the continuous phase conversion of a product in a kneader mixer, into which the product is introduced, said mixer comprising kneading elements that are mounted on at least one shaft. The product is back-mixed until a predefined viscosity of the product is determined by measurement of the torque of the shaft, or a product with a predetermined viscosity that has already been achieved is back-mixed, the kneader mixer is then switched to a continuous mode, in which optionally and additional component is added and the product is subsequently transported to the discharge point.

Abstract: An experimental mixing device may comprise a driving source, an eccentric member, a control member and a mixing member. The control member may be selective installed in the experimental mixing device and be configured to adjust the mixing member, thereby providing various operational motions of the mixing member, for example an orbital motion, a see-saw motion, a 3-D twist motion, or a crank motion. The use of the control member may eliminate the need of separating the mixing member from the experimental mixing device. Thereby, the experimental mixing device may have adjustable patterns and quantity of the mixing motion and lead to easy usage and manufacture.

Abstract: A homogenization device comprising a flow-through channel having at least two local constrictions of flow wherein the size of a first local constrictions is adjustable thereby permitting variable flow rate through one portion of the device and the size of a second local constriction is fixed thereby permitting constant flow rate through another portion of the device.

Abstract: A device for providing a visual indication of the amount of liquid or other materials in a blender cup or other receptacle is provided. The device is mounted on the rotatable impeller shaft in the base of the cup, and preferably is employed to affix the impeller to the shaft. Graduations formed as part of or provided on the device at appropriate locations provide a visual indication of the amount of ingredients introduced.