Patents Issued in February 6, 2007
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Patent number: 7173831Abstract: In one embodiment, an apparatus includes a transformer having a primary winding and a secondary winding and a switching circuit to facilitate a periodic application of an input voltage to the primary winding. The switching circuit includes an active switch and a capacitor commonly coupled to the primary winding. In one embodiment, the apparatus further includes a synchronous rectification circuit coupled to the secondary winding to generate a rectified signal, an output filter coupled to the synchronous rectification circuit to provide an output voltage in response to the rectified signal, and a control circuit coupled to the output filter to receive the output voltage and coupled in a switching control relationship with the active switch and the synchronous rectification circuit.Type: GrantFiled: September 23, 2005Date of Patent: February 6, 2007Assignee: Intel CorporationInventor: Viktor D. Vogman
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Patent number: 7173832Abstract: The present invention relates to a multifunction power convertor in the field of power transmission. The multifunction power convertor consists of a rectifier circuit, a filter circuit connecting with the rectifier circuit, an inverter circuit connecting with the filter circuit, and differential mode voltage suppression reactors (LS1, LS2, LS3) and filter capacitor group that connect in series with the output lines (U, V, W) of the inverter circuit respectively. The characteristic of the present invention is that a closed magnetic ring is provided on the output lines (U, V, W) between the differential mode voltage suppression reactors and the filter capacitor group, and the output lines (U, V, W) wind in parallel on the closed magnetic ring.Type: GrantFiled: April 8, 2003Date of Patent: February 6, 2007Inventor: Jialin Wu
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Patent number: 7173833Abstract: A power supply device and an operating method thereof are provided. The power supply device includes a main converter and an auxiliary converter. The main converter includes a power factor corrector (PFC), a first capacitor that connects in parallel with the PFC and a DC/DC converter that connects in parallel with the first capacitor. The auxiliary converter is connected in parallel to the main converter. When the power supply device operates in a normal mode, the main converter and the auxiliary converter together provide a first output to an output load. When the power supply device is in a standby mode, the DC/DC converter is turned off so that only the auxiliary converter provides a second output to the output load. Meanwhile, the PFC is in operation to maintain the voltage of the first capacitor in order to meet the demand of the output dynamic response of the main converter.Type: GrantFiled: April 29, 2005Date of Patent: February 6, 2007Assignee: Delta Electronics, Inc.Inventors: Kun-Chi Lin, Youjun Zhang, Qinggang Kong, Junshan Lou, Hongjian Gan
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Patent number: 7173834Abstract: A half-controlled silicon control rectifying system and method thereof are provided. In this case, the first detection unit detects the zero cross phase of the triphase AC in input port thereof. The second detection unit detects the voltage of the DC bus. Then the control unit controls the silicon-controlled rectifying unit by software. Therefore, the efficiency of soft actuation is achieved.Type: GrantFiled: April 11, 2005Date of Patent: February 6, 2007Assignee: Delta Electronics, Inc.Inventors: Chui-Min Tai, Cheng-Te Chen
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Patent number: 7173835Abstract: A circuit for synchronous rectifying is provided for forward power converter. A secondary winding of a transformer includes a first terminal and a second terminal for generating a switching voltage. A saturable inductor is coupled from the second terminal to a third terminal for providing a delay time. A first transistor is coupled from the first terminal to a ground terminal. A second transistor is connected from the third terminal to the ground terminal. The first and second transistors operate as synchronous rectifiers. An inductor is equipped from the third terminal to an output terminal of the forward power converter. Furthermore, a current-sensing device generates a current signal in response to an inductor current of the inductor. A control circuit receives the switching voltage and the current signal for generating a plurality of signals for driving a plurality of transistors, respectively.Type: GrantFiled: November 16, 2005Date of Patent: February 6, 2007Assignee: System General Corp.Inventor: Ta-yung Yang
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Patent number: 7173836Abstract: A circuit making use of a push/pull-type control chip to drive a half bridge-type inverter circuit connects a drive circuit to a conventional half bridge-type inverter circuit, and has a push/pull-type control chip having two output terminals, a drive circuit having two input terminals and two output terminals, and a half bridge-type switch assembly having two electronic switches. The two input terminals of the drive circuit are connected with the two output terminals of the push/pull-type control chip and controlled by the push/pull-type control chip. Each of the two electronic switches of the half bridge-type switch assembly has a control terminal, which is connected to one of the two output terminals of the drive circuit and driven by the drive circuit for converting a DC power source into an AC power source sent to the primary side of a transformer.Type: GrantFiled: September 8, 2004Date of Patent: February 6, 2007Assignee: Lien Chang Electronic Enterprise Co., Ltd.Inventors: Chun-Kong Chan, Jeng-Shong Wang
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Patent number: 7173837Abstract: A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).Type: GrantFiled: August 31, 2004Date of Patent: February 6, 2007Assignee: Netlogic Microsystems, Inc.Inventors: Roger Bettman, Eric H. Voelkel
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Patent number: 7173838Abstract: In accordance with the regions which are component elements of memory information (entry) and input information (comparison information or search key), quaternary information including a pair of the minimum value and the difference or ternary information including a pair of the data and the mask are used as I/O signals. In addition, in accordance with the two types of information, two types of encoding circuits and decoding circuits are disposed, and either one of the encoding circuits and the decoding circuits are activated in accordance with the values set to the registers disposed to designate the format of information in each region of the entry and the search key. By selecting the desired register from the plurality of registers in response to the external command signals and address signals, the encoding and decoding in accordance with the information to be processed are carried out.Type: GrantFiled: March 7, 2005Date of Patent: February 6, 2007Assignee: Hitachi, Ltd.Inventors: Satoru Hanzawa, Tomonori Sekiguchi, Riichiro Takemura
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Patent number: 7173839Abstract: Disclosed are an apparatus and a method that at-speed-test a data cache included in a semiconductor integrated circuit by means of an on-chip memory having a size smaller than that of the data cache. A data cache has a first data storage area. An on-chip memory has a second data storage area smaller than the first data storage area, and stores test data. A address decoder decodes addresses so that the first data storage area is mapped to the second data storage area when an access for the test data stored in the on-chip memory is required.Type: GrantFiled: March 31, 2005Date of Patent: February 6, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Young-Sik Kim
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Patent number: 7173840Abstract: In order to program a memory module, some of its inputs are stimulated via internal memory locations of a so-called boundary scan (BSCAN) register that is provided in the form of an IC or ASIC. In order to activate or deactivate a write operation, the control signal input of the memory module, said control signal input being responsible for generating a WRITE_ENABLE signal, is controlled exclusively. The switching over of the WRITE_ENABLE signal from “LOW” to “HIGH” potential and vice versa thus ensues according to two JTAG instructions of an instruction sequence that provides for the generation of a LOW or HIGH level at the setting signal input or resetting signal input of an update flip-flop of the memory location responsible for generating the WRITE_ENABLE signal.Type: GrantFiled: September 3, 2003Date of Patent: February 6, 2007Assignee: Siemens AktiengesellschaftInventors: Karlheinz Krause, Elke Tiemeyer
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Patent number: 7173841Abstract: A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.Type: GrantFiled: December 3, 2004Date of Patent: February 6, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Ching Peng, Shyue-Shyn Lin, Wei-Ming Chen
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Patent number: 7173842Abstract: An embodiment of the invention provides an on-chip heating system to both initially anneal and revive cycle-fatigued polymer ferroelectric materials utilized in memory devices. By heating the polymer ferroelectric material above its Curie temperature, the polymer ferroelectric material can crystallize as it cools. As such, the ferroelectric properties of the polymer are enhanced and/or restored.Type: GrantFiled: March 31, 2004Date of Patent: February 6, 2007Assignee: Intel CorporationInventors: Mark S. Isenberger, Hitesh Windlass, Wayne K. Ford, Carlton E Hanna
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Patent number: 7173843Abstract: A nonvolatile memory device features a serial diode cell as a cross-point cell using a nonvolatile ferroelectric capacitor and a serial diode chain. The serial diode cell comprises a ferroelectric capacitor and a serial diode switch. The ferroelectric capacitor, located where a word line and a bit line are crossed, stores values of logic data. The serial diode switch is connected between the ferroelectric capacitor and the bit line and selectively switched depending on voltages applied to the word line. The nonvolatile memory device using a serial diode cell comprises a plurality of serial diode cell arrays, a plurality of word line driving units and a plurality of sense amplifiers. Each of the plurality of serial diode cell arrays each includes a single serial diode cell where a word line and a bit line are crossed. The plurality of word line driving units selectively drive the word line. The plurality of sense amplifiers sense and amplify data transmitted through the bit line.Type: GrantFiled: June 28, 2004Date of Patent: February 6, 2007Assignee: Hynix Semiconductor Inc.Inventor: Hee Bok Kang
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Patent number: 7173844Abstract: A reference voltage generating device that provides a constant reference voltage even with temperature change in a ferroelectric random access memory and a method for driving the same are provided. A device for generating a reference voltage in a ferroelectric random access memory including memory cells, each of which has one ferroelectric capacitor and one access transistor, includes a reference cell composed of a ferroelectric capacitor and a transistor; a reference plate line connected to one end of the ferroelectric capacitor constituting the reference cell; and a reference plate line driver circuit for adjusting a voltage level of a reference plate line enable signal depending on temperature change so that a constant reference voltage is generated.Type: GrantFiled: August 4, 2005Date of Patent: February 6, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Han-Joo Lee, Kang-Woon Lee, Byung-Jun Min, Byung-Gil Jeon
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Patent number: 7173845Abstract: A memory cell includes first and second p-channel transistors and first and second n-channel transistors in a cross-coupled latch configuration. Power control circuitry associated with the memory cell is coupled to selectively perform voltage transitions on the source terminals of one or more of the n-channel and/or p-channel transistors in the memory cell during a data corruption mode of operation to destroy data stored in the latch and set the memory cell to a known state. In one implementation, the power control circuitry is coupled to the source terminal of one of the n-channel transistors to transition that terminal from a low voltage reference level (present during a normal mode of operation) to a high voltage reference level and back to the low voltage reference level. In another implementation, the power control circuitry is coupled to the source terminal of one of the n-channel transistors and the source terminal of at least one of the p-channel transistors.Type: GrantFiled: February 27, 2004Date of Patent: February 6, 2007Assignee: STMicroelectronics, Inc.Inventor: Thomas Allyn Coker
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Patent number: 7173846Abstract: A new magnetic RAM cell device is achieved. The device comprisese, first, a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A reading switch is coupled between the free layer and a reading line. A writing switch is coupled between a first end of the pinned layer and a first writing line. A second end of the pinned layer is coupled to a second writing line. Architectures using MRAM cells are disclosed.Type: GrantFiled: February 13, 2003Date of Patent: February 6, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Denny D. Tang, Yu Der Chih
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Patent number: 7173847Abstract: A horizontally disposed elliptical or rectangular magnetic memory cell includes at least two conductive lines to carry current and a magnetic element disposed between the conductive lines. The current through the conductive lines induces a magnetic field, such that the magntic element is directly accessible. The magnetic memory cell can be sensed with a GMR head.Type: GrantFiled: November 4, 2003Date of Patent: February 6, 2007Assignee: MagSil CorporationInventor: Krish Mani
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Patent number: 7173848Abstract: A magnetic random access memory (MRAM) has memory units or stacks of multiple memory cells arranged in the X-Y plane on the MRAM substrate with each memory unit having four possible magnetic states. Each memory unit is located at an intersection region between two orthogonal write lines and has two stacked memory cells. The two cells are magnetically separated from each other by a separation layer and have the easy axes of magnetization of their free ferromagnetic layers aligned substantially orthogonal to one another. The application of write-current pulses of equal magnitude and the appropriate direction through the orthogonal write lines above and below the memory units can generate each of the four magnetic states which can be detected as four independent logical states.Type: GrantFiled: February 1, 2005Date of Patent: February 6, 2007Assignee: Meglabs, Inc.Inventor: Kochan Ju
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Patent number: 7173849Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.Type: GrantFiled: August 4, 2005Date of Patent: February 6, 2007Assignee: Macronix International Co., Ltd.Inventors: Tso-Hung Fan, Chih-Chieh Yeh, Tao-Cheng Lu
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Patent number: 7173850Abstract: A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.Type: GrantFiled: August 30, 2004Date of Patent: February 6, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Koji Sakui, Junichi Miyamoto
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Patent number: 7173851Abstract: A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.Type: GrantFiled: October 18, 2005Date of Patent: February 6, 2007Assignee: Kilopass Technology, Inc.Inventors: John M. Callahan, Hemanshu T. Vernenker, Michael D. Fliesler, Glen Arnold Rosendale, Harry Shengwen Luan, Zhongshang Liu
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Patent number: 7173852Abstract: In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase. Data is rewritten when severe errors are found during read operations. Portions of data are corrected and copied within the time limit for read operation. Corrected portions are written to dedicated blocks.Type: GrantFiled: October 18, 2005Date of Patent: February 6, 2007Assignee: SanDisk CorporationInventors: Sergey Anatolievich Gorobets, Reuven Elhamias, Carlos J. Gonzalez, Kevin M. Conley
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Patent number: 7173853Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.Type: GrantFiled: May 23, 2006Date of Patent: February 6, 2007Assignee: Renesas Technology Corp.Inventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume, Katsutaka Kimura
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Patent number: 7173854Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.Type: GrantFiled: April 1, 2005Date of Patent: February 6, 2007Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Siu Lung Chan
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Patent number: 7173855Abstract: Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.Type: GrantFiled: August 31, 2004Date of Patent: February 6, 2007Assignee: Micron Technology, Inc.Inventors: Stephen R. Porter, Scott J. Derner
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Patent number: 7173856Abstract: The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a bias voltage to the feedback transistor in response to a reference voltage on the biasing transistor. A cascode-connected transistor is coupled to the feedback transistor and the biasing transistor. This transistor provides a stable bias voltage to the biasing transistor. An output latch circuit is coupled to the bitline for providing a latched output of the memory cell's data.Type: GrantFiled: August 5, 2004Date of Patent: February 6, 2007Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Giovanni Santin, Michele Incarnati
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Patent number: 7173857Abstract: At the time of an operation of writing data to a specific memory cell in a memory block, a semiconductor memory device applies a write voltage for a predetermined period and, after that, performs a verifying operation by using a sense amplifier circuit and a comparator. When it is found as a result of the verifying operation that writing to the memory cell is insufficient, the writing operation is performed again by an instruction of a memory control circuit. At this time, the memory control circuit adjusts a write voltage.Type: GrantFiled: January 25, 2005Date of Patent: February 6, 2007Assignee: Renesas Technology Corp.Inventors: Hiroshi Kato, Yasuhiko Taito, Tsukasa Ooishi, Jun Ohtani
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Patent number: 7173858Abstract: The nonvolatile memory according to the present invention can precisely read information included in a memory transistor subject to a shift phenomenon because electrical read is performed on the memory transistor by using a reference voltage generated from a refresh memory transistor. Further, according to the present invention, the period of time during which the refresh operation is performed can be longer than before, which improves the reliability of information stored in the memory transistor. Furthermore, the margin between distributions of threshold voltages can be reduced, which improves the scale of integration of the multilevel nonvolatile memory.Type: GrantFiled: August 12, 2005Date of Patent: February 6, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kiyoshi Kato
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Patent number: 7173859Abstract: A program voltage signal implemented as a series of increasing program voltage pulses is applied to a set of non-volatile storage elements. Different increment values can be used when programming memory cells to different memory states. A smaller increment value can be used when programming memory cells to lower threshold voltage memory states and a larger increment value used when programming memory cells to higher threshold voltage memory states such as the highest memory state in an implementation. When non-volatile storage elements of a set are programmed to different memory states under simultaneous application of a single program voltage signal, programming can be monitored to determine when lower state programming is complete. The increment value can then be increased to complete programming to the highest memory state.Type: GrantFiled: April 5, 2005Date of Patent: February 6, 2007Assignee: Sandisk CorporationInventor: Gerrit Jan Hemink
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Patent number: 7173860Abstract: Non-volatile memory such as flash EEPROM has memory cells that may be programmed in parallel using a self-limiting programming technique. Individual cells have charge storage units that may be charged by hot electrons in a self-limiting manner. As the charge storage unit reaches the required level of charge, hot electrons are no longer generated, or are generated in reduced number. The level of charge at which hot electron generation stops is determined by the voltage applied to the cell. Thus, several cells may be programmed in parallel, each self-limiting at a charge level corresponding to the voltage applied.Type: GrantFiled: August 9, 2005Date of Patent: February 6, 2007Assignee: SanDisk CorporationInventor: Raul-Adrian Cernea
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Patent number: 7173861Abstract: According to some embodiments, a nonvolatile semiconductor memory device includes high voltage circuits that prevent high voltages, which are applied to bitlines during an erase operation, from being applied to low voltage circuits that are operable with low voltages. Each high voltage circuit includes a first switching circuit for selectively isolating the low voltage circuit from the bitlines, and a second switching circuit for inhibiting a leakage current to the low voltage circuit from the bitlines. The second switching circuit is connected between the first switching circuit and the low voltage circuit.Type: GrantFiled: October 28, 2004Date of Patent: February 6, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul Cho, Yeong-Taek Lee
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Patent number: 7173862Abstract: After execution of sub-block erase (S2) for partly erasing a memory cell block, sub-block erase verify read is executed (S4). As a result of the sub-block erase verify read, if the sub-block erase is completed, then terminate the sub-block erase (S5). If otherwise the sub-block erase is not completed yet, then perform over-program verify read (S6) to thereby determine whether the cause of an event that a sub-block erase-verify result becomes “Fail” due to the deficiency of erase or the presence of an over-programmed cell or cells. If the result of such over-program verify read is “Pass,” then repeat execution of the sub-block erase verify read (S2). When the over-program verify read (S6) is “Fail,” output a Fail result and then complete the operation (S8).Type: GrantFiled: May 27, 2005Date of Patent: February 6, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Takuya Futatsuyama, Kenichi Imamiya, Koji Hosono, Noboru Shibata
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Patent number: 7173863Abstract: A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.Type: GrantFiled: March 8, 2004Date of Patent: February 6, 2007Assignee: SanDisk CorporationInventors: Kevin M. Conley, Reuven Elhamias
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Patent number: 7173864Abstract: There is provided a data latch circuit that comprises a first buffer for buffering an input data signal in synchronization with an input strobe signal, a first latch unit for conducting a switching operation in response to the strobe signal and latching an output signal from the first buffer for a preset time, a second buffer for buffering an output signal from the first latch unit in synchronization with the strobe signal, and a second latch unit for performing a switching operation in response to the strobe signal and latching an output signal from the second buffer. Further, the present invention provides a semiconductor device using the data latch circuit.Type: GrantFiled: May 17, 2005Date of Patent: February 6, 2007Assignee: Hynix Semiconductor Inc.Inventor: Geun-Il Lee
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Patent number: 7173865Abstract: Systems and methods for stacked die memory depth expansion. In accordance with a first embodiment of the present invention, a circuit comprises a first memory input enabling depth expansion in a memory. The circuit further comprises a second memory input enabling address range selection in a memory and a plurality of address inputs accessing an expanded memory depth. The circuit also comprises one or more external chip enable inputs and a decoding logic coupled to the first memory input, second memory input, plurality of address inputs and the external chip enable input, wherein the decoding logic generates an internal chip enable signal and a stacked die select signal.Type: GrantFiled: November 22, 2004Date of Patent: February 6, 2007Assignee: Cypress Semiconductor CorporationInventors: George M. Ansel, Scott A. Jackson
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Patent number: 7173866Abstract: The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.Type: GrantFiled: June 29, 2004Date of Patent: February 6, 2007Assignee: Hynix Semiconductor Inc.Inventors: Kwang Jin Na, Young Bae Choi
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Patent number: 7173867Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can include selectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.Type: GrantFiled: April 15, 2004Date of Patent: February 6, 2007Assignee: Broadcom CorporationInventor: Esin Terzioglu
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Patent number: 7173868Abstract: A SENSE AMPLIFIER OF FERROELECTRIC MEMORY DEVICE features improvement of the amplification degree. The SENSE AMPLIFIER OF FERROELECTRIC MEMORY DEVICE comprises a MBL sensing unit, a voltage dropping unit, a coupling regulation unit, a pull-down regulation unit, a sensing load unit, and an amplification unit. The level of the sensed voltage is double regulated, thereby improving the amplification degree on low voltage sensing data, and a small sensing voltage of a main bit line can be embodied, thereby embodying a lower voltage memory.Type: GrantFiled: February 15, 2005Date of Patent: February 6, 2007Assignee: Hynix Semiconductor Inc.Inventor: Hee Bok Kang
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Patent number: 7173869Abstract: The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first voltage level using a voltage regulator, determining that a second voltage level is desired and initializing the voltage regulator to provide the second voltage level based on determining that the second voltage level is desired.Type: GrantFiled: August 13, 2004Date of Patent: February 6, 2007Assignee: Micron Technology, Inc.Inventors: Theodore T. Pekny, Stephen J. Gualandri
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Patent number: 7173870Abstract: Disclosed is a memory device, which combines a self-refresh enable signal and a power mode decision signal and prevents an internal voltage from being dropped down without the increase of IDD3P current when the memory device performs a self-refresh operation. The memory device includes an operation mode internal voltage generator used in an operation mode, and a controller for enabling the operation mode internal voltage generator while performing a self-refresh operation with a predetermined period and activating a memory cell array of the memory device, even when the memory device is in a stand-by mode.Type: GrantFiled: April 12, 2005Date of Patent: February 6, 2007Assignee: Hynix Semiconductor Inc.Inventor: Eun Suk Lee
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Patent number: 7173871Abstract: A semiconductor memory device is disclosed. The device comprises at least one data input/output reference signal input and output pin and a plurality of integrated circuits, each with a data input/output reference signal input and output pad connected to the data input/output reference signal input and output pin. Each integrated circuit further comprises a data input/output reference signal input and output buffer for buffering a data input/output reference signal input from the data input/output reference signal input and output pad when data is input. This buffer also buffers an internally generated data input/output reference signal, and outputs the buffered signal when data is output. The internally generated data input/output reference signal output can be disabled on each integrated circuit in response to a control signal, thus allowing a single one of the plurality of integrated circuits to be selected to generate the reference signal.Type: GrantFiled: March 19, 2003Date of Patent: February 6, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Youp Kong, Jun-Young Jeon, Jae-Hyeong Lee
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Patent number: 7173872Abstract: The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.Type: GrantFiled: January 5, 2006Date of Patent: February 6, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-Sun Park, Hyung-Dong Kim, Sang-Seok Kang, Jong-Hyun Choi, Yong-Hwan Jung
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Patent number: 7173873Abstract: A device and a method for breaking the leakage current path, wherein the leakage current is caused by a defect in a memory cell of a memory array, are provided. The device includes a column selection line, a row selection line, a switch device coupled to the column selection line, the row selection line, a power supply terminal and a memory cell. When a column turn-off signal is coupled to the column selection line and a row turn-off signal is coupled to the row selection line, the switch device is turned off and thus a power from the power supply terminal can not be coupled to the memory cell. When at least one of the column selection line and the row selection line does not receive the turn-off signal, the switch device is not turned off and the power can be coupled to the memory cell.Type: GrantFiled: November 20, 2003Date of Patent: February 6, 2007Assignee: Winbond Electronics Corp.Inventor: Cheng-Sheng Lee
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Patent number: 7173874Abstract: A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.Type: GrantFiled: August 9, 2005Date of Patent: February 6, 2007Assignee: Micron Technology, Inc.Inventors: Alistair Gratrex, Graham Kirsch
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Patent number: 7173875Abstract: A CMOS static random access memory (SRAM) cell array, an integrated chip including the array and a method of accessing cells in the array with improved cell stability. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability.Type: GrantFiled: September 27, 2004Date of Patent: February 6, 2007Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Rajiv V. Joshi, Donald W. Plass
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Patent number: 7173876Abstract: A semiconductor integrated circuit is provided, using a one-port memory cell, capable of smoothly performing a data write/read operation in accordance with an instruction from a CPU and a data read operation to display an image on a display panel. The semiconductor integrated circuit includes a memory cell having a port through which data is input to and output from a set of bit lines, a write/read circuit connected with the port via the set of bit lines, a read circuit connected with the port via the set of bit lines, a CPU-system control circuit that controls the write/read circuit so that a data write or read operation based on a write request or read request from a CPU is performed for a first period, and a display-system control circuit that controls the read circuit so that data to be supplied to a display panel is read for a second period which does not overlap the first period.Type: GrantFiled: March 11, 2004Date of Patent: February 6, 2007Assignee: Seiko Epson CorporationInventor: Zenzo Oda
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Patent number: 7173877Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.Type: GrantFiled: September 30, 2004Date of Patent: February 6, 2007Assignee: Infineon Technologies AGInventors: Hermann Ruckerbauer, Christian Sichert, Dominique Savignac, Peter Gregorius, Paul Wallner
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Patent number: 7173878Abstract: Disclosed is an apparatus for driving output signals of a DLL circuit. The apparatus includes a first driving part and a second driving part for receiving output signals of the DLL circuit, wherein the DLL circuit is employed for a synchronous memory device, an output signal of the first driving part controls a data output driver of the synchronous memory device, and an output signal of the second driving part controls an ODT circuit of the synchronous memory device.Type: GrantFiled: April 21, 2005Date of Patent: February 6, 2007Assignee: Hynix Semiconductor Inc.Inventor: Kyoung Nam Kim
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Patent number: 7173879Abstract: A processing technique to apply high resolution, non-Fourier based beamformers to practical active sonar system implementations.Type: GrantFiled: June 8, 2004Date of Patent: February 6, 2007Assignee: Farsounder, Inc.Inventors: Matthew Jason Zimmerman, James Henry Miller
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Patent number: 7173880Abstract: Arrangement with an acoustic array with a sound velocity meter, suitable to be arranged under water. The acoustic array is able to receive acoustic signals from an underwater device and to provide acoustic array output data to a processing arrangement such that the processing arrangement can perform in real-time, a calculation of a position of the underwater device relative to the acoustic array based on the acoustic array output data. The sound velocity meter is able to measure velocity of sound in fluid layers just below a vessel floating on the water and to provide sound velocity meter output data to the processing arrangement such that the processing arrangement can correct the calculation of the position of the underwater device based on the sound velocity meter output data in real-time.Type: GrantFiled: June 25, 2004Date of Patent: February 6, 2007Assignee: Think!Global B.V.Inventor: Francois Bernard