Abstract: A first circuit is disposed on the semiconductor substrate, operates synchronously with a first clock signal, and outputs a first output signal delayed by a first delay time from the first clock signal. A first measuring circuit measures indirectly a first increase and a first decrease of the first delay time. A setting circuit operates synchronously with the first clock signal, outputs a second clock signal delayed from the first clock signal by a second delay time adding the first increase and subtracting the first decrease. A second circuit inputs the first output signal and operates synchronously with the second clock signal.

Abstract: An output of a first data register is coupled to an input of a second data register. The same periodic clock signal clocks both data registers. A controller monitors the clock signal, a first load signal and a read signal. The controller generates a guard band signal using the clock signal and the first load signal. The controller also generates a second guard band signal from the read signal and the clock signal. A second load signal, that is used to load the second data register, is created by performing a logical AND operation on the two guard band signals.

Abstract: A two-dimensional parity method and system for rotating parity information in a disk array, such as a RAID, to provide multiple disk fault tolerance with reduced write bottlenecks, is presented. The method includes forming a plurality of blocks, each block comprising a plurality of stripes extending across multiple disks, reserving at least one stripe in each block for parity, dividing each block into a plurality of chunks, wherein at least one of the chunks in the block comprises parity information, and shifting the position of each parity chunk in each block to a different disk with respect to the parity chunk in adjacent blocks. The method further includes shifting the position of each parity strip in the at least one stripe in each block to a different disk with respect to the parity chunk in adjacent blocks. A system for translating information in a disk array includes an array controller configured to shift parity chunks and parity strips.

Abstract: A writable-once optical recording medium such as a BD-WO, and a method and apparatus for managing the writable-once optical recording medium, are provided. The recording medium includes at least one recording layer having at least one temporary defect management area and at least one final defect management area. The method includes recording temporary defect management information in the temporary defect management area of the recording medium, the temporary defect management information including disc usage management information indicating a recording use status of the recording medium; and transferring, at a transfer stage, the temporary defect management information from the temporary defect management area to the final defect management area of the recording medium.

Abstract: A method of recovery from a data storage system failure in a data storage system having a host computer writing data to a first storage unit with a first storage controller synchronously mirroring the data to a second storage unit, and with a second storage controller asynchronously mirroring the data to a third storage unit. The method begins with the detection of a failure associated with the first storage unit. Upon detection of the error or failure associated with the first storage unit, the synchronous data mirroring relationship between the first storage unit and the second storage unit is terminated and the host is directed to write data updates directly to the second storage unit. Upon correction of the failure associated with the first storage unit, the asynchronous mirroring of data updates from the second storage unit to the third storage unit is suspended and synchronous mirroring of the data updates in a reverse direction, from the second storage unit to the first storage unit, is commenced.

Abstract: The present invention provides a novel system and method for failover. In an embodiment, a primary server and a backup server are available to a plurality of clients. Messages containing requests are processed by the primary server, while a mirror image of transaction records generated by the processing of those requests is maintained in volatile memory of both the primary server and the backup server. In this mode of operation, the volatile memory is periodically flushed to non-volatile memory.

Abstract: A method and circuit for repairing a memory array having one or more memory segments each having one spare column and a predetermined number of spare rows common to all segments, the method comprises, while testing the memory array for failures, generating an equal number of unique segment repair solutions for each segment with each segment repair solution including one defective column address, if any, and a number of defective row addresses, if any, corresponding to the predetermined number of spare rows; and, after completing testing, analyzing all segment repair solution combinations consisting of one segment repair solution selected from each segment; and identifying the best segment repair solution combination of combinations having a number of different defective row addresses which is less than or equal to the predetermined number of spare rows.

Abstract: A method of verifying a monitoring and responsive infrastructure of a system is provided and described. The method includes setting a sensor to a simulation mode. Further, a test value is provided to simulate a real value outputted by the sensor. While in the simulation mode, the test value instead of the real value is sent to the monitoring and responsive infrastructure to invoke a response. Moreover, the response to the test value is verified. In an embodiment, the monitoring and responsive infrastructure is compliant with an Intelligent Platform Management Interface specification.

Abstract: An apparatus and method for testing a computer system by utilizing a Field Programmable Gate Array (FPGA) and programmable memory modules is provided. The apparatus includes a controller, a plurality of programmable memory modules, and an FPGA. Each programmable memory module stores configuration data of peripheral devices of the computer system in corresponding versions, respectively, which are differentiated according to functions of the computer system. Each memory module stores configuration data about a PCI host controller, a memory controller, a PLL, an interrupt controller, an arbiter, a UART, or a timer. The FPGA is programmed according to data stored in one memory module selected from among the programmable memory modules. Therefore, in the apparatus, the FPGA does not contain a bus bridge circuit, so that the FPGA has an increased programmable area and can be easily connected even with peripheral devices requiring many input and output ports.

Abstract: An integrated circuit (“IC”) comprising a plurality of logic modules. The IC further comprises a plurality of bus segments each associated with one of the logic modules; a debug bus interconnecting the bus segments in a ring; and a debug port connected to the debug bus for accessing debug data on the debug bus. Each bus segment takes in data from the logic module associated therewith and outputs the data to the debug bus to be forwarded to the next bus segment along the ring.

Abstract: A computer program product is provided that is readable by a computing system and encoding a computer program of instructions. The computer program product includes a hardware protected region that is utilized to store a portion of a computer BIOS. The BIOS includes a compressed computer program for restoring at least a portion of the computer BIOS when uncompressed and executed. The computer program product also includes a non-hardware protected region that is utilized to store the remainder of the computer BIOS. The hardware protected region may include an uncompressed computer program that may be utilized to uncompress the compressed program. The hardware protected region may also include an uncompressed program for detecting and initializing one or more memory devices within the computer system. Methods and apparatus are also provided for creating and utilizing the contents of the computer program product.

Abstract: A log acquisition method is provided that allows a processing log of software to readily be acquired and reduces the man-hours needed for analyzing a bug. The log acquisition method is a method for acquiring a runtime log of a program 91 including a function (FuncAA), comprising the step of changing the address of the function (FuncAA) loaded to the address of a function (92) for log acquisition, wherein the function (92) for log acquisition comprises the steps of: calling the function (FuncAA) (96) to cause a predetermined process to be executed (97), receiving the result of the execution (98), and passing said result to said program 91 (101), recording given information when calling the address of the function (FuncAA) (95, 100), and recording given information when receiving the result of the execution (99, 100).

Abstract: A protecting route design method is disclosed for a communication network including a plurality of nodes having preset information on a protecting route to switch over in parallel from a working route thereto when link or node failure occurs, according to a failure notification message including failure location information being transmitted from a failure detection node to each node. The protecting route design method includes the steps of searching a protecting route which can minimize a transfer time of the failure notification message from the failure detection node; and then, updating the searched protecting route to a protecting route having a spare communication capacity sharable for a different failure and having a route switchover time to be completed within a given time limit.

Abstract: An error correction coding apparatus includes a parity check matrix generation unit which generates a parity check matrix having a number of elements having a value of 1 in each row thereof, having a predetermined number of elements having a value of 1 in each column thereof, and having the other elements having a value of 0; a parity check matrix adjustment unit which receives the parity check matrix from the parity check matrix generation unit, searches the parity check matrix for a cycle forming group of four elements positioned at respective vertexes of a rectangle and having a value of 1, and when there is at least one cycle forming group, replaces the value of 1 of at least one element of the cycle forming group with the value 0 of another element, to output a adjusted parity check matrix without a cycle forming group therein; and an LDPC coding unit which receives the adjusted parity check matrix from the parity check matrix adjustment unit and receives an m-bit message word to perform LDPC coding.

Abstract: An integrated circuit comprising a processor and memory, the memory storing a set of data representing program code and/or an operating value, wherein each bit of the data is stored as a bit/inverse-bit pair in corresponding pairs of physically adjacent bit cells in the memory.

Abstract: Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.

Abstract: In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.

Abstract: A scan test circuit includes a scan flip-flop that receives a reset signal, a data signal, a scan data signal, and a scan shift enable signal selecting either the data signal or the scan data signal. A reset control circuit controls the reset signal according to the scan shift enable signal. Even if the reset signal originates in a combinatorial circuit, the reset control circuit can prevent the flip-flop from being reset during a scan shift sequence, without the need for external control of the reset signal. Further control of the reset signal can be provided by a mask circuit. These reset control features enable improved fault coverage to be obtained with a reduced number of external input terminals, a reduced number of test patterns, and only a small amount of additional test circuitry.

Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).

Abstract: A semiconductor apparatus comprises a processor having an instruction register inside thereof, a pseudorandom number generating device activated in response to a test operation and generating pseudorandom numbers, an input switchover device for switching over between data input in normal operation and input of the pseudorandom numbers from the pseudorandom number generating device in the test operation to thereby output the data or pseudorandom numbers to the instruction register. The pseudorandom numbers generated in the pseudorandom number generating device are inputted to the instruction register via the input switchover device so that the random instructions are implemented and a random test is implemented with an activation rate equivalent to the same in the normal operation.

Abstract: A semiconductor LSI circuit provided with a scan circuit includes: to-be-tested combinational logic circuits; scan circuits adjacent to and disposed alternately with the combinational logic circuits; scan elements, which form the scan circuits; a first selector inserted in a first scan circuit scan and connects a first group of scan elements and a second group of scan elements; a second selector inserted in a second scan circuits and connects a third group of scan elements and a fourth group of scan elements; a first route provided in the first group of scan elements and extending from a scanning output terminal of a scan element; and a second route provided in a third group of scan elements and extending from the scanning output terminal of a scan element. The first selector selects either the first route or the second route.

Abstract: The test circuit tests a test target circuit and outputs a test result to a tester. The test circuit includes a first clock generator, a second clock generator, a test target circuit, a BIST circuit for performing the test, and a tester synchronous circuit. The BIST circuit repeats the test the number of times determined by the first clock and the second clock. The tester synchronous circuit selects a test result so as to output all the test results from the BIST circuit and outputs the selected test result.

Abstract: An alignment module receives a sequence of un-aligned data words, finds a frame alignment word, and aligns the data words based on the position of the frame alignment word in the un-aligned data words. Comparators compare segments of two consecutive un-aligned data words to a frame alignment word and generate a first logic signal when there is a match. A shift register and a counter are used to determine which comparator generates the first logic signal. The counter sends a count to a barrel shifter, which shifts the un-aligned data words according to the count to generate aligned data words.

Abstract: A circuit configuration for testing a circuit using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve comparing actual data that are output by the circuit under test with prescribed nominal data in the test device. A combinational logic device for logically combining the sequentially output test results is provided such that result data indicate fault free operation of the circuit under test only if the actual data which are output match the prescribed nominal data in all of the sequentially performed test procedures. The result data is output via an addressing and control unit in the circuit under test.

Abstract: Hitless Switching provides a method of delivering data to a remote point in a reliable fashion. However, no guarantee or acknowledgement is provided that data has been written to a remote storage device. This is problematic for remote data mirroring. Apparatus and methods are provided to guarantee that data arriving at a remote terminal is correctly stored. Interaction with hitless switching and remote optical mirroring systems are described.

Abstract: An RLP (Radio Link Protocol) frame receiving method transmits an RLP frame entirely and quickly in consideration of a radio environment in a mobile communication system. The method discriminates an error frame from the received RLP frame, measures a degree of loss of the received RLP frame and compares the measured degree of loss with a reference value when the error frame is detected. XID parameters (Exchange Identification Parameters) set during an initial stage of reception are varied on the basis of a comparison result and retransmission is then requested of the RLP frame corresponding to the error frame on the basis of the varied XID parameters.

Abstract: A method for determining r error detection bits of a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix. The parity control matrix includes at least two consecutive complementary columns. The present invention also relates to a method for determining a syndrome, as well as a coding and decoding circuit.

Abstract: A method of embedding an additional layer of error correction into an error correcting code, where information is encoded into code words that are arranged in columns of a code block. The method includes reducing the length of each row of the code block by adding row symbols together according to a predetermined adding rule resulting in a reduced code block; encoding the shortened rows of the reduced code block using a horizontal error correcting code to obtain horizontal parities; and embedding the horizontal parities as additional layer in the error correcting code.

Abstract: An apparatus comprises a check bit encoder circuit and a check/correct circuit. The apparatus operates on encoded data blocks, wherein each encoded data block includes a data block, a first plurality of check bits, and a second plurality of check bits. The encoded data block is logically arranged as an array of R rows and N columns, and each of the N columns comprises data bits from a respective one of the plurality of components. The first check bits form a first column of the array, and each of the first check bits covers a row of the array. The second check bits form a second column of the array and are defined to cover bits in the array according to a plurality of check vectors. Each check vector corresponds to a different bit in the array and is an element of a Galois Field (GF(2R)). The check vectors are derived from a plurality of unique elements of GF(2R), each of which corresponds to a different column of the array.

Abstract: A base model matrix is defined for the largest code length of each code rate. The set of shifts {p(i,j)} in the base model matrix are used to determine the shift sizes for all other code lengths of the same code rate. Shift sizes {p(f,i,j)} for a code size corresponding to expansion factor zf are derived from {p(i,j)} by scaling p(i,j) proportionally, and a model matrix defined by {p(f,i,j)} is used to determine the parity-check bits for the f-th code.

Abstract: An error-correction coding method and an error-correction decoding method utilize error detection and error correction for an audio signal when a video signal and the audio signal are multiplexed and transmitted by a DVI. After an error correction code is added to each sample (sample data unit) of the digital audio signal, n continuous (n: integer equal to or larger than 2) pieces of the samples (sample data units) of the digital audio signal, to which error correction codes are added, are interleaved to generate a coded audio signal.

Abstract: In order to reproduce data in a stable manner by correction of random and burst errors of a wide range without lowering a transfer speed, C2 error correction for correcting an inter-sector error is carried out in addition to the conventional C1 error correction for correcting an error generated in a sector. The configuration of an error correction unit (or an ECC block) including C1 and C2 codes is formed as a track. That is to say, one track is used as the base of an ECC block unit. In this way, two ECC block units never exist in the same track.

Abstract: Flexibly configurable layer one transport channels produce radio blocks in response to communication information and extract communication information from radio blocks. Each transport channel can include an encoder or a decoder coupled to and cooperable with a data puncturer or a data repeater. An information source can produce for each transport channel first configuration information and second configuration information, wherein the first configuration information is indicative of how the associated transport channel is to be configured if a first modulation type is used for a current radio block, and wherein the second configuration information is indicative of how the associated transport channel is to be configured if a second modulation type is used for the current radio block. The physical layer can include a description information source that provides description information from which various configurations of the transport channels can be determined.

Abstract: Parallel concatenated turbo trellis encoder structure. A dual path turbo trellis coded modulation encoder employs two interleavers and two constituent encoders and is also operable to encode symbols whose code rate may vary on a symbol by symbol basis. In addition, each of the interleavers of the parallel concatenated turbo trellis encoder structure may perform modified interleaving where input bits are treated differently depending on the order in which they are received. This interleaving may be differentiated on a bit level. In some embodiments, the implementation of the parallel concatenated turbo trellis encoder structure ensures that the output order of encoded symbols is the same as the order in which the input is received. This input may itself be in the form of bits and/or symbols. Alternatively, the parallel concatenated turbo trellis encoder structure may also support a scrambled ordering of the encoded output with respect to the input.

Abstract: A P-tap parallel decision-feedback decoder (PDFD) is also disclosed. The PDFD includes a plurality of state shift registers. For each state of a code utilized by an incoming data stream, a survivor metric for a state is shifted into the first shift register for the state. Each first shift register has M cells. A decision device is coupled to the first shift registers for outputting a first survivor metric according to survivor metrics in the first shift registers. A second shift register has N delay cells, and the first survivor metric is shifted into the second shift register.

Abstract: Provided are a method, system, and program for generating parity data when updating old data stored in an array of storage devices in a data organization type which utilizes parity data. In one embodiment, a logic engine has plural registers or store queues in which new data obtained in a read operation is stored. A logic function such as an Exclusive-OR function is performed on the new data in each of the plural registers using old data obtained in another read operation. A logic function such as an Exclusive-OR function is performed on the intermediate data in one of the plural registers using old parity data of a first type obtained in another read operation, to generate new parity data of the first type. A logic function such as an Exclusive-OR function is performed on the intermediate data in another of the plural registers using old parity data of a second type obtained in another read operation, to generate new parity data of the second type.

Abstract: A conversion processing system includes conversion processing which converts a conversion object into one or more conversion candidates, and performs the conversion processing related to time information. The conversion object is a letter or a symbol, for example. The system has a dictionary, a time detection part and a conversion part. The dictionary relates one or more conversion candidates corresponding to the conversion object to the time information, and stores these. The time detection part outputs the time information. When converting the conversion object into one or more conversion candidates, the conversion part refers to the time information. By this, the conversion processing can be optimized, and conversion efficiency can be improved.

Abstract: A method and apparatus for providing local data persistence for a Web server application. A Web page provided to a client application (e.g., a Web browser) by the server application contains a data entry area as well as a save button and a restore button. When the user actuates the save button, the Web page dynamically creates a new page that contains the data to be saved and a message prompting the user to save the new page in a user-designated location by using the file-saving function of the Web browser. The user may then close the original Web page, and the new page will remain saved locally. The user may then return to the original Web page and actuate the restore button to repopulate the original Web page with the data that has been saved locally. The save page contains a script function which becomes active when the page is loaded to perform the desired restoration function.

Abstract: A swoopy text method and system for generating and displaying curved text to connect primary source data with secondary data, including alternatively connecting different text streams, to augment the meaning of original text and/or to replace the meaning of the original text stream with secondary data.

Abstract: A character string is extracted from an image photographed by a camera. It is determined whether or not the extracted character string includes an address on a network. Software for accessing the address runs. Accordingly, a user can easily access a desired address on the network.

Abstract: An interface and a method is provided for permitting a user to explore a collection of data. The data collection provides nodes as structural elements, and references which are assigned to nodes and hold the address of another node. Multiple references can be assigned to each node, thus guiding a user of the system to multiple other nodes, and multiple references can hold the same address, so that multiple nodes can have references pointing to the same node. The interface allows visualizing the network created by the interconnection of the nodes on a display region. The interface also allows the user to intuitively navigate along the references in both directions of the references, so that the user can explore which nodes are referenced by a certain node, and also by which nodes a certain node is referenced.

Abstract: Collisions between document objects on a document page are resolved. A collision is identified and a two-dimension resolution of the collision is provided by moving the object the shortest distance from a pre-collision location that would avoid the collision. The process calculates the shortest distance to move the object. The invention also may establish logic that designates some objects as “not able to collide” and the process will not move those objects to resolve a collision.

Abstract: A method and system for the automatic layout of a photobook page are disclosed. The method includes receiving a number of images for placement onto the photobook page, the photobook page having a first dimension and a second dimension wherein the first dimension is greater than the second dimension. A square root of the number of images is approximated. A total number of page divisions is determined along the first dimension of the photobook page, wherein the total number of page divisions correspond to the approximated square root. Each photobook page is evaluated for division into a regular array of image areas using a modulus of the number of images and the square root. A number of image areas to be included in a page division is determined using a ratio of the number of images to the approximated square root. The images are distributed automatically on the photobook page among the multiple image areas.

Abstract: Attributes can be set for an entire document, each chapter, and each page by using an entire document attribute, chapter attribute, and page attribute. When the print format of a chapter is set with a chapter attribute different from the entire document attribute, this chapter is printed in a print format complying with the chapter attribute. Similarly, when the print format of a page is set with a page attribute different from the entire document attribute or chapter attribute, this page is printed in the print format complying with the page attribute. In hierarchically displaying the document structure with a book, chapters, and pages, a predetermined icon is so added as to identify a chapter or page having a unique attribute.

Abstract: A remote document viewing system that allows wireless handheld devices equipped with only built-in browsers to view document files stored in remote computers in real time without downloading the entire document files first onto the wireless handheld devices, and without requiring the wireless handheld devices to pre-install any special applications. The document file content is converted into a series of web pages optimized for the display of the wireless handheld device.

Abstract: Programs, methods and apparatus for context sensitive font generation, especially handwriting fonts. In a preferred embodiment, a computer program product contains instructions to identify a character string including upper case, lower case, and/or symbolic characters; identify the first character in the string; identify a plurality of handwritten glyphs corresponding to the character; select one of the glyphs based upon an adjacent character in the string; and repeat the foregoing steps, thereby converting the character string.

Abstract: A graphical user interface supports an interactive client-server authentication based on Random Partial Pattern Recognition algorithm (RPPR). In RPPR, an ordered set of data fields is stored for a client to be authenticated in secure memory on the server side. A graphical user interface presents a clue generated at the server to the client, such positions in the ordered set of a random subset of data fields from the ordered set. The client enters input data in multiple fields of the interface according to the clue, and the server accepts the input data from the client. The input data includes storage units representing alpha-numeric characters, images and colors corresponding to the field contents for the data fields. The interface includes indicators for elapsed time and status of the authentication session.

Abstract: The present invention relates to a method of establishing a customized webpage desktop applied in an information apparatus. After an operating system is enabled, a shell program is initialized, and a browser is called to register the browser as a desktop format, and to cause the browser to display information on the corresponding desktop area of the information apparatus. A webpage file is read from a specific directory according to a path pointed to by the shell program. The webpage file has local application links. The browser reads the webpage file and displays the webpage file in the desktop format in the desktop area of the information apparatus to form the customized webpage desktop.

Abstract: In a display of properties (or metadata) for multiple selected files, properties may be aggregated. Visual differentiation may be used to associate displayed aggregated values with one or more selected files to which the values pertain. Multi-value properties may also be aggregated and differentiated and/or accentuated. When aggregating multiple multi-value properties, steps may be taken to carry relative priority or positioning assigned by each of the selected files to which the multi-value properties pertain. Aggregated multi-value properties may include prompt text informing them of editing options, and users may edit properties by editing the displayed aggregated properties. Changes to the aggregated properties may be applied to the properties of the various selected files.

Abstract: A first primary display window displays first primary objects linked to a scope window. A second primary display window displays second primary objects linked to the scope window. The second primary objects are independent of the first primary objects. One or more secondary display windows display secondary objects linked to one of the primary display windows. A secondary display window may be linked to the scope window so that the secondary objects displayed in the secondary display window are linked to the scope window. Data to create a window may be query-driven and the window type may be data-driven. Window type may be changed after creation and windows may be docked to each other to prevent overlap. Windows may link back to the scope window.