Abstract: A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall current carrying capacity of power transistor structure.

Abstract: A method of producing a semiconductor device includes, in order to electrically connect a lower layer wiring and an upper layer wiring opposite to each other with an interlayer insulation film intervening between them, a step of forming a via-hole, which exposes the lower layer wiring upward from the lower layer wiring through the interlayer insulation film, a step of forming a protective film for preventing erosion, and a step of forming a plug for electrically connecting the lower layer wiring to the upper layer wiring, wherein the protective film is formed by a CVD process in order to cover a residue having stuck to the inner wall of the hole concerned during forming the via-hole.

Abstract: To provide a method of forming a wiring for the purpose of providing a semiconductor device, which is superior in reliability and cost performance. Further, to provide methods of manufacturing a semiconductor device and a display device by using the method of forming the wiring according to the present invention. According to the present invention, when a wiring material and the like is directly patterned on a substrate mainly having an insulating surface by droplet discharging method, a wiring is formed at a position including at least an opening in contact with an underlying portion on an insulating film provided with the opening by dropping a liquid droplet containing a conductive composition by droplet discharging method. By heating the substrate with the wiring formed thereon, a surface of the wiring on the opening and a surface of the wiring other than the wiring on the opening are approximately leveled, and the opening is filled.

Abstract: Silicon oxide etching solutions containing the product of at least one bifluoride source compound dissolved in a solvent consisting of at least one carboxylic acid, and further comprising from about 0.5 to about 3 percent by solution weight of hydrofluoric acid and from about 1 to about 5 percent by solution weight of water, wherein the total concentration of bifluoride source compound is between about 1.25 and about 5.0 moles per kilogram of solvent. Methods for selectively removing silicon oxides and metal silicates from metal surfaces are also disclosed.

Abstract: An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire (304) attached to the pad by ball bonding (305), a loop (306) in the wire closed by bonding the wire to itself (307) near the ball, and a portion (307) of the remainder of the wire extended approximately parallel to the surface. The interconnect can be confined to a space (308) equal to or less than three ball heights from the surface.

Abstract: A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) in a second region (3), then forming insulating films (20, 28) on the etching stop insulating film (18) and the wiring (16), then forming a hole (28) on a first-stage conductive plug (15b) by etching a part of the insulating films (20, 28) until the etching stop insulating film (18) is exposed, then exposing an upper surface of the first-stage conductive plug (15b) by etching selectively the etching stop insulating film (18) through the hole (28), and then forming a second-stage conductive plug (31a) in the hole (28).

Abstract: A dual damascene process employs a via fill material (38) with an etch rate that is within 60% of an etch rate that an underlying dielectric layer (34) etches for a given dielectric etch chemistry in which a trench (48) and via (50) are being formed. In one embodiment, an organic via fill material plug (40) is employed in conjunction with a bottom anti-reflective coating (BARC) material layer (42). Both the organic via fill material plug (40) and the BARC material layer (42) are selected to have a material with an etch rate that within 60% of an etch rate that an underlying dielectric layer (34) etches for a given dielectric etch chemistry in which the trench (48) and via (50) are formed.

Abstract: The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

Abstract: A semiconductor device and a process for producing the same, the semiconductor device comprising two conductive layers provided as separate layers, and an insulating layer sandwiched by the two conductive layers, in which the two conductive layers are electrically connected to each other with an embedded conductive layer or an oxide conductive layer provided as filling an opening formed in the insulating layer, and the embedded conductive layer comprises an organic resin film containing a conductive material dispersed therein or an inorganic film containing a conductive material dispersed therein.

Abstract: An alternating source MOCVD process is provided for depositing tungsten nitride thin films for use as barrier layers for copper interconnects. Alternating the tungsten precursor produces fine crystal grain films, or possibly amorphous films. The nitrogen source may also be alternated to form WN/W alternating layer films, as tungsten is deposited during periods where the nitrogen source is removed.

Abstract: In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of low-k dielectrics in passivation levels. Low-k dielectrics in passivation levels help lower capacitance on metal lines, thereby reducing RC delay and increasing signal propagation speeds.

Abstract: A method of patterning and releasing chemically sensitive low k films without the complication of a permanent hardmask stack, yielding an unaltered free-standing structure is provided. The method includes providing a structure including a Si-containing substrate having in-laid etch stop layers located therein; forming a chemically sensitive low k film and a protective hardmask having a pattern atop the structure; transferring the pattern to the chemically sensitive low k film to provide an opening that exposes a portion of the Si-containing substrate; and etching the exposed portion of the Si-containing substrate through the opening to provide a cavity in the Si-containing substrate in which a free-standing low k film structure is formed, while removing the hardmask. In accordance with the present invention, the etching comprises a XeF2 etch gas.

Abstract: Methods for planarizing a metal layer in a semiconductor device are disclosed. An illustrated example method comprises dividing a metal layer into a first section and a second section. A polishing removal rate associated with the first section is greater than a polishing removal rate associated with the second section. The method also includes forming an oxide layer on the first section of the metal layer; and planarizing the oxide layer and the metal layer using a chemical mechanical polishing process.

Abstract: A semiconductor device which includes: a semiconductor chip bonded to a surface of a solid device; and a stiffener surrounding the periphery of the semiconductor chip. A surface of the stiffener opposite from the solid device is generally flush with a surface of the semiconductor chip opposite from the solid device.

Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

Abstract: The present invention relates to a method of manufacturing semiconductor device with composite buffer layers. The method includes etching grooves in n type and p type semiconductor wafers respectively. The areas of grooves in n type wafer just correspond to the areas without grooves in p type wafer, and vice versa. The grooves in both n type and p type wafers have the same depth. Two wafers are directly bonded together so that the grooves in one wafer are filled with the grooves in the other wafer. Then, chemical bonding is implemented. The bonding may also be made through thin dielectric layer (e.g. SiO2). If necessary, grinding, polishing or chemical mechanical polishing processes are carried out to remove the redundant material. Thereby, it is easy to manufacture the semiconductor device with composite buffer layer as voltage sustaining layer.

Abstract: Provided is a method of manufacturing a nano scale semiconductor device, such as a nano scale P-N junction device or a CMOS using nano particles without using a mask or a fine pattern. The method includes dispersing uniformly a plurality of nano particles on a semiconductor substrate, forming an insulating layer covering the nano particles on the semiconductor substrate, partly removing the upper surfaces of the nano particles and the insulating layer, selectively removing the nano particles from the insulating layer, and partly forming doped semiconductor layers in the semiconductor substrate by partly doping the semiconductor substrate through spaces formed by removing the nano particles.

Abstract: A method of reducing foreign material concentrations in an etch chamber having inner chamber walls is described. The method includes the step of etching a work piece in the etch chamber such that reaction products from the work piece having one or more elements form a first layer of reaction products that partially adhere to the inner chamber walls. A species is introduced into the etch chamber that increases the adhesion of the first layer of reaction products to the inner chamber walls.

Abstract: Processes for treating a morphologically-modified surface of a silicon upper electrode of a plasma processing chamber include exposing the surface to a gas composition containing at least one gas-phase halogen fluoride. The gas composition is effective to remove silicon from the morphologically-modified surface and restore the surface state.

Abstract: A method of making a transistor with independent gate structures. The gate structures are each adjacent to sidewalls of a semiconductor structure. The method includes depositing at least one conformal layer that includes a layer of gate material over a semiconductor structure that includes the channel region. A planar layer is formed over the wafer. The planar layer has a top surface below the top surface of the rat least one conformal layer at a location over the substrate. The at least one conformal layers are etched to remove the gate material over the semiconductor structure.

Abstract: A method includes performing a first etch process to form a via hole in a dual-damascene integrated circuit structure comprising a first dielectric layer and a second dielectric layer. The via hole extends at least substantially through the first and second dielectric layers. The method further includes filling at least a portion of the via hole with a plug material to form a plug within the via hole, and performing a second etch process through the first dielectric layer and the portion of the plug adjacent the first dielectric layer to form a trench in the first dielectric layer. The second etch process is performed using an RF power of less than 1,000 Watts and using an etching chemistry that includes CF4 and N2. For example, second etch process may use an etching chemistry of CF4/N2/Ar, which may additionally include one or both of CO and O2.

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.

Abstract: A method for manufacturing a micro-structural unit is provided. By the method, micro-machining is performed on a material substrate including first through third conductive layers and two insulating layers, one of which is interposed between the first and the second conductive layers, and the other between the second and the third conductive layers. The method includes several etching steps performed on the layers of the material substrate that are different in thickness.

Abstract: The present invention provides a method for etching a substrate 100. The method includes conducting a first etch on an anti-reflective layer 170 and a portion of a hardmask layer 140, 150 to form an opening 162 in the substrate 100. The first etch is designed to be selective to a remaining portion of the hardmask layer 140, 150. A second etch, which is different from the first etch, is conducted on a remaining portion of the hardmask 140, 150, and it is designed to be less selective than the first etch to the remaining portion of the hardmask 140, 150. The first etch allows polymer to build up on the sidewalls of the opening 162, and the polymer substantially remains on the sidewalls during the second etch.

Abstract: By heat treating a silicon dioxide liner prior to patterning a silicon nitride spacer layer, the etch selectivity of the silicon dioxide with respect to the silicon nitride is increased, thereby reducing or eliminating the problem of pitting through the silicon dioxide layer. This allows further scaling of the devices, wherein an extremely thin silicon dioxide liner is required to obtain an accurate lateral patterning of the dopant profile in the drain and source regions.

Abstract: The present invention relates to a method for fabricating a cavity in substrate for a component for electromagnetic waves, the method comprising providing said cavity by removal of material from said substrate by removal of material by immersing the substrate in a liquid bath of a chemical etchant, so that resultant cavity has a top and a bottom side and sidewalls, and said cavity at one of said top and/or bottom sides exhibits an at least a four sided opening having an opening with at least two different adjacent angles. The invention also relates to the component for microwave applications.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. A minute pattern is formed using a hard mask film of a series of a nitride film as an etch mask. Before a hard mask film removal process is performed, the step of performing given etching using an oxide film etchant is added to remove an abnormal oxide film on the nitride film. It is thus possible to effectively remove the hard mask film. Generation of voids in a pattern below the hard mask film can be also effectively prevented using BOE in which the composition ratio of HF and NH4F and an etching temperature are optimized as an oxide film etchant.

Abstract: Disclosed is a method for manufacturing a semiconductor laser device, comprising the steps of: (a) forming a first conductive-type clad layer, an active layer, and a second conductive-type clad layer on a first conductive-type semiconductor substrate; (b) forming a ridge structure by selectively etching the second conductive-type clad layer; (c) forming a current blocking layer around the ridge structure, the current blocking layer having protrusions on the upper surface thereof adjacent to the ridge structure, and an amorphous and/or polycrystalline layer on a partial area thereof; and (d) removing at least the amorphous and/or polycrystalline layer from the current blocking layer, and wet-etching the upper surface of the current blocking layer so that the protrusions are reduced in size.

Abstract: A method for texturing surfaces of silicon wafers comprising the steps of dipping the silicon wafers in an etching solution of water, concentrated hydrofluoric acid and concentrated nitric acid and setting a temperature for the etching solution. The etching solution comprises, in percent, 20% to 55% water, 10% to 40% concentrated hydrofluoric acid and 20% to 60% concentrated nitric acid and the temperature of the etching solution is between 0 and 15 degrees Celsius.

Abstract: A method for the caustic etching of silicon which is of importance for the semiconductor industry and silicon wafer manufacture in particular, that includes using one or more iodate or chlorite salts as additives in the etching process to achieve improved surface conditions, such as smaller facets and lower roughness, on the resulting silicon substrate.

Abstract: A method of manufacturing a MOS transistor is provided that achieves high-speed devices by reducing nitrogen diffusion to a silicon substrate interface due to redistribution of nitrogen and further suppressing its diffusion to a polysilicon interface, which prevents realization of faster transistors. An oxide film is exposed to a nitriding atmosphere to introduce nitrogen into the oxide film, and a thermal treatment process is performed in an oxidizing atmosphere. The thermal treatment process temperature in the oxidizing atmosphere is made equal to or higher than the maximum temperature in all the thermal treatment processes that are performed later than that thermal treatment process step.

Abstract: A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of the first and second substance may include silicon and nitrogen. The nucleation layer may comprise silicon nitride. Further, a deposition method may include forming a first part of a nucleation layer on a first surface of a substrate and forming a second part of a nucleation layer on a second surface of the substrate. A deposition layer may be formed on the first and second parts of the nucleation layer substantially non-selectively on the first part of the nucleation layer compared to the second part. The first surface may be a surface of a borophosphosilicate glass layer. The second surface may be a surface of a rugged polysilicon layer.

Abstract: A method of forming a high dielectric oxide film conventionally formed using a post formation oxygen anneal to reduce the leakage current of such film includes forming a high dielectric oxide film on a surface. The high dielectric oxide film has a dielectric constant greater than about 4 and includes a plurality of oxygen vacancies present during the formation of the film. The high dielectric oxide film is exposed during the formation thereof to an amount of atomic oxygen sufficient for reducing the number of oxygen vacancies and eliminating the post formation oxygen anneal of the high dielectric oxide film. Further, the amount of atomic oxygen used in the formation method may be controlled as a function of the amount of oxygen incorporated into the high dielectric oxide film during the formation thereof or be controlled as a function of the concentration of atomic oxygen in a process chamber in which the high dielectric oxide film is being formed.

Abstract: A dielectric deposited on a substrate may be exposed to a salt solution. While exposed to the salt solution, an oxide is deposited on the dielectric.

Abstract: A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants including, for example, ozone, peroxides, permanganates, hypochlorites, chlorites, chlorates, perchlorates, hypobromites, bromites, bromates, hypoiodites, iodites, iodates and strong acids.

Abstract: An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing a hafnium metal layer on a substrate surface by atomic layer deposition and depositing a hafnium oxide layer on the hafnium metal layer by atomic layer deposition form a hafnium oxide dielectric layer substantially free of silicon oxide. Dielectric layers containing atomic layer deposited hafnium oxide are thermodynamically stable such that the hafnium oxide will have minimal reactions with a silicon substrate or other structures during processing.

Abstract: A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.

Abstract: A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

Abstract: This invention relates to a papermaking felt which makes it possible to increase the proportion of the base body thereby preventing flattening without costing extra production man-hour, and to maintain the functions such as the water drainage, wet paper smoothening capability, and wet paper web transport capability throughout its entire use period. The papermaking felt is composed of a base body and a batt fiber layer, characterized in that one or more thicknesses of endless base bodies are disposed on the felt back-face side and one or more thicknesses of open-ended base bodies is annularly wound not less than one turn on the felt front-face side.

Abstract: The invention is directed at a disposable dry cleansing article that is formed from a melt extruded fibrous web that has incorporated into the fibers forming the web from 0.5 to 20 percent by weight of a melt extruded lathering surfactant. The invention, dry article generally comprises a melt extruded fibrous web of a thermoplastic polymer having a basis weight of from about 10 to 200 g/m2, preferably 10 to 150 g/m2 wherein the fibers have a lathering surfactant incorporated into the fiber at a level that allows the article to be used two (2) or more times with a rinse foam volume of 15 or more, with an initial foam volume of at least 50 ml.

Abstract: Provided are near-infrared light-absorbing glass in which good color compensating characteristics are maintained even without containing harmful arsenic, permitting the thinning of the glass, and having good weatherability and forming properties; a near-infrared light-absorbing element comprised of such glass; a near-infrared light-absorbing filter employing such glass. Also provided, at low cost, are near-infrared light-absorbing glass permitting good color compensating, a near-infrared light-absorbing element comprised of such glass, and a near-infrared light-absorbing filter comprising such elements. The glass comprises cationic components with a certain composition as well as F? and O2? as anionic components. Alternatively, the glass is near-infrared light-absorbing glass, wherein the glass exhibits properties, based on a thickness of 0.

Abstract: A glass substrate for use as the substrate of an information recording medium such as a magnetic disk, magneto-optical disk, DVD, or MD or of an optical communication device, and a glass composition for making such a glass substrate, contains the following glass ingredients: 45 to 75% by weight of SiO2; 1 to 20% by weight of Al2O3; 0 to 8% by weight, zero inclusive, of B2O3; SiO2+Al2O3+B2O3 accounting for 60 to 90% by weight; a total of 0 to 20% by weight, zero inclusive, of R2O compounds, where R=Li, Na, and K; and a total of 0 to 15% by weight, zero inclusive, of TiO2+ZrO2+LnxOy, where LnxOy represents at least one compound selected from the group consisting of lanthanoid metal oxides, Y2O3, Nb2O5, and Ta2O5.

Abstract: A silicon nitride sintered body exhibiting a high heat conductivity, the silicon nitride sintered body includes a rare earth element in an amount of 2 to 17.5 mass % in terms of the oxide thereof, Fe in an amount of 0.07 to 0.5 mass % in terms of the oxide thereof, Ca in an amount of 0.07 to 0.5 mass % in terms of the oxide thereof, Al in an amount of 0.1 to 0.6 mass % in terms of the oxide thereof, Mg in an amount of 0.3 to 4 mass % in terms of the oxide thereof, and Hf in an amount not larger than 5 mass % (including 0 mass %) in terms of the oxide thereof.

Abstract: Hydrocracking catalyst composition comprising an optional metal hydrogenation component supported on a carrier comprising a zeolite of the faujasite structure having a unit cell size in the range of from 24.10 to 24.40 ?, a bulk silica to alumina ratio (SAR) above about 12, and a surface area of at least about 850 m2/g as measured by the BET method and ATSM D4365-95 with nitrogen adsorption at a p/po value of 0.03.

Abstract: This invention relates to a method of preparing a supported catalyst comprising the steps of contacting a solid titanium or solid aluminum compound with a supported catalyst compound, and heating the combination to at least 150° C.

Abstract: The application describes a mixed olefin polymerization catalyst composition comprising a support, a reaction product of at least one first organometallic compound and a first activator capable of rendering the first organometallic compound active for insertion polymerization, and at least one second organometallic compound, the activator incapable of rendering the second organometallic compound active for polymerization of the monomers. The mixed catalyst composition can be used to prepare a first polymer component in a first polymerization reactor stage and then, when an effective activator is added for the second organometallic compound, the catalyst composition can be used to prepare a second polymer composition that is homogeneously blended with the first polymer component.

Abstract: The present invention provides a heat-sensitive recording material comprising a substrate and a heat-sensitive recording layer provided thereon, the layer comprising a color forming system that combines an electron-donating colorless dye and an electron-accepting compound, in which the electron-accepting compound is a compound represented by the formula R1-Ph-SO2R2 (wherein R1 represents a hydroxyl group or an alkyl group, R2 represents -Ph, —NH-Ph, -Ph-OR3 or —NH—CO—NH-Ph, R3 represents an alkyl group, and Ph represents a phenyl group), and at least the heat-sensitive recording layer is formed by curtain-coating a coating solution for the heat-sensitive recording layer.

Abstract: Combination of a cytochrome P450 monooxygenase inducer with an organophosphate pesticide (insecticide or acaracide) provides effective control of ticks and flies, particularly against organophosphate-resistant strains of the ticks and flies. In use, a pesticidally effective amount of a composition of the cytochrome P450 monooxygenase inducer and organophosphate pesticide is applied to the locus of the targeted tick or fly.

Abstract: Substituted pyrazole compounds of the formula (1). The compounds are synthesized from a pyrazole derivative and a haloalkyleneoxime ester derivative, and have excellent herbicidal effects.

Abstract: A water based drilling fluid for use in drilling a subterranean well through a subterranean formation that swells in the presence of water, the drilling fluid is formulated to include: an aqueous based continuous phase; a weigh material; a shale encapsulator and an optional shale hydration inhibition agent. The shale encapsulator has the formula: which x and y have a value so that the molecular weight of the cation is in the range of about 10,000 to about 200,000 AMU; A is selected from C1–C6 alkyl, C2–C6 ether or amide; R, R? and R? are independently selectable C1–C3 alkyl; and B? is a charge balancing anion to the quaternary amine. The shale encapsulator and the optional shale hydration inhibition agent may be present in sufficient concentrations to reduce the swelling of the subterranean formation in the presence of water.