Abstract: One embodiment of the invention provides a circuit. The circuit includes a switching unit configured to connect or disconnect a voltage domain to a supply voltage input. The switching unit includes a first switch, a second switch and a third switch. The circuit includes a control signal input configured to receive a switch control signal. The circuit includes a signal distribution unit that is configured to output the switch control signal to the first switch delayed by a first time interval and to output the switch control signal to the second switch and to the third switch delayed by a second time interval.

Abstract: A semiconductor device and method of generating clock signals where a phase lock loop (PLL), or a delay lock loop (DLL), comprises a duty cycle correction circuit (DCC) having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate internal clock signals. The shared charge pump adjusts voltage level of control signal (VC) in response to the internal clock signals and provides the control signal VC to each of the amplification parts.

Abstract: Clock generation circuit and method of generating clock signals. The clock generation circuit includes an inverter directly receiving an external clock signal and outputting an inverted external clock signal, M (where M is an integer ?1) loop circuits arranged in series, the first loop circuit receiving the inverted external clock signal, each of the N loop circuits having n (where n is an integer ?2) nodes, each of the M?1 loop circuits generating n intermediate internal clock signals, each at a corresponding one of the n nodes, wherein a frequency of the n intermediate internal clock signals is a multiple of a frequency of the external clock signal and the inverted external clock signal; and n sets of inverters, each including M?1 inverters connected in series, each of the M?1 inverters receiving a corresponding intermediate internal clock signal from a previous loop circuit and outputting a corresponding intermediate internal clock signal to a next loop circuit.

Abstract: A current squaring cell is provided for producing an output current that correlates to the square of an input signal current. The current squaring cell comprises a first circuit portion, which receives a first tail current that is positively proportional to the input signal current, and a second circuit portion, which connects to the first circuit portion and receives a second tail current that is negatively proportional to the input signal current.

Abstract: A power source (201) and a printed transistor circuit (202) are combined with one another in a stacked and integral configuration. In a preferred though optional configuration this combination can further comprise a substrate (200) of choice. The power source can comprise a technology of choice such as, but not limited, to, a battery or a photovoltaic element. These elements can be combined (104) using a joining technology of choice such as, but not limited to, laminating these elements together or printing one upon the other.

Abstract: Provided are an IC and a method for automatically tuning process and temperature variations. The IC includes: a test circuit unit including test circuit elements having identical element values and variations to a tuning-targeted circuit element and at least one reference circuit element having a smaller variation than the tuning-targeted circuit element; a comparator that obtains a difference between intensities of first and second signals detected from the test circuit unit; and a tuning unit that tunes the variation of the tuning-targeted circuit element according to the difference between the intensities of the first and second signals. Thus, process and temperature variations of a circuit element can be detected and accurately tuned with respect to the circuit element itself. Also, the process and temperature variations can be tuned inside an IC. Thus, the time required for tuning the process and temperature variations can be reduced.

Abstract: A high voltage generation circuit includes a pump clock generation unit configured to generate a pump clock signal in response to a pumping enable signal, a charge pump configured to generate a high voltage on an output in response to the pump clock signal, and a switching unit to selectively couple the output of the charge pump to an output node in response to the pumping enable signal.

Abstract: A capacitance multiplier circuit for a filter is provided. The capacitance multiplier circuit capable of adjusting its equivalent capacitance and used in the filter, applied to a Phase Locked Loops (PLLs) circuit, includes a first operational amplifier having a positive input end for receiving an input signal, an output end, and a negative input end connected to the output end, a second operational amplifier having a positive input end, a negative input end connected to the output end of the first operational amplifier through a first resistor, and an output end connected to the negative input end through a second resistor, and a capacitor connected between the positive input end of the first operational amplifier and the output end of the second operational amplifier. An equivalent capacitance of the capacitance multiplier circuit is adjusted by configuring the ratio of the first resistor and the second resistor.

Abstract: An offset canceller outputs a signal during its offset compensating operation and compensates for the offset by capacitance or resistance devices connected externally to an operational amplifier. A driving circuit includes plural output circuits #1 to #n+1 for outputting driving signals to plural output terminals #1 to #n on one outputs and for outputting the driving signals on the other outputs coupled to corresponding plural output selectors #1 to #n, which then select one of two signals output from two neighboring output circuits to transmit the selected signals to the output terminals. The output circuits #1 to #n+1 have other outputs coupled to a decision circuit, which compares the signals to a reference voltage and outputs a decision signal representing the result of comparison at a predetermined timing. The output circuits execute the offset cancel operation responsive to the decision signal.

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: A feedback circuit for an operational amplifier is provided, the circuit comprising a first impedance element in a current flow path between an output of the operational amplifier and a first node, wherein a plurality of impedance elements are, in response to a control signal, selectively connectable either between the first node and a first input of the operational amplifier, or between the first node and a further node, and the further node and the first input of the operational amplifier are at the same potential such that a voltage at the first node is independent of the control signal.

Abstract: Novel uses of current-dividing multi-transistors (composite transistors) are described. The composite transistors can replace transistors in otherwise traditional circuits by making suitable design changes. Arrangements of these composite transistors in amplifiers and mixers allow easy selection of current and hence gain in circuits driven by them. In appropriate configurations, they allow the designer to dynamically select the current provided to successive stages. The invention may be used in any integrated circuit technology and assists designers in achieving effective and efficient designs.

Abstract: Embodiments of the present invention include circuits and methods with wide bandwidths. In one embodiment, parasitic capacitances of the output of a first stage and the input of a second stage are included in a network. The output of the first stage is coupled to the input of the network, and the input of the second stage is coupled to an intermediate node of the network. In one embodiment, the parasitic capacitance of the second stage is the largest capacitance in the network. In another embodiment, passive networks are coupled to the outputs of a stage, and one or more current injection circuits may be used to extend the bandwidth of the circuit.

Abstract: The output of a commercially available integrated high gain differential amplifier that already has reasonable linearity is connected back to the (?) input to obtain the well known circuit configuration for a non-inverting amplifier, whose gain may be unity or greater, and whose linearity in response to the (+) input is to be improved. We operate the part with power supplies that are dynamically varied to always be the amplifier input+N volts and that input-N volts. This allows the part to remain a low voltage swing part (±N volts) even though the actual output might swing several times that ±N volts. It improves linearity because the part is almost always operating at nearly ‘the same operating point’ relative to the perceived power supplies. The dynamically tracking power supplies maybe obtained from plus and minus higher voltage work supplies and the use of symmetrical current mirrors to produce matched ±N volt offsets that are referenced to the input of the amplifier.

Abstract: A relatively wide bandwidth low noise amplifier with an active input matching network. The active load maybe formed from a field effect transistor (FET) or high electron mobility transistor (HEMT) in a common gate configuration. The active load input matching network has a lower overall noise component to only transistor channel noise than reactive matching components, such as inductors and capacitors. By utilizing the active mode input matching network in accordance with the present invention, the circuit layout such amplifiers can be reduces significantly, for example, 23 mils×47 mils.

Abstract: An operational amplifier includes a differential amplifier circuit, receiving a low voltage signal, and a current mirror circuit provided on the downstream. The differential amplifier circuit also includes low withstand voltage N-channel transistors, connected to respective input terminals, and high withstand voltage N-channel transistors, connected to the drain electrodes of the low withstand voltage transistors via junction points, respectively. To the gate electrodes of both the high withstand voltage transistors supplied is a bias voltage. The source electrodes of the low withstand voltage transistors are connected to the drain electrode of another low withstand voltage transistor, which has its gate electrode supplied with a bias voltage so as to operate as a current source. Those low withstand voltage transistors are smaller in size than the high withstand voltage transistors.

Abstract: A system and method for generating a reset signal within a Phase Locked Loop (PLL) circuit is described. The reset signal is generated by inputting a reference signal and a lock detect signal into reset circuitry. The reset circuitry within the PLL comprises a series of interconnected latches, or D flip-flops, which are used to create a delay time. The delay time is the amount of time the reset circuit will wait until the reset signal indicates a reset. The reset circuit may also generate a reset signal having a pulse width. The pulse width is determined by the series of interconnected latches. The reset signal may be used to reset a Voltage Controlled Oscillator (VCO) or other circuits within a PLL or it may be used by circuits external to the PLL.

Abstract: A phase locked loop filter comprising a first capacitor for connecting to a first charge pump path; and a parallel resistor/capacitor circuit for connecting to a second charge pump path with the resistor/capacitor circuit having a second capacitor; wherein the first capacitor and second capacitor are connected in series to allow a voltage associated with the first capacitor and a voltage associated with the parallel resistor/capacitor circuit to be added together.

Abstract: An auto-adjusting high accuracy oscillator is disclosed, which comprises: a frequency comparator, for comparing a synchronization signal obtained from a USB host with an oscillation signal obtain from a device; a control tuning circuit, further comprising a counter and an adder/sub circuit; and an oscillating element; wherein a variation is obtained by the counting of the counter while transmitting the variation to the adder/sub circuit to be encoded thereby into a digital code so as to enable the oscillating element to perform a frequency up/down operation accordingly for approaching the synchronization signal successively.

Abstract: Current sources are selectively coupled to a current controlled frequency determining circuit of an oscillator. A buffer amplifier has an input coupled to the current controlled frequency determining circuit of the oscillator and the buffer amplifier output is selectively coupled to the current sources not coupled to the frequency determining circuit of the oscillator. The buffer amplifier output maintains substantially the voltage of the current controlled frequency determining circuit on each of the current sources not coupled to the frequency determining circuit so that when any current source is coupled thereto, there is substantially no voltage difference therebetween. This substantially prevents generation of undesirable frequency spikes during coupling of the current sources to the frequency determining circuit of the oscillator.

Abstract: A first current source for sinking electrical current, a first differential circuit for switching the electrical current of the first current source according to an input signal, a second current source for sourcing electrical current, a second differential circuit for switching the electrical current of the second current source according to an input signal, and at least one amplitude limiter/attenuator circuit that reduces the input signal to a desired voltage amplitude and supplies it as a control signal that switches the first and second differential circuits are provided, respective outputs of the first and second differential circuits being combined as output. Disturbances of the output current that are consequent upon driving the switching elements and result from channel charges below gate electrodes and parasitic source and drain capacitances are suppressed.

Abstract: A method and apparatus for providing a radiation hardened Phase Locked Loop (PLL) are presented. The radiation hardened PLL includes an adjustable bandwidth loop filter. The adjustable filter modifies an unfiltered voltage control signal and provides a stable voltage control signal to a Voltage Controlled Oscillator (VCO) during detected radiation induced transient events. The adjustable filter filters out radiation effects by decreasing its bandwidth when a radiation event is detected.

Abstract: An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a transient loss of lock. The lock detect circuit may also include a phase alignment detect circuit to detect a misalignment in the phase of a reference clock and a feedback clock. Additionally, the lock detect circuit may include a reference clock detect circuit to detect if the reference clock signal is detected. Output signals from all of the above circuits may be communicated to a logic circuit in order to create an enhanced lock detect signal. An extended lock detect signal may also be communicated to the logic circuit.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal oscillating at a first frequency in response to (i) a first control signal, and (ii) a second control signal. The second circuit may be configured to generate the second control signal in response to (i) an input signal having a voltage and (ii) the output signal. The second circuit may be configured to compare a peak voltage of the output signal to the input voltage.

Abstract: A high frequency Colpitts oscillation circuit, comprises: a Colpitts oscillation circuit; and a collector grounded amplifier circuit, wherein an output terminal of the Colpitts oscillation circuit is coupled to an input terminal of the collector grounded amplifier circuit, and an output terminal of the collector grounded amplifier circuit is coupled to the Colpitts oscillation circuit as feedback.

Abstract: An apparatus and method for providing a stable gain over wide frequency range in a VCO are presented. A VCO uses a waveform generator along with a bias generator having a frequency select input. The frequency select input is used to adjust the amount of output current and/or gain of the bias generator. The output current of the bias generator determines the frequency of the output of the waveform generator. Multiple bias and waveform generators may be used to expand the frequency range of the VCO. A PLL may be programmed for a variety of output frequencies by using the frequency select input of the VCO.

Abstract: An apparatus and method for providing a power supply compensted voltage or current is presented. A supply compensated current and voltage source utilizes a differential amplifier connected to a bandgap reference voltage and a scaled power supply voltage. When power supply varies, the differential amplifier regulates a stable compensated output. The output may be a compensated voltage or current. In addition, multiple currents and voltages may be referenced from the differential amplifier. The stable compensated output may be supplied as a reference bias for external circuitry. In addition, the compensated output may be supplied to a voltage controlled oscillator.

Abstract: Embodiments of the acoustic galvanic isolator comprise a carrier signal source, a modulator connected to receive an information signal and the carrier signal, a demodulator, and an electrically-isolating acoustic coupler connected between the modulator and the demodulator. The acoustic coupler comprises no more than one decoupled stacked bulk acoustic resonator (DSBAR). An electrically-isolating acoustic coupler based on a single DSBAR is physically small and is inexpensive to fabricate yet is capable of passing information signals having data rates in excess of 100 Mbit/s and has a substantial breakdown voltage between its inputs and its outputs.

Abstract: A re-balancing device (1) comprising a line (12). Said line comprises a first pole (3) of a first conductor (2) and a first pole (6) a second conductor (5) on a first side (8), in addition to a second pole (7) of a first conductor (2) and a second pole (7) of a second conductor (5) on a second side. The second side (9) of the line (12) is connected to a network consisting of impedances and a symmetrical connection (Out), with a first end (10) and a second end (11). The first pole (3) of the first conductor (2) is directly guided to a reference potential (GR) and the two first poles (3,6) form an unsymmetrical connection (In). The second pole (4) of the first conductor (2) is connected to the first end (10) of the symmetrical connection (Out) and connected to the reference potential (GR) via the third impedance (x3).

Abstract: Apparatus and method for communicating high-speed signals between a primary printed circuit board and one or more secondary printed circuit boards. The high-speed signals are communicated between the primary printed circuit boards and the secondary printed circuit boards through multi-layer flexible conductors.

Abstract: A surface acoustic wave device having a surface acoustic wave filter having a comb-shaped electrode pattern formed on a piezoelectric element, electrode terminals for inputting and outputting of the surface acoustic wave filter are connected with corresponding electrode patterns of a package through bumps, wherein the comb-shaped electrode pattern has a pair of reflective electrodes, and an input comb-shaped electrode and an output comb-shaped electrode disposed between the pair of reflective electrodes; and an electrode terminal of either the input comb-shaped electrode or an output comb-shaped electrode is disposed such that the electrode terminal is positioned on the side opposite to the side of the other electrode terminal sandwiching a grounded electrode using a routing pattern.

Abstract: The invention discloses a phase shifter (200, 300) for an electrical signal, comprising input means for said signal, additionally comprising first (120) and second (130) alternative signal paths, the second signal path being achieved by means of an additional signal path (130) which has both its starting and ending point at the first signal path (120), there being a predetermined difference in electrical length between the signal paths, the phase shifter comprising means (240, 242, 243; 340, 342) for closing and opening one of the two signal paths at a time. The means (242, 342) for closing and opening the first signal path is a single switch located at a point in the first signal path between the starting and ending points of the additional signal path, with the electrical distance between said starting and ending points, apart from that occupied by said switch, being virtually zero.

Abstract: Flap resonator, comprising a first electrode and a second electrode, the second electrode comprising a support part separated from an adjacent end of the first electrode by a dielectric part, and a beam part extending from said support part and over at least a part of a surface of the first electrode. The support part has an effective width that is smaller than the width of the beam part.

Abstract: A boundary acoustic wave device includes a solid layer laminated onto a single crystal substrate, electrodes provided between the single crystal substrate and the solid layer, and boundary acoustic wave elements provided on the single crystal substrate having the same cut angle, wherein the propagation direction of one of the boundary acoustic wave elements is different from that of at least one of the other boundary acoustic wave elements. A compact and high-performance boundary acoustic wave device using a boundary acoustic wave is provided by increasing the steepness of a filter band and by forming filters or resonators with different fractional bandwidths on a single substrate.

Abstract: In order to permit electronic tuning of the frequency of a circuit including dielectric resonators, such as a dielectric resonator filter, tuning plates are employed adjacent the individual dielectric resonators. The tuning plates comprises two separate conductive portions and an electronically tunable element electrically coupled therebetween. The electronically tunable element can be any electronic component that will permit changing the capacitance between the two separate conductive portions of the tuning plates by altering the current or voltage supplied to the electronically tunable element. Such components include virtually any two or three terminal semiconductor device. However, preferable devices include varactor diodes and PIN diodes.

Abstract: A band-pass filter (10) for reducing harmonic electromagnetic signals includes an input line (100), an output line (120), at least one first resonator (140), and at least one second resonator (160). The input line inputs electromagnetic signals. The output line outputs electromagnetic signals. The first resonator includes a first grounded end (141), electronically connected to the input line, and a first open end (142). The second resonator is disposed parallel to the first resonator. The second resonator includes a second grounded end (161), electronically connected to the output line, and a second open end (162). The first grounded end is disposed in the same direction as the second grounded end, and the first open end is disposed in the same direction as the second open end.

Abstract: Inside a multilayer dielectric substrate, there are a spiral-shaped first slot set in a part of a first ground conductor layer and a spiral-shaped second slot in a part of a second ground conductor layer put on the front surface of the multilayer dielectric substrate, the first slot and the second slot are opposite in a spiral winding direction and the first slot and the second slot overlap with each other as viewed from the top face, so that a resonance phenomenon can be produced at a frequency lower than a resonance frequency of a resonator with a conventional structure.

Abstract: The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.

Abstract: An apparatus comprises a ring of magnetic material, a source for applying a setting magnetic field to the ring, and first and second electrodes for applying an electric current to the ring. A method of using the apparatus to write to a magnetic storage medium is also provided.

Abstract: A method and apparatus for generating and measuring a torsional wave in a rod, shaft or pipe using magnetostriction are provided. The magnetostrictive transducer includes at least one strip attached to a predetermined position of a rod member, an insulator disposed around the strip, a coil wound around the insulator, and magnets providing a bias magnetic field to the strip, wherein a plurality of strips are attached to the rod member at predetermined intervals in a circumferential direction, and one pole of the magnet is close to an end of a first strip among the plurality of strips, and another pole of the magnet is close to an end of a second strip among the plurality of strips.

Abstract: Method and arrangement for providing a magnetic switch arrangement comprising a first magnetic system, a second magnetic system and a magnetic switching element. The first magnetic system (24) is arranged for biasing the magnetic switching element (18) and the second magnetic system (25) is arranged to interact with the biasing magnetic field from the first magnetic system at the magnetic switching element so that the magnetic switching element is in a predefined state. The second magnetic system (25) includes two equally polarized permanent magnets (4, 5) positioned at a predefined distance apart. An advantage of the method and arrangement is its provision of a magnetic switch arrangement which shows an improved tolerance towards deviations in the magnetic field of the permanent magnets.

Abstract: A gradient coil arrangement generates magnetic field gradients across the main magnetic field of a magnetic resonance imaging system and includes a first conductive member, and a second conductive member electrically coupled to the first conductive member, wherein the second conductive member forms a segment that has an approximate shape of an arc when viewed along a direction of extension of the first conductive member.

Abstract: The invention relates to a magnetic bearing element having at least one annular permanent magnet (2, 3) that is surrounded by an annular binding band (5), which element is characterized in that the permanent magnet (2, 3) is divided at least one location (4) and spaced apart there.

Abstract: The object of the present invention is to provide an eddy current retarder capable of ensuring brake capacity and preventing magnetic leak. In one preferred embodiment of the invention, an eddy current retarder (1) comprises a first magnet ring (18) disposed opposite a brake rotor (3) and comprising a plurality of permanent magnets (16) disposed with a spacing in the circumferential direction, and a second magnet ring (7) disposed opposite the first magnet ring (18) and comprising a plurality of permanent magnets (10) disposed with a spacing in the circumferential direction, wherein the magnetic force of each permanent magnet (10) of the second magnet ring (7) is set larger than the total magnetic force of one or a plurality of permanent magnets (16) of the first magnet ring (18) serving as a partner in forming a magnetic circuit in a brake OFF state. As a result, the magnetic flux leaking to the brake rotor (3) during the brake OFF can be almost zeroed.

Abstract: In inductive devices and transformers, a periodic transformation system reduces or prevents heat or distortion, reduces resistance or impedance and improves output energy. In one embodiment, the Tru-Scale Reactance Transformation System provides an harmonic relationship among the core, winding, magnetic flux, and the current in order to maximize energy output of inductive devices, such as a transformer, by reducing EMF collisions in any type of power systems.

Abstract: A wire-stacked transformer has a first loop supplied with electric power and built with one or more metal plates forming a magnetic field, a second loop disposed in a concentric circle with the first loop and generating induction current, and loop wires disposed between the respective metal plates of the first loop and supplying electric power to each metal plate. Accordingly, efficiency of a power amplifier can be enhanced by reducing the loss of the DAT.

Abstract: An embedded inductor suitable for a wiring board is provided. The wiring board comprises a plurality of patterned conductive layers, at least an insulating layer, and a plurality of conductive vias. The insulating layer is disposed between the neighboring patterned conductive layers. Two of the patterned conductive layers are electrically connected to each other through one of the conductive vias. The embedded inductor comprises a conductive spiral structure and at least an insulating portion. The insulating portion is disposed in the insulating layer and adjacent to the conductive spiral structure. The dielectric constant of the insulating portion is lower than that of the insulating layer. A parasitic capacitance value generated from the operation of the embedded inductor of the present invention is lower. Accordingly, the resonant frequency and the quality factor of the embedded inductor are effectively improved.

Abstract: An embedded inductor suitable for a wiring board is provided. The wiring board having a plurality of patterned conductive layers and a plurality of insulating layers, and one of the insulating layers is disposed between any two adjacent of the patterned conductive layers. The embedded inductor at least includes a first conductive trace, a second conductive trace, a third conductive trace, a first conductive structure, and a second conductive structure. These conductive traces are respectively formed of different patterned conductive layers of the wiring board. The first conductive structure and the second conductive structure passing through the insulating layers connect the conductive traces in a spiral pattern. The embedded inductor with such spiral pattern is arranged on a plane that is perpendicular to the patterned conductive layers of the wiring board.

Abstract: A multi-loop transformer includes a first loop built with at least one metal plate forming a magnetic field with electric power supplied; a second loop, disposed in a concentric manner with the first loop, which generates induction current; at least one first sub-loop disposed in the concentric manner with the first loop, and electrically connected to the first loop, the second loop being disposed between the first sub-loop and the first loop; and electric power supply units, disposed between the respective metal plates of the first loop, which supplies electric power to each metal plate. Accordingly, the present invention can improve the efficiency of a power amplifier by reducing the loss of the distributive active transformer (DAT).

Abstract: The present invention is directed to an inductor fabricated above a substrate surface comprising a first set of inductors in a lower dielectric layer, a second set of inductors in an upper dielectric layer, and interconnects extending between the first and second sets of conductors to form a single continuous helical current path that turns around a central region. Since each turn of the inductor includes only one leg close to the substrate, the parasitic capacitance between the inductor and the substrate can be reduced and there is more free space in the upper and lower layers for increasing the width of the conductors and thereby reducing the series resistance of the inductor. Meanwhile, since the magnetic field generated by the inductor is substantially confined in a closed tube defined by its turns, there is less interference between the inductor and its neighboring components on the same and/or surrounding substrates.