Abstract: A system comprises a storage controller for managing transfers of data between a host and storage memory; a data mover coupled to the storage controller handling data transferred between a host and storage memory; and a buffer coupled to the data mover for storing data being transferred. The storage controller modifies operation of the storage system based on status of the data transfer. An associate method comprises transferring data between a host and storage memory via a storage system, and dynamically adjusting operation of the storage system depending on status of the data transfer.

Abstract: A method and apparatus for ensuring fair and efficient use of a shared memory buffer. A preferred embodiment comprises a shared memory buffer in a multi-processor computer system. Memory requests from a local processor are delivered to a local memory controller by a cache control unit and memory requests from other processors are delivered to the memory controller by an interprocessor router. The memory controller allocates the memory requests in a shared buffer using a credit-based allocation scheme. The cache control unit and the interprocessor router are each assigned a number of credits. Each must pay a credit to the memory controller when a request is allocated to the shared buffer. If the number of filled spaces in the shared buffer is below a threshold, the buffer immediately returns the credits to the source from which the credit and memory request arrived.

Abstract: When reading/writing data between a computer and a mass storage of a mass storage apparatus, the data transmitted from the computer are immediately confirmed by using an output device attached to the mass storage apparatus. There is provided a control device 101 for interpreting a command received from a control device 120 and for carrying out an output processing to an output device 103 if it is decided that the received command is a command for giving an instruction for outputting data stored in a mass storage 102 to the output device 103 in a state of a connection to the control device.

Abstract: An information processing device for setting a parameter about objective data, comprising an output unit for outputting the objective data, an operation unit for detecting an instruction of a user, an output control unit for altering the parameter value with time in order and instructing the output unit to output the objective data the parameter value of which is set, and a processing unit for defining the parameter value when the instruction is detected as the parameter value about the objective data.

Abstract: A data transfer apparatus comprises a plurality of selectors each having two inputs and an output, and a transfer gate gating the transfer of data, wherein one inputs of the plurality of selectors are connected to respective bits of a data bus in the order that transfer bits are arranged, while the other inputs thereof are connected to the outputs of the other selectors in the order, the transfer gate is connected to the output of the final-stage selector of the plurality of selectors, data of the respective corresponding bits of the data bus is set in the respective plurality of selectors when a transmission enable signal is in a negated state, and when the transmission enable signal is arranged to be in an asserted state, the plurality of selectors and the transfer gate are connected so as to serially transfer the data, and the set data is serially transferred in the connecting state by means of a delayed action resulting from an inter-selector delay time.

Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

Abstract: An integrated circuit 2 is provided with multiple bus masters 4, 6 and multiple bus slaves 8, 10, 12, communicating via a multi-channel communication bus. A separate write data channel, read data channel and write response channel are provided as well as a separate write address channel and a read address channel. The provision of a dedicated write response channel frees the read data channel to be more efficiently used for the transfer of read data. Transactions may be burst mode transactions with a single write response corresponding to the write transaction as a whole.

Abstract: A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.

Abstract: Method and apparatus for supporting multi-function PCI devices in PCI bridges. Respective pre-fetch buffers are allocated in response to respective initial data transfer requests issued by a multi-function PCI device. A programmable buffer fill watermark is set up for each pre-fetch buffer. While a portion of data corresponding to the data transfer requests fill the pre-fetch buffers, the fill level of each buffer is monitored to determine if it meets or exceeds its buffer fill watermark. In response to such a condition, the multi-function PCI device is connected to the PCI bridge and a virtual buffer is mapped to the pre-fetch buffer. The pre-fetch buffer is then emptied. During subsequent data transfers, each of the pre-fetch buffer becomes filled, the PCI device is connected, and the virtual buffer is mapped to the filled buffer. The process is continued until all data corresponding to the original data transfer request is received by the multi-function PCI device.

Abstract: A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffers 34 are provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffers 34 are responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.

Abstract: An apparatus and method for remote USB host controlling are described herein.

Abstract: An input processing circuit is interposed between input terminals and input ports of an MPU. An output processing circuit is interposed between output ports of the MPU and output terminals. The input processing circuit includes switch sections and processing sections. The output processing circuit includes switch sections and processing sections. A switch control section switches the switch sections based on switch information stored in a switch information storage section to switch a connection relationship between the input terminals and the input ports, processing for an input signal, a connection relationship between the output ports and the output terminals, and processing for an output signal.

Abstract: The present invention relates to computer systems and methods for providing a memory buffer for use with native and platform-independent software code. In a particular embodiment, the method includes providing a first software program compiled to platform-independent code for execution in a first process of the computer system, providing a second software program compiled to native code for execution in a second process of the computer system, and sending a message from the first process to the second process to request a memory buffer. In another particular embodiment, the computer system includes a processor and a memory. The computer system includes a first process to execute a first software program coded in a safe language, a second process to execute a second software program coded in an unsafe language, and an inter-process communication mechanism that allows data message communication between the first process and the second process.

Abstract: Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.

Abstract: A method for apparatus for masking a postamble ringing phenomenon in a DDR SDRAM comprising the steps of storing data, which are applied from a memory controller, in a data input latch through a data buffer and aligning the stored data, controlling the data input latch in such a manner that the data stored in the data input latch do not change, transmitting the data stored in the data input latch to a data input/output detection amplifier, enabling the data input latch to receive new data after the data, which have been transmitted to the data input/output detection amplifier, are transmitted to a global input/output line. In the method, a stable write operation can be performed even in devices having high operation speeds, such data rates above 400 MHz. Thus, a stable write operation can be performed under conditions wherein the tDQSS has a value of 0.75tCK to 1.25tCK.

Abstract: A method and apparatus for using a binary CAM array to implement Classless Interdomain Routing (CIDR) Address processing. A binary CAM array is segmented into a plurality of array groups, each of which includes a number of rows of binary CAM cells, a group global mask circuit, and a mask valid bit indicating whether the group global mask circuit stores a valid group global mask.

Abstract: Secondary or augmented control of a storage array in a cost effective manner is accomplished by connecting a host to the storage array via a storage adapter independent of a RAID controller. The RAID controller provides primary control for services standard to the RAID controller. Augmented or enhanced services as well as backup control are provided by a control module executing on the host, communicating to one or more selected storage devices within the storage array via the storage adapter. In one embodiment, the control module detects faults or failures in the RAID controller, selectably directs storage commands to the RAID controller, emulates a storage controller including a RAID controller, and provides enhanced or augmented services such as conducting diagnostic, firmware update, or disaster recovery operations.

Abstract: Improved techniques for accessing data storage systems are disclosed. These techniques detect, correct and prevent undesirable access delays experienced in storage systems. “Slow-access” refers to an access operation that does not successfully complete within a predetermined amount of time. When slow-access is detected, an attempt is made to provide data by other means rather than waiting for the access operation to eventually complete. By way of example, parity information is used to generate data rather than waiting beyond a predetermined amount of time for a “slow-read” operation to complete. In addition, preventative measures can be taken to avoid reoccurrence of a “slow-access” operating once it has been identified. These preventative measures, for example, include rewriting the same data to the same data section that caused the slow-access problem or remapping the section to another section in order to avoid the same section of data to cause another slow access problem.

Abstract: A disk array controller which includes a channel interface unit for connecting a host computer through a first type channel, a channel interface unit for connecting a host computer through a second type channel, a plurality of disk interface units provided with an interface with a magnetic disk unit respectively, a cache memory unit, and a shared memory unit. The number of access paths connected to said cache memory unit is less than the number of access paths connected to the shared memory unit.

Abstract: A volume management method is proposed for setting at least a logical volume over a plurality of physical storage devices by taking requested performance of other volumes into consideration.

Abstract: A point-to-point connected multiprocessing node uses a snooping-based cache-coherence filter to selectively direct relays of data request broadcasts. The filter includes shadow cache lines that are maintained to hold copies of the local cache lines of integrated circuits connected to the filter. The shadow cache lines are provided with additional entries so that if newly referenced data is added to a particular local cache line by “silently” removing an entry in the local cache line, the newly referenced data may be added to the shadow cache line without forcing the “blind” removal of an entry in the shadow cache line.

Abstract: A method and apparatus for a dedicated cache memory are described. Under an embodiment of the invention, a cache memory includes a general-purpose sector and a dedicated sector. The general-purpose sector is to be used for general computer operations. The dedicated sector is to be dedicated to use for a first computer process.

Abstract: An instruction virtual address space includes only virtual addresses corresponding to physical addresses of address areas of a physical address space storing pages of only instructions. A data virtual address space includes only virtual addresses corresponding to physical addresses of address areas of the physical address space storing pages of only data. The instruction and data virtual address spaces use duplicated virtual addresses. Instruction and data address translation units translate virtual addresses of the instruction and data virtual address spaces into physical addresses of the single physical address space. A data access efficiency and an instruction execution speed can be improved.

Abstract: A system and method for managing memory data is provided. Data stored within a main memory may be requested by multiple requesters that may include one or more cache memories. When the data is provided by the main memory to a requester, it will be provided in a state that is based on the way the data was recently used by the requesters. For example, if a pattern of read-only usage has been established for the data, the data will be returned to a requester in a shared state. If data that was provided in a shared state must be updated such that the requester is required return to main memory to obtain read/write privileges, the main memory will thereafter provide the data in an exclusive state that allows write operations to be completed. This will continue until a pattern of read-only usage is again established.

Abstract: A destaging method is provided for destaging a storage apparatus system comprising a disk control apparatus that functions as a data storage unit and is provided with disk apparatuses and a first cache memory, and an information processing apparatus that is connected to the disk control apparatus and provided with a second cache memory.

Abstract: A precedence determination system including a first type memory bank configured to receive a first search signal and to provide first search result indications, a second type memory bank configured to receive a second search signal and to provide second search result indications, a precedence number table coupled to the first and second type memory banks and configured to provide programmable precedence numbers, and a precedence determination circuit coupled to the first and second type memory banks and the precedence number table and configured to provide a third search result indication is disclosed. In one embodiment, the first type memory bank can be a static random access memory (SRAM) and the second type memory bank can be a ternary content addressable memory (TCAM).

Abstract: A media processing device uses an external storage device. The media processing device includes a storage device access module, an information source, a program memory, a system memory, a signal processor, a user interface and a system controller. The system controller accesses the external storage device, reads file information, and constructs contents to be displayed. When the system controller receives a command to select a media file, the system controller accesses the external storage device, searches for the selected media file, reads data of the searched media file, copies the read data, and provides the copied data to be decoded. When the system controller receives a commend to encode a signal, the system controller controls the signal processor to encode the input signal into media data, constructs a media file from the encoded media data, positions the media file, and copies the constructed media file when the external storage device is accessible through the storage device access module.

Abstract: This invention is a system and method for preparing workload data that may be accessed in a data storage environment and then replayed for testing or other reasons. The invention has the capability to prepare a trace of I/Os to a data storage system for an extended period of time for replaying these I/Os back to that or another system. Variables may also be manipulated through a preparation process and is particularly useful for customizing benchmarking tests, or consolidation, or trouble-shooting, or capacity planning.

Abstract: Two data centers located in the vicinity are connected using a synchronous transfer copy function, and one of the data centers is coupled with a third data center disposed at a remote location by an asynchronous remote copying function. The order whereat a storage sub-system located in the vicinity has received data from a host is consistently guaranteed, and the third data center holds the data. Further, each storage sub-system includes a function whereby, during normal operation, data can be exchanged and the data update state can be obtained by the storage sub-systems located in the two data centers that do not directly engage in data transmission.

Abstract: A technique that can efficiently achieve migration of a configuration and data between storage units with varying constructions of configuration information and that can alleviate burdens of personal operation by an administrator, etc. With the configuration information of each storage unit controlled by the storage control server, based on each piece of configuration information, the transfer-source configuration information is converted into information necessary for establishing the logical partition configuration of a storage unit which has the transfer-destination logical partition function. The information prepared by the conversion is transmitted to the transfer-destination storage unit and the configuration with the transfer-source logical configuration set as the transfer-destination logical partition is updated in the transfer-destination storage unit.

Abstract: The system is disclosed in which a storage system having data, and meta-data which describes attributes of the data including its address, can copy the data to a secondary system in a more efficient manner. The storage system identifies the blocks which contain the data described in the meta-data, then reads those blocks in the order of their addresses and copies them to the desired target. The method reduces disk access time and thereby speeds copy operations.

Abstract: A 1-chip microcomputer of the present invention has (a) a monitor flag for setting a flag indicating that a specified address space is accessed, (b) an access permission address range setting register, for setting an address range in which an access is permitted while the flag is set, (c) an access permission area detection circuit for judging whether the access is made within the address range thus set, (d) an access permission setting register, for setting whether or not an access with respect to an address other than the address range should be permitted, and (e) memory read-out control circuit and memory writing control circuit for controlling an access with respect to a nonvolatile memory based on a result thus judged and content set by the access permission setting register. With the arrangement, it is possible to provide a 1-chip microcomputer that maintains the security among application programs.

Abstract: An automated data storage library accesses data stored on storage media contained in cartridges in response to commands from an external host. The cartridges may include cartridge memory and a component in the library may include a cartridge memory interface for reading data from and/or writing data to the cartridge memory. When a cartridge is to be stored in the library, the library modifies the contents of the cartridge memory, or the contents of the storage media such that the data stored on the cartridge becomes inaccessible, thereby preventing access to the data outside of the library. To perform an authorized access, the library restores the contents of the cartridge memory or the storage media. Alternatively, the library provides a correction or correction algorithm to the drive to allow access to the data stored on the storage media without removing the access protection of the storage media.

Abstract: There is provided a portable storage device which makes it possible to largely reduce time that is taken to remove the storage cartridge that is inserted and cannot be handled. A removable hard disk cartridge contains a hard disk and a control circuit for control of writing and reading of data in and from the hard disk in a casing thereof. A main unit includes an automatic loading/ejecting mechanism that receives the hard disk cartridge into a predetermined inner position within the main unit and ejects the same out from the position, and a microprocessor that controls storage operation for storing data in the hard disk cartridge. Before the automatic loading/ejecting mechanism performs a receiving operation, it is determined whether access to contents recorded on the hard disk can be gained, and when the access cannot be gained, the receiving operation by the automatic loading/ejecting mechanism is inhibited.

Abstract: A circuit for prevention of unintentional writing to a memory prevents unintentional writing to a nonvolatile memory, after a recovery from a transitory power failure. The circuit includes a low-voltage detection circuit for detecting a power supply voltage drop depending on the state of a control signal for the detection circuit. A writing operation to the memory is prohibited depending on the control signal as well as upon an output signal of the low-voltage detection circuit.

Abstract: An integrated circuit memory device comprises a memory array to store data, a circuit to output the data at a pin, and a register to store a value that indicates a mode of operation of the integrated circuit memory device. The mode of operation is selected from at least one of a synchronous mode of operation and an asynchronous mode of operation. During the synchronous mode of operation, the circuit outputs the data in response to a transition of an external clock signal. During the asynchronous mode of operation, the circuit outputs the data after a period of time from when a transition of an external control signal is detected.

Abstract: The generation and selection of addresses to be employed in a verification environment are tightly coupled to ensure that the addresses a user desires to be selected have been generated. Addresses are generated based on one or more defined selection attributes. The generated addresses are maintained in a database structure that also includes any attributes associated with the addresses. At least one address is selected from the database structure via a filter and forwarded to a component under test.

Abstract: The present invention provides for the employment of a dynamic debugger for a parallel processing environment. This is achieved by dynamically updating mapping information at run-time in a mapping table, wherein the mapping table is read by the dynamic debugger.

Abstract: A system for storing data includes a virtualization apparatus coupled to a computer and to a plurality of storage devices. In response to a request from the computer, the virtualization apparatus issues a notice that a predetermined size of a virtual volume has been allocated to the computer. Upon receiving an access request issued from the computer to the virtual volume, the virtualization apparatus allocates storage areas existing in the plurality of storage devices to the virtual volume, converts the access request received from the computer into an access request addressed to a storage device having the storage devices allocated to the virtual volume, and transmits the converted access request to the storage device.

Abstract: Various embodiments of the present invention are directed to methods by which a virtual-machine monitor can introduce branch instructions, in order to emulate privileged and other instructions on behalf of a guest operating system, into guest-operating-system code residing on virtually aliased virtual-memory pages. In a described embodiment of the present invention, the virtual-machine monitor physically aliases each virtual alias for a particular physical memory page by allocating a physical page for the virtual alias, copying the original contents of the physical memory page to the allocated physical page, or physical alias page, and subsequently patching each physical alias page appropriate to the physical address of the physical alias page.

Abstract: A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be decoded from one or more instructions. Each of the operations may be associated with a respective address. The trace cache memory is coupled to the trace generator and includes a plurality of entries each configured to store one of the traces. The trace generator may be further configured to restrict each of the traces to include only operations having respective addresses that fall within one or more predetermined ranges of contiguous addresses.

Abstract: A system for generating addresses for a digital signal processor in which the program instructions include a code for accessing a memory associated with said processor. An address calculation circuit calculates each access address to the memory on the basis of operation codes designated by the address generation code of one of the instructions and of the content of one address register selected from said address registers. Each address generation code defines an operation code to be sent to the calculation circuit. Each of the address registers is further associated with a configuration register designated at the same time as the address register by the address generation code, and each of the configuration registers contains a set of predefined operation codes, each adapted to command a predetermined calculation operation in the calculation circuit.

Abstract: A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information pursuant to instruction execution. A coprocessor instruction has a format identifying a saturating operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in bits zero through seven of the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated.

Abstract: A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for shifting the data bytes to the start of a instruction based upon a length of an immediately prior instruction.

Abstract: An instruction rollback processor system according to the present invention is provided. The instruction rollback processor system includes: an instruction window buffer storing a plurality of instructions not yet executed and are arranged in a predetermined order; a multiplexer receiving an output of the instruction window buffer; and a rollback unit connected between the output side of the multiplexer and another input of the multiplexer.

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

Abstract: A processing system provides predicate data that indicates whether instructions processed by a processor pipeline should be executed by the pipeline. In architecture, the system of the present invention utilizes a register, a pipeline, and predicate circuitry. The pipeline includes a first stage and a second stage for processing instructions of a computer program. The predicate circuitry is configured to read a first predicate value from the register and to receive a second predicate value. The predicate circuitry may transmit the first predicate value read from the register to the first stage and then select between the first predicate value and the second predicate value. The predicate value selected by the predicate circuitry is transmitted to the second stage.

Abstract: One embodiment of the present invention provides a system that avoids write-after-write (WAW) hazards while speculatively executing instructions. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint, defers the instruction, and executes subsequent instructions in an execute-ahead mode. During this execute-ahead mode, instructions that cannot be executed because of unresolved data dependencies are deferred, and other non-deferred instructions are executed in program order. If an unresolved data dependency is resolved during the execute-ahead mode, the system moves into a deferred mode wherein the system executes deferred instructions.

Abstract: A processing unit of the invention has multiple instruction pipelines for processing multi-threaded instructions. Each thread may have an urgency associated with its program instructions. The processing unit has a thread switch controller to monitor processing of instructions through the various pipelines. The thread controller also controls switch events to move from one thread to another within the pipelines. The controller may modify the urgency of any thread such as by issuing an additional instruction. The thread controller preferably utilizes certain heuristics in making switch event decisions. A time slice expiration unit may also monitor expiration of threads for a given time slice.

Abstract: The processing of instructions from multiple threads using a shared dispatch pipeline is controlled by invoking a dispatch flush operation wherein instructions of a selected thread in the shared dispatch pipeline are flushed in response to resource requirements. An exception condition detected in one thread can be resolved by issuing a following instruction for that thread. Until the exception condition is resolved, resources are not released that allow the second thread to dispatch which in turn prevents dispatch from the first thread to resolve the exception condition. A flush of the first thread is not issued to resolve the stall. Instead, a dispatch flush of the second thread is issued. If a second thread instruction has long latency resource requirements that prevent the first thread from dispatching to resolve the exception, then a hold is issued controlling when the second thread instruction is refetched.