Abstract: Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric layers. Such embodiments include forming metal-containing dielectric layers over a silicon-containing substrate where a metal-containing layer is first formed and that treated to form a dielectric layer. Dielectric layers formed by methods of the present invention have a dielectric constant greater than that of silicon dioxide, and can have an equivalent oxide thickness of less than 2 nanometers. Such dielectric layers are useful in the forming of a variety of semiconductor devices such as transistors, capacitors and the like where such devices and integrated circuits formed from such devices are encompassed by embodiments in accordance with the present invention.

Abstract: A method of forming a gate oxide film for high voltage region of semiconductor devices includes forming patterns on a semiconductor substrate having a high voltage region, thereby exposing only a gate oxide film formation region for high voltage, forming a metal oxidization layer on the entire surface, and performing a process of removing the patterns, thereby forming the metal oxidization layer only in the gate oxide film formation region for high voltage.

Abstract: Methods for stabilizing a threshold voltage in an NMOS transistor are disclosed. A disclosed method comprises: forming a gate electrode on an active region in a substrate of a first conductive type; implanting ions of a second conductive type into the active region to form LDD regions; forming spacers on the sidewalls of the gate electrode; implanting ions of the second conductive type into the active region to form second source/drain regions; implanting halo ions into the active region; activating ions in the source/drain regions by conducting a first thermal process; and moving the halo ions toward the surface of the channel under the gate electrode by conducting a second thermal process.

Abstract: Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.

Abstract: A method for fabricating a capacitor in a semiconductor device is disclosed.

Abstract: A method of fabricating an MIM capacitor is provided, by which higher capacitance can be secured per unit volume or area by forming a dual-stack type capacitor to increase an effective area of the capacitor. The method includes patterning a first metal layer, forming a planarized second insulating layer having a trench exposing a portion of the patterned first metal layer, forming a second metal layer within the trench, forming a first dielectric layer on the second metal layer, forming first via holes exposing the patterned first metal layer, forming first plugs filling the trench and first via holes, forming a third metal layer thereover, forming a second dielectric layer on the third metal layer, forming a patterned fourth metal layer on the second dielectric layer, patterning the second dielectric layer and the third metal layer, forming a planarized third insulating layer having second via holes therein, and forming a patterned fifth metal layer on the third insulating layer.

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a semiconductor device. At least one thin conductive material layer is disposed within the material of the metallization layer to reduce the surface roughness of the metallization layer, thus improving the reliability of the MIM capacitor. The thin conductive material layer may comprise TiN, TaN, or WN and may alternatively comprise a barrier layer disposed over or under the TiN, TaN, or WN. One plate of the MIM capacitor is patterned using the same mask that is used to pattern conductive lines in a metallization layer, thus reducing the number of masks that are required to manufacture the MIM capacitor.

Abstract: Disclosed are a semiconductor wafer, a semiconductor device, and a method of manufacturing the semiconductor device, which are capable of easily carrying out an alignment between a semiconductor substrate and an electron beam exposure apparatus.

Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of layered high permeability shielding lines are formed on the first layer of insulating material. The pair of layered high permeability shielding lines include layered permalloy and/or Ni45Fe55 films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of layered high permeability shielding lines.

Abstract: Disclosed herein is a method of forming an element isolation film of a semiconductor device. An aluminum oxide film of a high wet etch rate is used as a pad oxide film, a trench is formed, and top and bottom edges of the trench is made rounded while removing some of the aluminum oxide film by a cleaning process. It is thus possible to make the top and bottom edges of the trench rounded without using polymer. It is also possible to minimize generation of a moat due to a step between a field region and an active region in a cleaning process before a gate oxide film is formed.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on the NMOS side, for stack etch, channel-stop implant, and silicon recess etch (optional); the other masking step is exactly complementary, and performs the analogous operations on the PMOS side. After these two steps are performed (in either order), an additional nitride layer can optionally be deposited and etched to cover the sidewall of the active stack. Field oxide is then formed, and processing then proceeds in conventional fashion.

Abstract: A method for bonding semiconductor structures together is described. The technique includes providing a bonding surface on each of two semiconductor structures, brushing a bonding surface of at least one of the structures to remove contaminants and to activate hydroxyl groups on the bonding surface to enhance hydrophilicity and to facilitate molecular bonding of the structures, and joining the bonding surfaces together by molecular bonding to form a composite structure.

Abstract: A method is provided for fabricating a substrate for optics, electronics, or opto-electronics. This method includes the steps of implanting atomic species into a face of a source substrate to form a weakened zone therein corresponding to the depth of penetration of the atomic species; transferring the seed layer on to a support substrate by bonding a face of the support substrate to the face of the source substrate and detaching the seed layer from the source substrate; depositing a working layer on the seed layer to form a composite substrate comprising the support substrate, seed layer and working layer; and detaching the seed layer and the working layer from the support substrate to form a substrate. Advantageously, the support substrate comprises a material having a thermal expansion value of about 0.

Abstract: An electrode insulator and method for fabricating the same, wherein a T-shape electrode insulator made of inorganic dielectric material is fabricated perpendicular to the first electrode formed on the substrate, and insulating the second electrode from the first electrode. Inorganic films are used twice to form the insulator, and the T-shaped insulator fabricated is composed of two parts, the lower part is a column of ridge and the upper part is a horizontal cover to form an overhanging portion. Thereby, the overhanging portion can prevent metal film of the second electrode from forming between two insulators, so that the insulation can be achieved.

Abstract: The invention relates to a method for creating a pattern on a substrate comprising a first alignment structure, using an elastomeric stamp comprising a patterning structure and a second alignment structure. The method comprises a moving step for moving the elastomeric stamp towards the substrate, and a deformation step for deforming the patterning structure with a tensile or compressive force generated by cooperation of the first alignment structure and the second alignment structure.

Abstract: A process for producing semiconductor chips having a protective film on the back surface includes the steps of: providing a sheet to form the protective film having a release sheet and a protective film-forming layer formed on a detachable surface of the release sheet, wherein the protective film-forming layer includes a thermosetting component, an energy ray-curable component and a binder polymer component; adhering a protective film-forming layer of the sheet to form the protective film onto a back surface of a semiconductor wafer having circuits on its surface; curing the protective film-forming layer by irradiation with an energy ray, and thereafter, further conducting the additional steps of (in any order): detaching the release sheet from the protective film-forming layer; further curing the protective film-forming layer by heating; and dicing the semiconductor wafer together with the protective film-forming layer with respect to each circuit.

Abstract: A method of fabrication a polysilicon layer is provided. A substrate is provided and then a buffer layer having a plurality of trenches thereon is formed over the substrate. Thereafter, an amorphous silicon layer is formed over the buffer layer. Finally, a laser annealing process is conducted so that the amorphous silicon layer melts and crystallizes into a polysilicon layer starting from the upper reach of the trenches. This invention can be applied to fabricate the polysilicon layer of a low temperature polysilicon thin film transistor liquid crystal display such that the crystals inside the polysilicon layer are uniformly distributed and have a larger average size.

Abstract: A method for forming a semiconductor device includes placing a Si substrate and an Sc2O3 powder source in an oxide chamber, and vaporizing the Sc2O3 powder source in the oxide chamber so as to form a single crystal Sc2O3 film on the Si substrate through electron beam evaporation techniques.

Abstract: FinFET devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and methods for producing the same. The methods involve dopant implants into the insulator layer, thereby creating borophosphosilicate glass (BPSG) diffusion sources within the insulation layer underlying the active regions of the SOI wafer. Backend high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the active regions, thereby forming a retrograde dopant profile extending towards the channel region. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.

Abstract: A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface side opposite to the insulator, and a second gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is substantially uniform and an n-type dopant of a concentration of above 6×1020 atoms/cm3 is contained.

Abstract: A semiconductor device is provided, which aims to reduce the standby power thereof by reducing the leak between a body and a drain with restraining the effect on a threshold voltage, in order to actualize the highly reliable semiconductor device. When extension regions are formed, an n-type impurity less diffusive than phosphorus (P+), for example, arsenic (As+) is used as an impurity. In addition to ordinary ion implantation with high dose (high concentration) and low acceleration energy, As+ ions are implanted with low dose and high acceleration energy.

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate, forming an insulating layer over the semiconductor substrate, forming a conductive layer over the insulating layer, forming a first metal silicide layer over the conductive layer, patterning the conductive layer to form a patterned first layer, wherein the patterned first layer is a part of a control electrode, patterning the first metal silicide layer to form a patterned first metal silicide layer over the control electrode so that the patterned first metal silicide layer remains over the control electrode, and forming a second metal silicide over the patterned metal silicide layer, wherein the second metal silicide layer has a thickness greater than the thickness of first metal silicide layer.

Abstract: A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon layer formed on a gate dielectric layer over a substrate. Etching the second silicon layer is stopped at the etch stop oxide layer. A spacer structure is formed about the interim gate electrode stack, and then the top silicon portion and the sandwiched oxide portion are removed. The spacer structure height may be reduced. A metal layer is formed over the bottom silicon portion of the interim gate electrode stack and over source and drain regions of the substrate, all of which are silicided at the same time to form a fully silicided (FUSI) gate electrode and silicided source and drain regions.

Abstract: A semiconductor fabrication process includes forming a gate stack overlying semiconductor substrate. Source/drain regions are formed in the substrate laterally aligned to the gate stack. A hard mask is formed overlying a gate electrode of the gate stack. A first silicide is then formed selectively over the source/drain regions. After removing the hard mask, a second silicide is selectively formed on the gate electrode. The first silicide and the second silicide are different. Forming the gate stack may include forming a gate dielectric on the semiconductor substrate and a polysilicon gate electrode on the gate dielectric. The gate electrode may have a line width of less than 40 nm. Forming the second silicide may include forming nickel silicide in upper portions of the gate electrode.

Abstract: A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold.

Abstract: Nanowire fluid sensors are provided. The fluid sensors comprise a first electrode, a second electrode, and at least one nanowire between the first electrode and the second electrode. Each nanowire is connected at a first end to the first electrode and at a second end to the second electrode. Methods of fabricating and operating the fluid sensor are also provided.

Abstract: Disclosed is a method of manufacturing a semiconductor device, including the steps of: forming on a second insulating film a first resist pattern having a first window; employing the first resist pattern as an etching mask to form first openings exposed from contact regions CR; forming, on a second conductive film, a second resist pattern having first resist portions; employing the second resist pattern as an etching mask to form first and second conductors, a floating gate and a control gate; forming a third resist pattern in regions I, II and III; and employing the third resist pattern as an etching mask to remove the portions of the second conductors under second windows.

Abstract: The present invention is directed to a multi-layer interconnection circuit module in which plural unit wiring layers are interlayer-connected to each other through a large number of via holes so that they are laminated and formed, wherein respective unit wiring layers (8) to (12) are adapted so that photo-lithographic processing is implemented to a first insulating layer (22) formed by photosensitive insulating resin material to form via hole grooves (25), and photo-lithographic processing is implemented to a second insulating layer (23) formed by photosensitive insulating resin material on the first insulating layer (22) to form wiring grooves (27).

Abstract: A polymer spacer material may increase the dimensions of the patterned photoresist that is used as a mask to etch the layers below the photoresist, which in turn translates into smaller dimensions etched into the underlying materials. This allows for the formation of integrated circuits having smaller features, smaller overall size, and greater density of features. In particular, the use of a polymer spacer material allows for the formation of contacts within flash memory cells having decreased dimensions so that higher density flash memory cells may be created without causing shorts between contacts or shorts due to misalignment of the contacts. Additionally, the use of the polymer spacer material extends the use of photolithography technologies that are used to form the patterns into the photoresists.

Abstract: A method of fabricating a semiconductor device. The method comprises creating a via in a dielectric layer that is formed on a substrate, filling the via, and optionally, the surface of the dielectric layer with a sacrificial material, patterning a first photoresist layer on the sacrificial material to define a trench for the semiconductor device, removing the first photoresist layer without affecting the sacrificial material, repatterning a second photoresist layer on the sacrificial material to define the trench for the semiconductor device, forming the trench, and removing the second photoresist layer and the sacrificial material completely after the trench is formed.

Abstract: Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line.

Abstract: A silicidation blocking layer (SBL) pattern is formed on a substrate including an active region and a field region. The SBL pattern covers the field region and exposes the active region. A silicide layer is formed on the active region by reacting metal with silicon existing in the active region. An insulation layer is formed on the substrate including the silicide layer. An opening exposing the silicide layer is formed by selectively etching the insulation layer under a condition having an etching selectivity between the SBL and the insulation layer. Conductive material is filled up the opening. The field region of a substrate is sufficiently protected by the SBL pattern without any additional process so that the failure of a semiconductor device is effectively prevented because the flow of a leakage current through the field region is blocked.

Abstract: An atomic layer deposition method is used to deposit a TiN or TiSiN film having a thickness of about 50 nm or less on a substrat. A titanium precursor which is tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or Ti{OCH(CH3)2}4 avoids halide contamination from a titanium halide precursor and is safer to handle than a titanium nitrate. After a monolayer of the titanium precursor is deposited on a substrate, a nitrogen containing reactant is introduced to form a TiN monolayer which is followed by a second purge. For TiSiN, a silicon source gas is fed into the process chamber after the TiN monolayer formation. The process is repeated several times to produce a composite layer comprised of a plurality of monolayers that fills a contact hole. The ALD method is cost effective and affords an interconnect with lower impurity levels and better step coverage than conventional PECVD or CVD processes.

Abstract: The method of the invention comprises accumulating experimental data or obtaining existing data with regard to the optimal time-temperature relationship of the deposition process on various film-formation stages for various materials, forming nuclei of a selected material on the surface of the treated object in the first stage under first temperature-controlled conditions for the formation of nuclei of said selected material, converting the nuclei of the aforementioned selected material into island-structured deposited layer of said material by causing lateral growth of the nuclei under second temperature-controlled conditions; converting the island-structure layer into a continuously interconnected cluster structure by causing further lateral growth of said island-structured deposited layer under third temperature-controlled conditions; forming a first continuous film of said material under fourth temperature controlled conditions which provides said first continuous film with predetermined properties; and t

Abstract: A process to deposit a thin film by chemical vapor deposition includes evacuating a chamber of gases; exposing a device to a gaseous first reactant, wherein the first reactant deposits on the device to form the thin film having a plurality of monolayers in thickness; evacuating the chamber of gases; exposing the device, coated with the first reactant, to a gaseous second reactant under a plasma treatment, wherein the thin film is treated by the first reactant; and repeating the previous steps.

Abstract: Provided is a method of manufacturing a semiconductor device with enhanced electrical characteristics. The method includes disposing a substrate on a substrate support in a process chamber, pre-heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 60 seconds or more, forming a silicon protective layer on the substrate by supplying a silicon source gas into the process chamber and heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 10 seconds or more, and forming a tungsten layer on the silicon protective layer.

Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to a first reducing gas and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method may further provide exposing the substrate to a deposition gas comprising a second reducing gas and the tungsten precursor gas to form a tungsten bulk layer on the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples include that the ALD and CVD processes are conducted in the same deposition chamber or in different deposition chambers.

Abstract: A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.

Abstract: Chemical-mechanical planarization (CMP) apparatus and methods for detecting polishing pad properties using ultrasonic imaging is presented. An ultrasonic probe assembly transmits ultrasonic signals onto the surface of a polishing pad during a CMP process. Reflected ultrasonic signals are collected and analyzed to monitor polishing pad properties in real-time. This allows CMP process adjustments to be made during the CMP process.

Abstract: The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and an unlanded portion located along at least a portion of a lateral edge of the metal line. The unlanded portion is at least partially filled with a polymer, and the landed portion is substantially filled with a conductive material. A method for manufacturing the interconnect is also provided.

Abstract: A method of manufacturing a semiconductor device comprises preparing a working film to be processed, forming an adhesion improving region on the working film for increasing an adhesion between the working film and a mask material containing carbon, forming the mask material on the working film, forming a resist pattern on the mask material, the mask material having a higher etching resistance for the working film than the resist pattern, transferring the pattern of the resist pattern onto the mask material, and etching the working film by using the mask material as a mask.

Abstract: A method of manufacturing a spacer for a substrate having a gate structure formed thereon. The method comprises steps of forming a first oxide layer over the substrate and forming a nitride layer on the first oxide layer. A first asymmetric etching process is performed to remove a portion of the nitride layer until a portion of a top surface of the first oxide layer is exposed. A second asymmetric etching process is performed to remove a portion of the first oxide layer by using the remaining nitride layer as a mask until about 50% to 90% portion of the first oxide layer is removed. A quick wet etching process is performed to remove a portion of the remaining first oxide located on the top of the gate structure and on the substrate.

Abstract: In one embodiment of the invention, a method for finishing or treating a silicon-containing surface is provided which includes removing contaminants and/or smoothing the surface contained on the surface by a slow etch process (e.g., about <100 ?/min). The silicon-containing surface is exposed to an etching gas that contains an etchant, a silicon source and a carrier gas. Preferably, the etchant is chlorine gas so that a relatively low temperature (e.g., <800° C.) is used during etching or smoothing processes. In another embodiment of the invention, a method for etching a silicon-containing surface during a fast etch process (e.g., about >100 ?/min) is provided which includes removing silicon-containing material to form a recess in a source/drain (S/D) area on the substrate. The silicon-containing surface is exposed to an etching gas that contains an etchant, preferably chlorine, a carrier gas and an optional silicon source.

Abstract: One embodiment of a method for forming a low-k dielectric for a semiconductor device assembly comprises forming a silicon dioxide layer, then forming a patterned masking layer such as silicon nitride on the silicon dioxide. Using the patterned nitride layer as a pattern, the silicon dioxide is etched to form a plurality of hemispherical microcavities in the silicon dioxide. Openings in the patterned nitride are filled, then another layer is formed over the silicon nitride layer using the silicon nitride as a support over the microcavities. An inventive structure resulting from the method is also described.

Abstract: An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are provided. In one embodiment, the cleaning composition combines a solvent, a cleaning agent such as a hydroxycarboxylic acid or salt thereof, and at least one antimicrobial agent resulting in a cleaning composition in which microbial growth is inhibited. Examples of suitable antimicrobial agents include a benzoic acid or salt such as potassium or ammonium benzoate, and sorbic acid or salt such as potassium sorbate. The composition is useful for cleaning a wafer and particularly for removing residual particles after a conductive layer has been planarized to a dielectric layer under the conductive layer in a chemical mechanical planarization of a semiconductor wafer with abrasive slurry particles, particularly after a CMP of copper or aluminum films.

Abstract: The present invention relates to methods of making oxide layers, preferably ultrathin oxide layers, with a high level of uniformity. One such method includes the steps of forming a substantially saturated or saturated oxide layer directly or indirectly on a semiconductor surface of a semiconductor substrate, and etchingly reducing the thickness of the substantially saturated or saturated oxide layer by an amount such that the etched oxide layer has a thickness less than the substantially saturated or saturated oxide layer. In certain embodiments, methods of the present invention provide etched oxide layers with a uniformity of less than about +/?10%. The present invention also relates to microelectronic devices including made by methods of the present invention and manufacturing systems for carrying out methods of the present invention.

Abstract: A high density plasma chemical vapor deposition (HDPCVD) process is disclosed. First, a first deposition step is performed on a wafer. Then, the wafer is rotated with an angle. A second deposition step is performed for completing the deposition. By the rotation of the wafer, the thin film is formed with a desired uniformity.

Abstract: The invention includes selective oxidation methods and transistor fabrication methods. In one implementation, a selective oxidation method includes positioning a substrate within a chamber. The substrate has first and second different oxidizable materials. The substrate is therein exposed to a gas mixture comprising an oxidizer and a reducer under conditions effective to selectively grow an oxide layer on the first material relative to the second material. The oxidizer oxidizes the first and second materials under the conditions. The reducer reduces oxidized second material under the conditions back to the second material. After selectively growing the oxide layer on the first material relative to the second material, partial pressure of the oxidizer and the reducer is reduced within the chamber by flowing an inert gas to the chamber while chamber pressure and chamber temperature are at or above those of the conditions during the exposing. Other aspects and implementations are contemplated.