Abstract: A light source unit includes: a light source board mounted with a light source; a case that houses the light source board; and a holding member that is disposed integrally with an inner wall of the case, and hold the light source board with the case.

Abstract: A resonant switching power source apparatus has a first switching element and second switching element being connected in series between output terminals of a DC power source and are alternately turned on and off; a series resonant circuit having a primary winding of a transformer and a current resonance capacitor and connected in parallel with the second switching element; a controller to control the first and second switching elements; a rectifying/smoothing circuit to rectify and smooth a voltage, which is generated on a secondary winding of the transformer during an ON period of the second switching element, and output the rectified-smoothed voltage; a current detector to detect a current passing through the series resonant circuit; and an overcurrent protector to turn off the first and second switching elements for a predetermined period so that excitation energy of the transformer is reset, if the current detector detects a predetermined current value.

Abstract: Control loop ripple voltage in an error amplifier may be the result of a non-linear time varying behavior of a switch mode power conversion process. An inverse waveform replica of the error amplifier control loop ripple voltage waveform may be generated to substantially cancel the non-linear loop dynamics introduced by the control loop ripple voltage. Once the control loop ripple voltage is substantially cancelled the bandwidth of the DC-to-DC converter control loop may be increased for faster loop response thus reducing the need for additional output filter capacitance.

Abstract: A digital pulse width modulation (DPWM) controlling system for controlling a load of an application circuit with a DPWM unit is provided, which comprises a comparator and a micro-control unit, the comparator receiving a sense signal detected from the load and a reference signal and comparing the sense signal and the reference signal to output an analog comparison signal, and the micro-control unit generating a trigger signal having a minimum pulse width and receiving the analog comparison signal to output a DPWM signal, wherein the micro-control unit adjusts the minimum pulse width of the trigger signal to obtain a pulse width of the DPWM signal in response to the analog comparison signal whenever the sense signal is within a stable duration so as to output the DPWM signal to the application circuit to control the load.

Abstract: A power supply includes an input, an output, a reverse current protection circuit, a synchronous rectifier and an output choke. The reverse current protection circuit is configured for detecting a flyback voltage indicative of reverse current, and for deactivating the synchronous rectifier in response to detecting the flyback voltage. The flyback voltage can be detected a variety of ways, including across the output choke, across a switch in the synchronous rectifier, across the secondary winding of a power transformer, etc.

Abstract: A capacitor multiplier including a capacitor, a first voltage follower, a first impedance element, and a second impedance element is provided. The input terminal of the first voltage follower is electrically connected to the first terminal of the capacitor. Wherein, the voltage level of the output terminal of the first voltage follower changes along with the voltage level of the input terminal thereof. The first terminal of the first impedance element is electrically connected to the first terminal of the second impedance element. The second terminal of the first impedance element is electrically connected to the first terminal of the capacitor. The second terminal of the second impedance element is electrically connected to the output terminal of the first voltage follower.

Abstract: In an inverter circuit including switching devices and diodes connected in parallel with the switching devices which are provided in pairs of upper and lower arms, and also including resistances for detecting phase currents in a motor connected to the lower arms, during dead time periods when both a switching device in an upper arm and a switching device in a lower arm are off, a voltage across a phase-current detection resistance induced by a phase current flowing through a diode is sampled.

Abstract: A control device calculates a voltage command value of a voltage step-up converter based on a torque command value and a motor revolution number and calculates an on-duty of an NPN transistor based on the calculated voltage command value and a DC voltage from a voltage sensor. When the on-duty is influenced by a dead time of NPN transistors, control device fixes the on-duty at 1.0 to control the NPN transistors in such a manner that the voltage is increased or decreased.

Abstract: One of a plurality of voltages is adapted to be applied to power supply terminals (2a, 2b, 2c). A rectifying circuit (6) rectifies the applied voltage and develops a rectified voltage between the output terminals (6a, 6b) thereof. Inverters (16a, 16b) are connected into one of a plurality of inverter connections between the rectifier output terminals (6a, 6b) in response to one of a plurality of inverter connection indicative signals. The inverter connections are set to correspond to respective ones of the plurality of voltages, so that a predetermined voltage can be applied to each inverter whichever one of the plurality of voltages is applied to the power supply terminals. An inverter connection indicative signal generating circuit (34) is manually operated to generate a desired one of the inverter connection indicative signals. A thyristor (8) is disposed between the rectifier output terminals (6a, 6b) and the inverters (16a, 16b).

Abstract: Resistive memory devices having at least one varistor and methods of operating the same are disclosed. The resistive memory device may include at least one bottom electrode line, at least one top electrode line crossing the at least one bottom electrode line, and at least one stack structure disposed at an intersection of the at least one top electrode line and the at least one bottom electrode line including a varistor and a data storage layer.

Abstract: In one embodiment, a CAM is provided that includes; a plurality of memory cells grouped to store a word, wherein the memory cells are organized into a plurality of ripple groups, each ripple group including a complex logic gate configured to determine whether a stored content for the ripple group's memory cells matches a corresponding portion of a comparand word if an enable input for the ripple group is asserted, each complex logic gate asserting an output if the determination indicates a match, the ripple groups being arranged from a first ripple group to a last ripple group such that the output from the first ripple group's complex logic gate functions as the enable input for a second ripple group's complex logic gate and so on such that an output from a next-to-last ripple group's complex logic gate functions as the enable input for the last ripple group's complex logic gate.

Abstract: A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors.

Abstract: A test module for testing the susceptibility of an integrated circuit design to latch-up, the test module comprising a plurality of test blocks (30), connected in parallel, each test block (30) comprising an injector block (12) for applying a stress current or voltage to the respective test block (30), and a plurality of sensor blocks (13) located at successively increasing distances from the respective injector block (12), each sensor block (13) comprising a PNPN latch-up test structure. The present invention combines the respective advantages of conventional IC stress current testing and latch-up parameter measurement using a standard PNPN latch-up test structure.

Abstract: The present invention discloses an inverter test device and a method thereof, which provides a single-load environment or a multi-load test environment to test electrical performance of an inverter or inverters, including: unbalanced current comparison, phase comparison, current/voltage deviation, and fusion heat (I2T), and record the test results, wherein the test method of the present invention is implemented with the procedures, which can be executed in a computer or a similar device to undertake control and data processing, and the electrical signals acquired by the inverter test device are processed, compared and calculated in order to realize the abovementioned tests of unbalanced current comparison, phase comparison, current/voltage deviation, and fusion heat (I2T).

Abstract: A memory includes a wafer having at least a first and second edge, at least one memory bank array, a data path, and a plurality of data pads. The data path is coupled to the memory bank array. The plurality of data pads are coupled to the data path and configured with the data path to bus data to and from the memory bank array. The data pads are further configured such that each of the data pads are located adjacent the first and second edges of the wafer. The memory component is configurable for alternative applications such that in a first application all of the data pads used to bus data are located only on the first edge of the wafer and such that in a second application at least one of the data pads used to bus data is located on the first edge of the wafer and at least one of the data pads used to bus data is located on the second edge of the wafer.

Abstract: In one embodiment, a content data management system that handles control information on management of content data decryption includes a first device (a recorder/player) for recording/reproducing the content data, a second device (a magnetic disk drive) for storing the content data, and a host processor for controlling data transfer between the first and second devices.

Abstract: A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.

Abstract: A nonvolatile semiconductor device is configured so that a load circuit applying voltage to a variable resistive element is provided electrically connecting in series to the variable resistive element, a load resistive characteristic of the load circuit can be switched between two different characteristics. The two load resistive characteristics are selectively switched depending on whether a resistive characteristic of the variable resistive element transits from low resistance state to high resistance state, or vice versa, voltage necessary for transition from one of the two resistive characteristics to the other is applied by applying writing voltage to a serial circuit of the variable resistive element and load circuit. After the resistive characteristic of the variable resistive element transits from one to the other, voltage applied to the variable resistive element does not allow a resistive characteristic to return from the other to one depending on the selected load resistive characteristic.

Abstract: An image sensor IC may have a non-volatile memory for several functions. The functions may include storing control parameters for a camera autofocus module, part tracking data, and data for defect correction or color science. The non-volatile memory can in particular be an antifuse non-volatile memory, which may not need special light shielding.

Abstract: A memory apparatus comprises a media, a tip adapted to write information to and read information from said media, a media movement mechanism attached to said media and configured to move said media in response to media control signals, and a capacitive sensor configured to detect an amount of relative movement of said media and said tip in at least an x-axis direction. The capacitive sensor includes a fixed comb having fingers protruding in an x-axis direction, a moving comb connected having fingers protruding in an x-axis direction, and an electrical path connected to said fixed comb and an electrical path connected to said moving comb. The relative movement in at least the x-axis direction is determined at least in part on a change in capacitance between said fixed and moving combs of said capacitive sensor.

Abstract: An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

Abstract: Apparatus and methods for reducing single-event upsets (SEUs) in latch-based circuitry (e.g., static random access memory (SRAM) cells) and other digital circuitry. According to an exemplary embodiment, a latch-based circuit includes a radiation-hardened latch having first and second cross-coupled inverters and first and second programmable resistance devices (PRDs). The first PRD is coupled between the output of the first inverter and the input of the second inverter. The second PRD is coupled between the output of the second inverter and the input of the first inverter. The PRDs may be programmed to low or high-resistance states. When SET to a low-resistance state, the latch of the latch-based circuitry may be accessed to read the current logic state stored by the latch or to write a new logic state into the latch. When RESET to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from generating SEUs.

Abstract: Asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl). Furthermore the invention relates to a random access memory comprising a plurality of such asymmetrical random access memory cells and to a method to operate such a random access memory.

Abstract: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Abstract: A magnetic memory device includes a plurality of transistors (316, 317) formed on a substrate and a common magnetic memory block (312) including multiple effective magnetoresistive elements (318, 319), a ferromagnetic recording (321), a non-magnetic space (323), and a free magnetic reading (322) layer formed above the transistors (316, 317). An extended common digital line (315) is located above the common magnetic memory block (312). The common magnetic memory block (312) is electrically connected with a respective source/drain electrode of the transistors (316, 317) through each a contact at a respective active area. The specific magnetization state of the ferromagnetic recording layer at the active areas can be changed by a heating process and applying an external field induced from the common digital line (315) and the bit (309, 311) or word (307) or word (307) lines.

Abstract: The present invention provides an array (20) of magnetoresistive memory elements (10) provided with at least one data retention indicator device (50). The at least one data retention indicator device (50) comprises a first magnetic element (51) and a second magnetic element (52) each having a pre-set magnetisation direction, the pre-set magnetisation direction of the first and second magnetic elements (51, 52) being different from each other. The first and second magnetic elements (51, 52) are suitable for aligning their magnetisation direction with magnetic field lines of an externally applied magnetic field exceeding a detection threshold value. According to the present invention, a parameter of the at least one data retention indicator device (50) is chosen so as to set the detection threshold value of the externally applied magnetic field to be detected.

Abstract: An MRAM circuit includes an MRAM array having a plurality of operational MRAM elements and a reference cell made up of one or more reference MRAM elements. A plurality of program lines within a first region are cladded with a flux-concentrating layer configured to focus a generated magnetic field while the portions of the program lines within a second region are uncladded so that the generated magnetic field is unfocused. Generally, the first region is associated with the operational MRAM elements and the second region is associated with the reference cell.

Abstract: A composite plug 104 is formed, and both a first plug (TiN) 106 and a second plug (W) 108 are disposed in one contact hole; the first plug (TiN) 106 functions as a heater electrode and the second plug (W) 108 functions as a contact plug. This eliminates the need to stack the heater electrode on the contact plug. The resistivities R11 and R12 of the first and second plugs of the composite plug 104 are in a relationship R11>R12.

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: A test interface receives a test command designating execution of a test for a memory cell. The test storage circuit stores test information necessary to execute the test. The test storage circuit includes an erasable programmable storage unit. The decoder decodes the test command input to the test interface, and selects the test information stored in the test storage circuit. The sense amplifier reads out, from the test storage circuit, the test information selected by the decoder. The holding circuit holds the test information read out by the sense amplifier. The control circuit controls a test operation of checking whether the memory cell normally operates, on the basis of the test information held in the holding circuit. The defect storage circuit is formed for the memory cell, and stores fail information indicating that the memory cell is defective if the memory cell does not normally operate in the test operation.

Abstract: A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug.

Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.

Abstract: A Flash memory system is implemented in a system-in-package (SIP) enclosure, the system comprising a Flash memory controller and a plurality Flash memory devices. An SIP relates to a single package or module comprising a number of integrated circuits (chips). The Flash memory controller is configured to interface with an external system and a plurality of memory devices within the SIP. The memory devices are configured in a daisy chain cascade arrangement, controlled by the Flash memory controller through commands transmitted through the daisy chain cascade.

Abstract: A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.

Abstract: A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line selection and biasing.

Abstract: In a nonvolatile memory cell having a trap layer, by executing first charge injection with a given wait time being secured and second charge injection after the first charge injection in a programming or erasing sequence, surrounding charge that may deteriorate the data retention characteristic is reduced utilizing an initial variation (charge loss phenomenon caused by binding of injected charge with the surrounding charge in an extremely short time) occurring immediately after programming. Thereafter, the charge loss in the initial variation is compensated, so that the subsequent data retention characteristic is improved. The second charge injection is executed only when a predetermined determination level has been reached.

Abstract: Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling methods may be applied at the die level, package level, and/or board level.

Abstract: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

Abstract: A self timing write architecture for semiconductor memory and a method for providing the same are provided. The core region of the semiconductor memory comprises of a normal memory cell array and a dummy column. The dummy column comprises of two blocks—block A and block B. Block A is composed of a cluster of N dummy cells in which data is written during write operation. The remaining cells in the dummy column together form block B which is meant for providing load for the dummy bit line. During a write operation, a dummy word line is generated to enable dummy memory cells of block A. The dummy bit line is then made to travel half the number of rows in the normal memory array and then made to return back. A dummy data is then written in all the dummy cells in block A. Simultaneously, a normal memory cell is also accessed and actual data is written into it. As soon as the writing operation is complete, a W-reset signal is generated to indicate successful completion of write operation.

Abstract: A memory device for early stabilization and rapid increase of a power level after deep power down exit includes a deep power down exit pulse generator, a deep power down exit mode signal generator, a current driving unit, a controller and a voltage generator. The deep power down exit pulse generator generates a deep power down exit pulse signal having a predetermined pulse width in response to a deep power down command. The deep power down exit mode signal generator generates a deep power down exit mode bias signal in response to the deep power down exit pulse signal. The current driving unit generates a deep power down exit mode reference voltage in response to the deep power down exit mode bias signal and a reference signal. The controller generates an enable signal in response to the deep power down exit mode bias signal or an active command.

Abstract: A repair I/O fuse circuit of a semiconductor memory device includes a reduced by as much as half layout area of fuses by replacing what one repair I/O information is represented by existing two I/O fuses with what one repair I/O information is represented by one I/O fuse. The repair I/O fuse circuit includes a plurality of I/O fuse circuits, each having one fuse. A repair signal indicates that there is an address to be replaced. If a chip enable signal is activated, each of the plurality of I/O fuse circuits outputs a repair I/O information signal depending on whether a fuse has been cut.

Abstract: The invention relates to a memory device comprising a non-volatile memory element, a read-out circuit for reading out an item of memory information stored in the memory element, a switching unit, by means of which a supply voltage can be applied to the read-out circuit, and a control unit, which has the capability of controlling the switching unit in a manner dependent on the memory information stored in the memory element.

Abstract: There is disclosed a semiconductor integrated circuit comprising a plurality of memory macros each including a redundancy cell, each of the memory macros being assigned with an address and transferred with data of a defect address of a semiconductor memory and store the data of the defect address, a plurality of non-volatile memory elements less in number than the plurality of memory macros, each of which stores redundancy data to be transferred to a memory macro and address data showing the memory macro as a transfer destination of the redundancy data in a form of set, and a transfer control circuit which transfers the redundancy data to the memory macro as the transfer destination from the non-volatile memory elements in accordance with the address data showing the memory macro as the transfer destination.

Abstract: A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.

Abstract: Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared by two or more devices under test. A chip selector may be used to select at least one or all the devices sharing a given set of test signals. By sharing test signals between multiple devices, the level of parallel testing may be increased without increasing the pin count and complexity of memory testers and probe cards.

Abstract: A semiconductor device for generating a test voltage for a wafer burn-in test and method thereof is disclosed. To generate the test voltage for a wafer burn-in test, a control signal may be generated in response to a supply voltage from an external wafer burn-in test device. A supplementary voltage may be generated in response to the control signal by using an internal voltage driving circuit. The test voltage may be generated by combining the supply voltage and the supplementary voltage.

Abstract: An internally asymmetric method for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A semiconductor memory device includes: a cell array with electrically rewritable and non-volatile memory cells disposed at crossings between bit lines and word lines, which intersect with each other; a row decoder configured to drive the word lines; and a sense amplifier so coupled to a selected bit line as to compare a cell current with a reference current and sense data of a selected memory cell in the cell array, wherein bit line precharge is performed for a certain time prior to the sense amplifier activation in a data read mode while word line boost is performed in advance of the bit line precharge.

Abstract: A circuit for enabling a sense amplifier in a semiconductor memory device includes a delay unit for outputting the delayed sense amplifier enable signal as a sense amplifier enable delay signal after delaying a sense amplifier enable signal in response to a delay control signal; and a delay control unit for controlling an intensity of the delay control signal by receiving a reference signal having a temperature reduction dependent characteristic. The length of the sensing time can increase by adjusting the delay at the sense amplifier enable signal according to a temperature decrease when a memory cell is formed on a silicon on insulator, and the sense amplifier enabling circuit is formed on a bulk silicon layer. In addition, the enable time point in the sense amplifier can be smoothly adjusted, and the possibility of operation failure in the semiconductor memory device can be reduced by reducing the occurrence of the sensing failure at the sense amplifier.