Abstract: A system including a chassis operable to receive a plurality of physical application modules and a test port via which an external test device is communicatively coupled to the system. Each physical application module includes a module bridge interface and boundary-scan test functionality. The test port is communicatively coupled to each of a chassis bridge interface in the chassis. When the module bridge interface of each of the physical application modules is communicatively coupled to a respective one of the plurality of chassis bridge interfaces, the boundary-scan test functionality of the respective physical application module is communicatively coupled to the test port.

Abstract: A printed circuit board (PCB) is provided. The PCB has at least a first surface and a second surface. One or more pre-defined areas defined on the first surface have connection to or comprise a PCB plane for the location of one or more electrical components thereon in use. One or more test pads provided on the second surface allow electrical testing of said PCB and/or one or more electrical components located thereon. Two or more connectivity points are provided on the first surface in each of said pre-defined areas. The connectivity points are a spaced distance apart and are substantially electrically isolated from each other in a first condition. The connectivity points are capable of electrical connection in a second condition.

Abstract: The purpose of the present invention is to improve a detection accuracy of a pilot signal detection circuit. A pilot detection signal voltage is input to a differential amplifier circuit 16 and a reference voltage generated by a reference signal generation circuit 17 is input to a differential amplifier circuit 19. A pilot signal is compared with the reference voltage by the differential amplifier circuits 16 and 19. Output currents of the differential amplifier circuits 16 and 19 are converted into voltages by a current-to-voltage conversion circuit 21. And an input to the current-to-voltage conversion circuit 21 is fed back with a voltage proportionate with an offset voltage of the circuit and the offset voltage of the pilot signal detection circuit is cancelled.

Abstract: An apparatus for measuring the properties of FET by generating a pulse to be applied to gate G of FET and measuring the voltage dependent on the drain current flowing to FET in response to the pulse, comprising a pulse generator for generating a pulse; a directional element disposed behind pulse generator; and voltage measuring device for measuring voltage.

Abstract: Pixel units are disposed in a display region of a substrate, and scan lines and data lines are used to control the pixel units. Inner short ring includes a first segment, a second segment and a connecting segment connecting both segments. The gates and sources of the first and second active device connect with the first and second segments respectively, and the drains connect with the connecting segment. The gates and sources of part of the third active devices connect with the first segment, and the drains connect with the odd scan lines. The gates and sources of other third active devices connect with the second segment, and the drains connect with the even scan lines. The gates of the fourth active devices connect with connecting lines, and the sources connect with data testing lines, and the drains connect with the odd and even data lines respectively.

Abstract: A display device having a sensing unit includes a first substrate having a plurality of test spacers, and a second substrate having a plurality of sensing unit test lines facing the test spacers, respectively. The surface heights of the sensing unit test lines are different from each other. The heights of the test spacers are substantially the same. The second substrate further includes a plurality of height difference portions formed under the sensing unit test lines, and the number of height difference portions formed under the sensing unit test lines is different for different sensing unit test lines.

Abstract: A plasma display panel comprises a barrier rib, a substrate on which a scan electrode and a sustain electrode are displaced, a dielectric layer covering the scan electrode and the sustain electrode, a first protective layer covering the dielectric layer and a second protective layer covering the first protective layer, and having an area less than an area of the first protective layer.

Abstract: A control system and method of a semiconductor inspection system are disclosed, wherein the inspection can be conducted without reducing the reliability of measurement even in the case where the supply voltage drops. The control system has a controller, a power supply for a power on-off circuit constituting a switching regulator designed to maintain the output voltage against a supply voltage drop, and a supply voltage drop detector. In the case where a supply voltage drop is detected during the measurement, the measurement is automatically suspended, and after restoring the supply voltage, the measurement is automatically restarted.

Abstract: A quantum computer can only function stably if it can execute gates with extreme accuracy. “Topological protection” is a road to such accuracies. Quasi-particle interferometry is a tool for constructing topologically protected gates. Assuming the corrections of the Moore-Read Model for v=5/2's FQHE (Nucl. Phys. B 360, 362 (1991)) we show how to manipulate the collective state of two e/4-charge anti-dots in order to switch said collective state from one carrying trivial SU(2) charge, |1>, to one carrying a fermionic SU(2) charge |?>. This is a NOT gate on the {|1>, |?>} qubit and is effected by braiding of an electrically charged quasi particle ? which carries an additional SU(2)-charge. Read-out is accomplished by ?-particle interferometry.

Abstract: A system and method for recovering a high frequency component of a slew rate controlled signal propagating along a transmission line enables the high frequency component to be recovered after being lost because of slew rate control and transmission line low pass filtering effects. The system includes a wave shaping circuit for receiving and shaping the slew rate controlled signal to recover the high frequency component. The method includes receiving the slew rate controlled signal, and recovering the high frequency component by shaping the slew rate controlled signal to produce a shaped signal, where the shaped signal includes the received slew rate controlled signal and the high frequency component.

Abstract: A driver circuit for a signal line of a large load is configured to include: a pMOS transistor having a source and a drain connected with a signal line and a ground line, respectively, and a gate receiving an input signal; and an nMOS transistor having a source and a drain connected with a signal line and a power supply line, respectively, and a gate receiving the input signal. As a result, the power consumption due to the signal line of a large load is reduced to realize a reduction of the power consumption of a semiconductor integrated circuit.

Abstract: A high voltage tolerant output buffer uses a substrate voltage control circuit to control the voltage at the substrate of the transistors in the output buffer. The circuitry of output buffer is such that the voltage between any two terminals of any of the transistors is not allowed to exceed the supply voltage of the output buffer. At the same time, the voltage at the source or drain of transistors of output buffer is not allowed to increase beyond its substrate voltage. The proposed circuit for output buffer can tolerate voltages higher than the voltage at which it is operated. The novel circuitry uses less hardware and prevents power dissipation in the circuit.

Abstract: The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.

Abstract: CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or ?processor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. Several frequency-adjusting techniques are presented which can be used in an distributed clock network environment which includes an array of oscillators. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of oscillators are described.

Abstract: A high voltage driver circuit for devices such as non-volatile memories, in which a low voltage driver is combined in two different ways with a high voltage driver In one, input-independent embodiment, a low voltage driver (Q7, Q8) is connected directly in parallel with a high voltage driver, thereby providing a high voltage signal path for high voltage operations and a low voltage signal path for low voltage operations. In an alternative, partially input-dependent embodiment, a low voltage driver is connected to the output of a high voltage driver (Q9, Q10), which may comprise a partial level shifter (Q 1 B Q6).

Abstract: A phase detector includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a first signal in response to a feedback signal and a clock signal. The second circuit is configured to provide a second signal in response to the clock signal and an inverted clock signal. The third circuit is configured to provide a third signal indicating whether the clock signal leads the feedback signal and a fourth signal indicating whether the feedback signal leads the clock signal in response to the first signal and the second signal.

Abstract: A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.

Abstract: Disclosed is an improved circuit and method for generating a power on reset signal, the circuit being a two-stage circuit comprising a delay-stage circuit and an output-stage circuit. The delay-stage circuit delays a time for a power on reset signal generated in the output-stage circuit changing from low to high, so that a power voltage having a low rising speed may be normally reset. Further, the two stages provide charging paths and discharging paths so that the power on reset signal may be prevented from changing from high to low when it has changed from low to high, when noises are presented on the power voltage.

Abstract: The low-power power-on reset circuit includes a NOT gate device, a time delay device, a wave shaping device and a NOR gate device, with which the present invention can provide a low power power-on reset circuit that can be formed by a complementary metal oxide semiconductor (CMOS), such that a lower power consumption and a higher noise margin can both be provided.

Abstract: An exemplary CPU frequency regulating circuit includes a detecting circuit, and a comparing circuit. The detecting circuit receives a PWM signal from a super I/O chipset, and converts the PWM signal to a load voltage responsive to a workload of a CPU. The comparing circuit is coupled to the detecting circuit for receiving the load voltage, and compares the load voltage with a reference voltage, and adjusts a frequency of the CPU according to a result of the comparison.

Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.

Abstract: A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having its gate terminal coupled to an inverted delayed control signal. A first and second pull down transistors are coupled in series between the first pull up transistor and a low voltage bias, wherein the gates of the first and second pull down transistors are coupled to the delayed control signal and inverted control signal, respectively. A third and fourth pull down transistors are coupled in series between the second pull up transistor and the low voltage bias. The gates of the third and fourth pull down transistors are coupled to a control signal and the inverted delayed control signal, respectively.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: Provided is a multi-phase clock generator which is not influenced by a mismatch and of which a maximum frequency is not limited. The multi-phase clock generator includes a first delay line, a second delay line, a phase detector, and an up/down counter. The first delay line generates a first clock signal by delaying an input clock for a first delay time. The second delay line generates a second clock signal by delaying the input clock for a second delay time in response to a control signal. The phase detector detects a phase difference between the first and second clock signals. The up/down counter generates the control signal in response to an output of the phase detector.

Abstract: A device is provided for transmitting electromagnetic signals between at least one first and at least one second functional unit, especially in the high frequency range. The device includes an electrically insulating substrate with a top and a bottom, a first electrically conductive layer of a first coating material on the bottom of the substrate, which layer can be connected to a reference voltage, and a second electrically conductive layer of a second coating material on the top of the substrate. The second electrically conductive layer can be, in at least one region, of fields of the second coating material that are spatially separated from one another and electrically insulated with respect to one another.

Abstract: An electronic system employing a clock signal correcting device is disclosed. One embodiment provides a leading edge delay device incrementing leading edges with respect to trailing edges, a trailing edge delay device incrementing trailing edges with respect to the leading edges, and a correction delay device delaying the leading edges of clock pulses if a leading edge incrementing step is greater than a trailing edge incrementing step and delaying the trailing edges of the clock pulses if the leading edge incrementing step is greater than the trailing edge incrementing step.

Abstract: There is provided a semiconductor device that operates at an internal clock based on a system clock and inputs/outputs data in synchronization with the internal clock. The semiconductor device includes a phase locked loop generating the internal clock and a switching element switching delay paths to be inserted into a feedback loop to the phase locked loop in accordance with data input/output in the semiconductor device.

Abstract: A signal transmitting circuit includes a driving circuit, and a plurality of receiving circuits receiving signals transmitted from the driving circuit. Each of the receiving circuits is coupled to the driving circuit consecutively via a transmission line. A filter means is coupled with a segment of the transmission line of two neighboring receiving circuits for filtering signal reflections from the receiving circuits.

Abstract: One embodiment of the present invention is directed to an apparatus for reducing errors affecting the intercept of a logarithmic device, the apparatus including a first switching device coupled to an input of the logarithmic device. The first switching device for switches the input of the logarithmic device between an input signal and a reference signal. The apparatus further includes a polarity switching device coupled to an output of the logarithmic device. The polarity switching device is configured to switch the polarity of an output signal of the logarithmic device when the logarithmic device is receiving one of the input signal and the reference signal. The apparatus further includes a low pass filter coupled to the polarity switching device.

Abstract: Mixer circuits with direct-current bias are disclosed. An example embodiment of such a mixer includes a first differential transistor pair and a second differential transistor pair. The example mixer also includes first and second local oscillator signal terminals and first and second mixed signal terminals. The first and second local oscillator signal terminals are coupled with the first and second differential transistor pairs. The first mixed signal terminal is coupled with the first differential pair and the second mixed signal terminal is coupled with the second differential pair. The mixer further includes first and second baseband signal terminals, where each baseband signal terminal is coupled with the first differential pair and the second differential pair. The mixer still further includes a first current source and a second current source.

Abstract: A circuit including a first sensitive node, a first component connected between the first sensitive node and a first terminal of a first switch, said first switch controlled by a first control signal variable between a supply voltage level and a second voltage level, and a second switch including a first terminal connected to the first terminal of said first switch, and a second terminal connected to a clean voltage supply, said second switch controlled to connect the first node of said first switch to said clean voltage supply when said first switch is in a non-conducting state.

Abstract: A gate-controlled switch configuration comprising a gate-controlled switch (V4) and a gate driver system (Ctrl, D1, D2, V1, V2), which in its first functional state is configured to change the amount of charge (Qgate) in the gate (G) of the gate-controlled switch (V4) to provide a normal turn-off functionality for the gate-controlled switch (V4), and in its second functional state it is configured to maintain the amount of charge (Qgate) in the gate (G) of the gate-controlled switch (V4) substantially constant. The gate driver system (Ctrl, D1, D2, V1, V2) is configured to produce a soft turn-off functionality during which the gate driver system (Ctrl, D1, D2, V1, V2) is in the first functional state a plural number of times, and between the subsequent first functional states it is in its second functional state.

Abstract: A switch including a first transistor including a first main terminal connected to a first switch node, a second main terminal connected to a second switch node and a control terminal, the second switch node being connected to a first clean voltage supply, and first control circuitry connected to the control terminal of the first transistor, including a first node connected to the first clean voltage supply, a second node connected to a second voltage level, and a control input node for receiving a first input control signal variable between a supply voltage level and a third voltage level, the first control means arranged to selectively connect the control terminal of the first transistor to one of the first node and the second node based on the first input control signal.

Abstract: A simple voltage detection circuit has few circuit elements, but provides a voltage output that is substantially temperature insensitive. The voltage detection circuit includes a diode-connected transistor, a cascode-connected transistor, as well as first and second resistors coupled between ground and a ramped power supply voltage. The diode-connected transistor exhibits a negative temperature coefficient. The on resistance of the cascode-connected transistor increases with temperature and thus the voltage dropped across the cascode-connected transistor also increases with temperature. By correctly sizing the cascode-connected device, the negative and positive temperature coefficients of the diode-connected and cascode-connected devices can be substantially cancelled out.

Abstract: A power supply controller including a MOSFET between a power source and a load, a ground terminal, a gate driving circuit structured to control a gate potential of the MOSFET to turn on power and control the gate potential of the MOSFET to turn off power based on a ground terminal potential, and a turn-off circuit structured to switch the MOSFET into a turn-off state regardless of control by the gate driving circuit when the ground terminal potential is at a higher value than a source potential of the MOSFET.

Abstract: A charge pump circuit includes capacitors and a number of forcing circuits for forcing the voltages on various nodes of the charge pump. The forcing circuits ensure that voltage differences across components thereof are up-limited in absolute value by a predetermined maximum voltage equal to a multiple of the absolute value of the difference between developed forcing voltages and lower than an absolute value of a charge pump voltage. The first and second forcing circuits ensure that the voltage differences across components in the forcing circuits are not higher than the predetermined maximum voltage when at least one among the voltages changes to a voltage higher in absolute value than said predetermined maximum voltage.

Abstract: A constant current output charge pump includes a switch module configured to compare a reference voltage with a load voltage and output a switch signal, a voltage margin control module configured to compare a first voltage and a second voltage with an output voltage and output a voltage margin control signal, a clock control module, a charge pump module, a current control module and a load module. The clock control module is configured to capture the switch signal and the voltage margin control signal and output a first clock signal and a second clock signal according to a system to the charge pump module for charging the input voltage.

Abstract: A chopper-stabilized amplifier receiving an input signal includes a first operational transconductance amplifier having an input chopper and an output chopper for chopping an output signal produced by the first operational transconductance amplifier. A switched capacitor notch filter filters the chopped output signal by operating synchronously with the chopping frequency of output chopper to filter ripple voltages that otherwise would be produced by the output chopper. In one embodiment, a second operational transconductance amplifier amplifies the notch filter output. The input signal is fed forward, summed with the output of the second operational transconductance amplifier, and applied to the input of a fourth operational transconductance amplifier. Ripple noise and offset are substantially reduced.

Abstract: The present invention provides a circuit that utilizes OP-sharing technique. The circuit includes an amplifier, a first application circuit, a second application circuit, and a reset circuit. The first application circuit drives the amplifier during at least a first working period. The second application circuit drives the amplifier during at least a second working period. The reset circuit resets the amplifier during at least a third working period. The third working period is between the first working period and the second working period.

Abstract: A multi-channel digital amplifier system to generate a pulse width modulation (PWM) signal having a different switching frequency in each channel, and a signal processing method thereof. The digital amplifier system includes a PWM conversion unit to convert a plurality of audio signals on a plurality of channels into low output power PWM signals having switching frequencies that are different from each other, a switching circuit unit to amplify the plurality of low output power PWM signals to a plurality of high power output PWM signals on the respective channels, and a filter unit to restore the plurality of high output power PWM signals to a plurality of analog audio signals on the respective channels.

Abstract: Systems and methods in which an ultrasonic signal is introduced into an audio signal before the audio signal is amplified by a switching amplifier. The added ultrasonic signal (e.g., a tone at half the amplifier's switching frequency) shifts the signals input to a set of power switches so that they do not switch nearly simultaneously. The ultrasonic signal causes the output current to be well defined to eliminate dead time distortion at low signal levels. Adding the tone ultrasonic signal causes the distortion to shift to an amplitude greater than zero. Signals that exceed this amplitude will experience the distortion, but the distortion will be less noticeable than in lower-amplitude signals. Signals that do not exceed this amplitude will not experience the distortion at all. Adding an ultrasonic signal may also draw energy away from the switch frequency and its harmonics to interference with AM radio reception.

Abstract: In a contactless IC card system, a modulating circuit manufactured in an IC form is operable at a high power efficiency. The demodulating apparatus is configured to include: first signal output means for outputting a first output signal having a predetermined phase with respect to that of an input signal, a second signal output means for outputting a second output signal having a predetermined phase with respect to that of the input signal, gate means for gating at least the second output signal, calculation means for adding, or subtracting the first output signal and the second output signal; and control means for controlling the operation of the gate means in response to a logic level of input data.

Abstract: A voltage regulator having an input voltage and adapted to supply a regulated output voltage, the regulator including an AB class amplifier and a power transistor having a non-drivable terminal coupled to the input voltage, a non-drivable terminal coupled to a reference voltage and a drivable terminal coupled to the output terminal of the amplifier; the amplifier is adapted to amplify the voltage difference between a further reference voltage and a fraction of the regulated voltage.

Abstract: In a differential-to-single-ended (D2S) converter having reduced power consumption and excellent duty ratio characteristics, and a phase-locked loop (PLL) circuit having the same, the D2S converter includes a differential amplifier and a latch circuit. The differential amplifier amplifies a differential input signal to generate a differential output signal. The latch circuit latches the differential output signal to generate a single output signal. A bias current of the differential amplifier may be determined according to a bias voltage proportional to a voltage which is provided to a delay cell of a voltage-controlled oscillator (VCO). The D2S converter may have reduced power consumption and excellent duty ratio characteristics, and the PLL circuit having the D2S converter may have a simple circuit configuration and less power consumption.

Abstract: This invention includes a gain control section 13 capable of changing an APC loop gain according to a power output level set in a power amplifier to allow suppression of variation in power output level when the power output level is low and suppression of occurrence of ringing when the power output level is high by making the loop gain high when the power output level is low and making the loop gain low when the power output level is high.

Abstract: A circuit includes at least two transistors arranged to form a current mirror, at least two transistors operatively coupled to the current mirror, where the transistors are arranged to form a differential pair amplifier, and a follower transistor operatively coupled to the current mirror and to the differential pair. The transistors of the differential pair, the current mirror, and the follower transistor are operatively coupled such that during operation an amplitude of a signal output from the follower transistor is proportional to an amplitude of an signal input into the differential pair.

Abstract: An amplifier circuit having an output delay that is selectively changed in accordance with a common mode voltage level. A replica delay circuit adapted for use within an internal clock generator include such an amplifier circuit. The amplifier circuit includes a first amplifier generating internal signal in response to input signals changes a common mode voltage level of the internal signals in response to control signals. The amplifier also includes a second amplifier comparing voltage levels of the internal signals, generating an output signal in accordance with a comparison result, and changing a duty cycle of the output signal when the common mode voltage level of the internal signals is changed.

Abstract: Low distortion is implemented even in a high input level, and a smooth change in gain is maintained. A first amplifier (10) with high gain and low noise that can be gain-controlled by a first gain control signal, and a second amplifier (20) with low gain and low distortion that can be gain-controlled by a second gain control signal are provided, and a third amplifier (30) is further coupled with an outputs of the first and the second amplifiers (10, 20). An input terminal of the first amplifier (10) and an input terminal of the second amplifier (20) are coupled with each other, and an output terminal of the first amplifier (10) and an output terminal of the second amplifier (20) are coupled with each other. The output of the first amplifier (10) is then turned on or off by a mode switching signal. A change in gain resulting from turning on and off the first amplifier (10) is corrected by the third amplifier (30).

Abstract: A noise removing apparatus and method usable in a portable recorder to remove noise and enhance a voice signal when the voice signal with noise is input to the portable recorder. The noise removing method includes dividing an input signal into a high frequency component signal and a low frequency component signal, adjusting a magnitude of the high frequency component signal by comparing the magnitude of the divided high frequency component signal and a magnitude of the low frequency component signal, enhancing a clearness of the low frequency component signal by filtering the divided low frequency component with an adaptive filter, and adding the magnitude-adjusted high frequency component signal and the clearness-enhanced low frequency component signal.

Abstract: A differential amplifier receives a differential input signal and generates an output signal at an output node. An auxiliary circuit coupled to the differential amplifier operates to improve slew rate response. In quiescent and small signal situations with respect to the differential input signal, the auxiliary circuit does not alter or change operation of the differential amplifier. However, in situations where a large signal change is experienced with respect to the differential input signal, the auxiliary circuit functions to speed up the sourcing and sinking current to/from the output node. A stability compensation capacitor coupled to the output node is accordingly more quickly charged or discharged and an improvement in slew rate performance of the differential amplifier is experienced.