Patents Issued in August 7, 2007
  • Patent number: 7254015
    Abstract: A multi-functional device for a computer has a first set of functions when the multi-functional device is inserted into the computer and a second set of functions when removed from the computer.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: August 7, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Memphis-Zhihong Yin, Cary J. Hoffer
  • Patent number: 7254016
    Abstract: A data storage system having an interconnect, storage devices coupled to a first side of the interconnect, and a processing subsystem coupled to a second side of the interconnect that is substantially opposite the first side. The method involves a user (e.g., a customer) receiving a fault signal from the data storage system (e.g., an email notification, a GUI message, an LED pattern, etc.), identifying a component of the data storage system as faulty in response to receiving the fault signal, and replacing the identified component with a new component. In general, the user replaces the identified component in a hot-swapping manner when the identified component is a storage device or a power supply. Additionally, the user replaces the identified component in a powered-down manner when the identified component is a portion of a storage processing circuit (e.g., an internal fan, a memory circuit, a storage processing circuit, etc.).
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: August 7, 2007
    Assignee: EMC Corporation
    Inventors: Stephen E. Strickland, Adrianna D. Bailey, Steven D. Sardella, Alan McIlvene, Maida Boudreau
  • Patent number: 7254017
    Abstract: A storage device assembly includes a tray (10) receiving a hard disk drive (60) therein, a bracket (20) attached in the tray, and a chassis (70). An actuator (30) is pivotally attached to an outer space of the bracket, a slider (40) is slidably attached to an inner space of the bracket, a spring (28) is arranged between the slider and the bracket. The chassis includes a number of spacing plates (73) each defining a pair of apertures (731). The tray includes a sidewall (12) defining a pair of apertures (121). The slider includes a pair of wedge-shaped extension tabs (411). The tray is secured in the chassis, with the extension tabs extending through the apertures of the tray and the chassis. To detach the tray from the chassis, the actuator is pivoted out and presses the slider to withdraw its extension tabs from the apertures of the chassis.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: August 7, 2007
    Assignees: Hong Fu Jin Precision Ind. (Shenzhen) Co., Ltd., Hon Hai Precision Ind. Co., Ltd.
    Inventors: Wen-Tang Peng, ChengLung Cheng, Shu-Gang Shi, Zhe Zhang
  • Patent number: 7254018
    Abstract: A computer enclosure includes a chassis (20), a drive bracket (10) rotatably attached to the chassis and a holder (50). The chassis includes a pair of parallel beams (30,40). The drive bracket forms a sliding member (111). The holder is secured to one of the beams of the chassis, and defines a groove (531). A number of holding positions (534) are defined in the groove to selectively hold the sliding member of the drive bracket.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: August 7, 2007
    Assignees: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Yong-Gang Zhang, Shao-Bo Han, Pin-Shian Wu
  • Patent number: 7254019
    Abstract: A heat dissipation module for a mobile computer, the mobile computer having a base (10) and a display unit (20) pivotally coupled to the base, the base having a number of through holes (13) defined on a shell (18) thereof, the heat dissipation module including: a cooling fan (14) disposed near the through holes of the shell; and a heat pipe (15) having a evaporating section (52), a condensing section (56), and an intermediate section (54) connecting the evaporating section and the condensing section; wherein the evaporating section of the heat pipe is disposed between the shell and the cooling fan, and the condensing section of the heat pipe is disposed on the display unit of the mobile computer.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: August 7, 2007
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Charles Leu, Tai-Cherng Yu, Ga-Lane Chen, Jhy-Chain Lin
  • Patent number: 7254020
    Abstract: The present invention discloses a fan assembly for a power supply and improves the traditional installation of a fan onto a power supply that leaves insufficient spaces for designing the connecting holes as required by the existing installation specification, and mounts the fan into a power supply at a specific position by a specific fixing member and uses the fixing member to keep the fan at a specific interval from the end surface of the power supply without being in direct contact with the power supply. Therefore, the interval from the end surface provides sufficient space for the design of the ventilation holes for the airflow and the connecting holes as required by the installation specification of the power supply.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: August 7, 2007
    Assignee: Zippy Technology Corp.
    Inventor: Tzung-Han Lee
  • Patent number: 7254021
    Abstract: A fan duct (8) buckled to a fan (7) is mounted in a computer enclosure (4) having an upper panel (44) defining a plurality of apertures (440). The fan duct includes a first open portion (80) having a first opening (804) and a second open portion (82) having a second opening (822). The first open portion comprises two opposite lateral flanges (802). Each flange forms a pair of latches (806, 808) buckled to the fan to prevent removal of the fan duct in the horizontal direction. A pair of resilient tabs (824) is formed at two opposite lateral sides of the second opening. The tabs are pressed by the upper panel of the computer enclosure to confine the fan duct to move upwardly. The second opening communicates with the apertures and the first opening communicates with the fan.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: August 7, 2007
    Assignees: Fu Zhum Precision Industry (Shenzhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Hsieh-Kun Lee, Chun-Chi Chen, Shin-Hsuu Wung, Yu Huang
  • Patent number: 7254022
    Abstract: The invention relates to a cooling system for equipment and network cabinets and to a method for cooling such cabinets, together with the electronic modules located therein. In order to achieve with extremely simple means and particularly low capital and operating expenditure a high power cooling for densely packed cabinets and cabinet arrangements, particularly server cabinets in data processing centers and the like, an air ducting is provided in a substantially airtight cabinet with equally long airflow paths and therefore equal flow resistances, together with a uniform supply air temperature. The circulated airflow is cooled with the aid of an air-water heat exchanger in the lower cabinet area. The heated exhaust air is collected in a collecting duct with a rising flow, reversed and supplied in a falling flow to the heat exchanger.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: August 7, 2007
    Assignee: Knuerr AG
    Inventor: Heiko Ebermann
  • Patent number: 7254023
    Abstract: A heat dissipation assembly includes a blower holder, a blower, a first heat sink and a second heat sink. The blower includes an inlet and an outlet and is attached to the blower holder. The blower holder is secured to the first heat sink with the inlet of the blower exposed to the first heat sink. The second heat sink is mounted to the blower holder and confronts the outlet of the blower. The second heat sink thermally connects with the first heat sink via heat pipes.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: August 7, 2007
    Assignees: Fu Zhun Precision Industry (Shenzhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Cui-Jun Lu, Ling-Bo Cao, Zhi-Qiang Sun
  • Patent number: 7254024
    Abstract: A Micro Blade is described for implementing an electronic assembly having a thin profile; it is a miniaturized stand-alone unit that is mechanically and thermally rugged, and connects to external components using a cable. The electronic assembly is preferably fabricated on a copper foil substrate including an interconnection circuit, a special assembly layer, and directly attached components. The components are preferably in bare die form, and are preferably attached using plated copper spring elements inserted into wells filled with solder. The copper foil substrate may be folded to form a compact system in package (SIP) inside of the Micro Blade. A jacket comprised of thermally conductive members is formed around the electronic assembly using hermetic seams. The Micro Blade is preferably cooled by immersion in water contained in a tank; the water is cooled and circulated using an external pumping system.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: August 7, 2007
    Inventor: Peter C. Salmon
  • Patent number: 7254025
    Abstract: A structure may be coupled to an adapter coupling two or more modules together. In some embodiments, the structure may direct air and/or dissipate heat from the modules into the air. The structures may direct air to components on a module that might receive less airflow without the structures. In some embodiments, the structure may be coupled to the adapter through a fastener (e.g., multiple structures may be manufactured with a plate, and the plate may be coupled to the adapter). In some embodiments, thermally conductive pathways may be used on the modules to conduct heat from components on the modules to a heat dissipating structure on the adapter.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: August 7, 2007
    Assignee: National Instruments Corporation
    Inventor: Richard G. Baldwin, Jr.
  • Patent number: 7254026
    Abstract: A heat dissipation device (40) includes at least a heat pipe (45) and a plurality of metal fins (43) thermally connected to the heat pipe. Each of the metal fins defines therein an aperture (431). An extension flange (433) extends outwardly from the metal fin and surrounds the aperture. The extension flange defines therein a plurality of slits (435). The apertures and extension flanges of the metal fins are aligned together. The heat pipe is received in the aligned apertures and soldered by a thermal medium material to the metal fins via the aligned extension flanges. During the soldering process, rosin content contained in the thermal medium material can be discharged away via the slits formed in the extension flange.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: August 7, 2007
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Ming Yang, Yeu-Lih Lin, Chin-Lung Chen
  • Patent number: 7254027
    Abstract: Embodiments include apparatus, methods, and systems of a processor module for a system board. In one embodiment, an electronic module, having first and second portions, is removably connectable to the system board. The first portion connects to the system board and includes a thermal dissipation device and a printed circuit board (PCB) with a processor connected to a first side of the PCB. The thermal dissipation device dissipates heat, via a heat exchange, from the processor. The second portion is disposed in a space created between the first portion and the system board. The second portion has a power system board for providing power to the processor. The power system board extends adjacent and parallel to a second side of the PCB.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: August 7, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Christian L. Belady, Gary W. Williams, Shaun L. Harris, Steven A. Belson, Eric C. Peterson
  • Patent number: 7254028
    Abstract: An electronic assembly includes a PCB (20), a socket (22) mounted on the PCB, a CPU (24) connected with the socket, a heat sink (10) in thermal contact with the CPU, a foldable back plate (30) attached to an underside of the PCB and a base plane (40) forming four bridges (42). The back plate includes a first piece section (32) and a second piece section (34) pivotally joined together by a pivot (36). The first and the second piece sections each comprise two legs inserted into two corresponding bridges. Screws are used to extend through the heat sink, the PCB, the bridges to threadedly engage with the legs of the back plate, respectively. The pivot is located under a part of the PCB at which the CPU is mounted.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: August 7, 2007
    Assignees: Fu Zhun Precision Industry (Shenzhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Hsieh-Kun Lee, Chun-Chi Chen, Shin-Hsuu Wung, Yu Huang
  • Patent number: 7254029
    Abstract: An electronic assembly includes a printed circuit aboard, a CPU, an electronic component and a thermal pad attached to the printed circuit board. The CPU and the electronic component are located on a first face of the printed circuit board. The electronic component is located near the CPU. The thermal pad is attached to a second face opposite to the first face of the printed circuit board and located just below the electronic component.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: August 7, 2007
    Assignees: Fu Zhun Precision Industry (Shenzhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Yong-Dong Chen, Guang Yu, Shin-Hsuu Wung, Chun-Chi Chen, Hsieh-Kun Lee
  • Patent number: 7254030
    Abstract: A low-cost heat sink easy to assemble which is designed to be mounted on a power semiconductor module (5) through the medium of cooling water includes a base member (1), a heat sink body (2) superposed on the base member (1) to form in cooperation with the base member (1) a passage through which the coolant flows, and a bellows-like flow straightening plate (6) disposed between the power semiconductor module (5) and the base member (1) in physical contact with the power semiconductor module (5) on one hand and with the base member (1) on the other hand. The flow straightening plate (6) partitions the passage into a plurality of flow straightening channels (14A, 14B).
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: August 7, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Chiba, Tetsuro Ogushi, Akira Yamada, Hiroshi Yamabuchi
  • Patent number: 7254031
    Abstract: A display apparatus having a heat dissipating structure for a driver integrated circuit is provided. The display apparatus may be a plasma display apparatus including a chassis base, a plasma display panel (PDP) adjacent to a first side of the chassis base, and a driving circuit board attached on a second side of the chassis base, the second side being opposite to the first side where the PDP is attached. The plasma display apparatus also includes a driver integrated circuit (IC) electrically connected to electrodes of the PDP and the driving circuit board at a position therebetween, the driver IC selectively providing a voltage to the electrodes of the PDP in accordance with signals controlled by the driving circuit board. The plasma display apparatus also has a heat dissipation unit positioned at the edge of the PDP wherein the heat dissipation unit dissipates heat from the driver IC.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: August 7, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Ki-Jung Kim, Tae-Kyoung Kang
  • Patent number: 7254032
    Abstract: A circuit board component includes a substrate having non-conductive material and conductive material supported by the non-conductive material. The conductive material defines a circuit board interface, a die interface, a heat spreader interface, and (iv) a set of connections which interconnects the circuit board interface, the die interface and the heat spreader interface. The component further includes a die coupled to the die interface. The die includes integrated circuitry which is configured to electrically communicate with a circuit board when the circuit board couples to the circuit board interface. The component further includes a heat spreader coupled to the heat spreader interface. The heat spreader is configured to dissipate heat from the die. The heat spreader in combination with the heat spreader interface forms an electromagnetic interference shield when a portion of the circuit board interface connects to a ground reference of the circuit board.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: August 7, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Jie Xue, Zhiping Yang, Yida Zou
  • Patent number: 7254033
    Abstract: Embodiments of methods, apparatuses, devices, and/or systems for heat dissipation are disclosed.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: August 7, 2007
    Inventors: Behdad Jafari, Inderjit Singh
  • Patent number: 7254034
    Abstract: A thermal management for EMI shielded circuit packs having one or more high-power components, i.e. heat sources. More particularly, a heat transfer device or assembly for EMI shielded circuit packs is provided whereby multiple components (e.g., high-power components) are cooled by individual heat sinks (i.e., each component has its own individual heat sink) which protrude into an external airflow through individual openings in the lid of the EMI shield. Mechanically-compliant, electrically-conductive gaskets are used to seal the base plates of the individual heat sinks against the lid of the EMI shield enclosure. As such, in accordance with the various embodiments, the conductive gaskets establish a compliance layer which accommodates any variation in the heights of the individual components, thereby, allowing optimum thermal contact between the components and their respective heat sinks without compromising the EMI shielding.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: August 7, 2007
    Assignee: Lucent Technologies Inc.
    Inventors: Cristian A Bolle, Marc Scott Hodes, Paul Robert Kolodner
  • Patent number: 7254035
    Abstract: Provided is a structure in which a shield 308 and a heat sink 307 integrated with a radiation fin 306 are sandwiched by a main substrate 381a and a power source substrate 381b. A hood 142d covers the radiation fin 306 so as to collect air for cooling. Major parts of the main substrate 381a are in contact with the heat sink 307 via heat conduction members having different heat conductivity so that an even thermal distribution is provided. Thus, parts of electronic equipment can be efficiently disposed in a limited space. Moreover, the parts of the electronic equipment can be effectively cooled.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: August 7, 2007
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Chiyoshi Sasaki, Kouji Hirata, Katsushi Itoh, Yasuhiro Ootori, Ryouichi Kubota
  • Patent number: 7254036
    Abstract: A module is electrically connectable to a computer system. The module includes a frame having an edge connector with a plurality of electrical contacts which are electrically connectable to the computer system. The module further includes a first printed circuit board coupled to the frame. The first printed circuit board has a first surface and a first plurality of components mounted on the first surface. The first plurality of components is electrically coupled to the electrical contacts of the edge connector. The module further includes a second printed circuit board coupled to the frame. The second printed circuit board has a second surface and a second plurality of components mounted on the second surface. The second plurality of components is electrically coupled to the electrical contacts of the edge connector. The second surface of the second printed circuit board faces the first surface of the first printed circuit board.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: August 7, 2007
    Assignee: Netlist, Inc.
    Inventors: Robert S. Pauley, Jayesh R. Bhakta, William M. Gervasi, Chi She Chen, Jose Delvalle
  • Patent number: 7254037
    Abstract: A mounting apparatus for mounting a motherboard (10) includes a base (200) with a number of standoffs (210) formed thereon, a driving member (130), an operating member (110) and a supporting tray (20) with a number of mounting holes (27) defined therein. The driving member is slidably attached to the base and a driving shaft (144) is formed thereon. The operating member is pivotally attached to the base with a first cutout (114) and a second cutout (116) defined therein. The supporting tray is secured on a bottom surface of the motherboard with a post (42) formed thereunder. The driving shaft and the post is respectively engaged in the first cutout and the second cutout. After the standoffs are received in corresponding mounting holes, the motherboard is assembled or disassembled by pushing or pulling the driving member.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: August 7, 2007
    Assignees: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Yun-Lung Chen, Guo-Hua Chen
  • Patent number: 7254038
    Abstract: A space-conscious system utilizes a low profile expansion card for providing a physical and electrical interface between a larger scale board, such as a motherboard, and an external component. The expansion card is mounted in a perpendicular orientation relative to the larger scale board, despite dimensional limitations with regard to such an orientation. The expansion card includes an input/output circuit board and a “signal-conduction extender” for enabling coupling to an external wall of the housing in which the expansion card and larger scale board are contained. In one possible embodiment, the housing is compatible with the 1U standard, the expansion card is an Ethernet card, and there is an adapter board at the front wall of the housing for routing connections from the expansion card to an exposed port. The invention allows a number of the expansion cards to be mounted in parallel within the same container.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: August 7, 2007
    Assignee: Barracuda Networks, Inc.
    Inventor: Dean M. Drako
  • Patent number: 7254039
    Abstract: A multi-service platform system (100, 200, 300, 400) includes a computer chassis (101, 201, 301, 401) having a plurality of 3U slots (205), a backplane (104) integrated in the computer chassis, a switched fabric (106) on the backplane. At least one of a VMEbus network and a PCI network are coincident with the switched fabric on the backplane. A payload module (102) having a 3U form factor is coupled to interface with one of the plurality of 3U slots, where the payload module is communicatively coupled with the backplane using the switched fabric and at least one of the VMEbus network and the PCI network. At least one multi-gigabit connector (118) is coupled to a rear edge (119) of the payload module, where the at least one multi-gigabit connector is coupled to communicatively interface the payload module to the backplane, and where the switched fabric and at least one of the VMEbus network and the PCI network are communicatively coupled with the payload module through the at least one multi-gigabit connector.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: August 7, 2007
    Assignee: Motorola, Inc.
    Inventors: Douglas L. Sandy, Jeffrey M. Harris, Robert C. Tufford
  • Patent number: 7254040
    Abstract: An apparatus, system, and method are disclosed for connecting and disconnecting daughter cards. A handle urges a locking member toward a base comprising a stop and a channel. The channel may direct the locking member to a specified position. The locking member biases the catch and the biased catch engages with the stop. The stop and the channel of the base secure the locking member to the base. In addition, the handle urges the locking member away from the base. The handle also urges an actuator to unbias the catch. The handle further disconnects the locking member from the base as the unbiased catch does not engage the stop.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: August 7, 2007
    Assignee: Lenovo Pte Ltd
    Inventors: Richard M. Barina, Norman Bruce Desroslers, Dean Frederick Herring, Paul Andrew Wormsbecher
  • Patent number: 7254041
    Abstract: A mounting apparatus for expansion cards, each of the expansion cards includes a slot cover. The mounting apparatus includes a chassis having a rear panel, a retaining bracket, and a top cover mounted on the chassis. The rear panel defines a plurality of slots for receiving the slot covers, and forms a support plate. A pair of securing slots is defined on the rear panel. The retaining bracket is detachably seated on the support plate. The retaining bracket includes a pressing plate and a main body perpendicular to the pressing plate. A pair of securing members extends outward from the main body, for engaging in the securing slots. The top cover has a flange extending down, and the main body of the retaining bracket is sandwiched between the flange of the top cover and the rear panel of the chassis.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: August 7, 2007
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Yun-Lung Chen, Yu-Ming Xiao
  • Patent number: 7254042
    Abstract: An Electro Magnetic Interference (EMI) shielding device (20) includes a body (201), at least a first engaging portion (203) extending from the body, and a pair of second engaging portions (205) formed on the body. A liquid crystal display device adopting the above mentioned EMI shielding device includes a TFT LCD panel, a power supply (12), an inverter (14) and an interface board (13). The power supply, the inverter and the interface board are formed on a printed circuit board (10). The EMI shielding device is positioned between the power supply and the inverter, with the first engaging portion inserted into the printed circuit board and the second engaging portions engaging with the printed circuit board. The EMI shielding device can reduce or potentially avoid the occurrence of EMI that would otherwise be produced by the printed circuit board.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: August 7, 2007
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Lan Huang
  • Patent number: 7254043
    Abstract: The present invention relates to a power converter, using input voltage provided by a fuel battery and processing an electrical characteristics transformation on the input voltage to output an output voltage to loading. The power converter comprises: a multiple-phase PWM controller to output multiple PWM control signals in accordance with the voltage level of output voltage; a multiple phase bridge converter to input and output the input voltage in accordance with the multiple PWM control signals; and a transformer to input and process an electrical characteristics transformation on the input voltage from the multiple phase bridge converters to output the output voltage. The multiple-phase PWM controller further comprises a PWM generator and at least one phase shifter.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: August 7, 2007
    Assignee: Tatung Co., Ltd.
    Inventors: Jih-Sheng Lai, Haun-Liung Chen, Kevin Wu
  • Patent number: 7254044
    Abstract: The present invention is directed generally to a power supply. According to various embodiments, the power supply includes at least one DC/DC converter. The converter includes a primary switch controlled by a pulse width modulated control signal such that the primary switch is on for a D time period of each switching cycle of the converter and is off for a 1-D time period of each switching cycle. Also, the power supply includes a current sensing element connected in series with the primary switch. In addition, the power supply includes a current limit circuit connected to the current sensing element. The current limit circuit includes a functional circuit having a first input responsive to a first signal whose voltage is proportional to the output current of the converter during the D time period of the switching cycle of the converter.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: August 7, 2007
    Assignee: Artesyn Technologies, Inc.
    Inventors: Marty Perry, Ian Poynton
  • Patent number: 7254045
    Abstract: A power factor is improved using a simplified structure without particularly providing a power factor improving circuit, and high efficiency is obtained.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: August 7, 2007
    Assignee: Sony Corporation
    Inventor: Noritoshi Imamura
  • Patent number: 7254046
    Abstract: In a DC to DC converter, first and second primary windings are magnetically coupled to a first secondary winding. Third and fourth primary windings are magnetically coupled to a second secondary winding. The first and second primary windings are magnetically coupled to the first secondary winding. The third and fourth primary windings are magnetically coupled to the second secondary winding. The first and third primary windings are coupled in series to form a first coil member. The second and fourth primary windings are coupled in series to form a second coil member. One end of the first coil member is coupled to the first positive power line. A first switching element is coupled between the first negative power line and the other end of the first coil member. A first capacitor is coupled between the first negative terminal and one end of the second coil member.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: August 7, 2007
    Assignees: Denso Corporation, Nippon Soken, Inc.
    Inventors: Koji Kawasaki, Keiji Shigeoka, Tsuyoshi Yamashita
  • Patent number: 7254047
    Abstract: Power converters having reduced body diode conduction loss, reduced reverse recovery loss and lower switching noise, among other benefits, have a resonant capacitor Cr connected across an unfiltered output. The resonant capacitor Cr resonates with the leakage inductance Lk of the transformer. The resonant capacitor and leakage inductance are selected such that ½ a LC resonance period is equal to an ON time of each secondary switch S1 S2. The resonance provides zero current switching for secondary switches S1 S2, eliminates zero body diode conduction during dead times, and eliminates reverse recovery losses in the secondary switches. The present invention is applicable to many different circuit topologies such as full bridge, active clamp forward, push-pull forward, and center-tap secondary. The present converters provide high energy conversion efficiency and high frequency operation.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: August 7, 2007
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Yuancheng Ren, Julu Sun, Ming Xu, Fred C. Lee
  • Patent number: 7254048
    Abstract: A programmable AC/DC power converter receives a plurality of input voltages and outputs a single voltage from an input voltage system. A transformer receives the single voltage. One of the plurality of input voltages is provided at a center tap of a secondary winding of the transformer. A transformed voltage is output. A rectifier receives the transformed voltage and outputs a DC voltage. A buck regulator receives a DC voltage, creates a regulated voltage, and outputs the regulated voltage and a regulated current to a portable appliance. A error correction system receives a programming signal and regulated signals and verifies that the regulated signal to programming signal ratio is within an acceptable range.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: August 7, 2007
    Assignee: Comarco Wireless Technologies, Inc.
    Inventor: Thomas W Lanni
  • Patent number: 7254049
    Abstract: A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Hendrik Hartono, Benjamin Louie, Aaron Yip, Hagop A. Nazarian
  • Patent number: 7254050
    Abstract: A method of controlling a negative differential resistance (NDR) element is disclosed, which includes altering various NDR characteristics during operation to effectuate different NDR modes. By changing biasing conditions applied to the NDR element (such as a silicon based NDR FET) a peak-to-valley ratio (PVR) (or some other characteristic) can be modified dynamically to accommodate a desired operational change in a circuit that uses the NDR element. In a memory or logic application, for example, a valley current can be reduced during quiescent periods to reduce operating power. Thus an adaptive NDR element can be utilized advantageously within a conventional semiconductor circuit.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: August 7, 2007
    Assignee: Synopsys, Inc.
    Inventor: Tsu-Jae King
  • Patent number: 7254051
    Abstract: A semiconductor memory device comprises a plurality of memory cells each having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal, wherein the plurality of memory cells are connected in series, and one or more selected transistors connected to at least one terminal of the series connected memory cells to constitute a memory cell block, the memory cell block having one terminal connected to a bitline and another terminal connected to a plate electrode, and wherein two memory cell blocks, which are respectively connected to two bit lines forming a bit line pair and also connected to the same word line, are respectively connected to a first plate electrode and a second plate electrode.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: August 7, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Daisaburo Takashima
  • Patent number: 7254052
    Abstract: The present invention relates to a memory circuit comprising a CBRAM resistance memory cell, which is connected to a bit line and a word line and has a CBRAM resistance element, the resistance of which can be set by means of a write current, in order to store an item of information, and which has a selection switch, which can be driven via the word line, in order to connect a first potential to the bit line via the CBRAM resistance element; a reference resistance cell, which is connected to the bit line and to a reference line and has a reference resistance element, the resistance of which is set to a resistance threshold value, and a reference selection switch, which can be driven via the reference line, in order to connect a second potential to the bit line via the reference resistance element; a read-out unit, which is configured to activate the reference selection switch and the selection switch for the purpose of reading out a memory datum, so that a memory cell current flows via the CBRAM resistance mem
    Type: Grant
    Filed: November 25, 2005
    Date of Patent: August 7, 2007
    Assignee: Infineon Technologies AG
    Inventor: Corvin Liaw
  • Patent number: 7254053
    Abstract: Systems and methodologies for programming a memory cell having a functional or selective conductive layer are provided. The functional zone can include active, and/or passive and/or barrier layers. The system includes a controller that can actively trace conditions associated with such programming. In one aspect of the present invention, by providing an external stimulus, an associated electrical or optical property associated with the memory cell is affected. Such property is then compared to a predetermined value to set/verify a programming state for the memory cell. The external stimulus can then be removed upon completion of the programming, or reduced to a verifying state to read information. The memory cell can include alternating layers of active, passive, diode, and barrier layers positioned between at least two electrodes.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Juri Heinrich Krieger, Nikolay Fedorovich Yudanov
  • Patent number: 7254054
    Abstract: A magnetic random access memory is provided including a substrate, a magnetoresistance element which includes a ferromagnetic layer having an invertible spontaneous magnetization, which varies in resistance according to the direction of the spontaneous magnetization, and is formed above the substrate, and a wiring which extends in a first direction and is used for making an electric current flow to generate a magnetic field to be applied to the magnetoresistance element. The wiring is formed so as to pass through a first position which is closer to the substrate than the magnetoresistance element and does not overlap the magnetoresistance element when viewed from a direction perpendicular to the main surface of the substrate, and a second position being above said magnetoresistance element.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: August 7, 2007
    Assignee: NEC Corporation
    Inventors: Tetsuhiro Suzuki, Sadahiko Miura
  • Patent number: 7254055
    Abstract: In a firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation, the phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: August 7, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Beak-hyung Cho, Du-eung Kim, Choong-keun Kwak
  • Patent number: 7254056
    Abstract: In an embodiment, a phase change non-volatile memory includes a number of memory cells. The memory cells include a phase change material which may transition between two memory states. The phase change material has different electrical properties in different states. The memory cells may be electrically addressable and include a transistor in each cell to electrically read and write data to the cell. An energy beam may be used to pre-program the device by heating selected memory cells, and consequently changing the state of the phase change material.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: August 7, 2007
    Assignee: Intel Corporation
    Inventor: Peter Nangle
  • Patent number: 7254057
    Abstract: An MTJ memory cell is independently provided with a write word line and a read word line used for data write and data read. By separately arranging read word lines every two regions formed by dividing a memory array in the column direction, it is possible to reduce signal propagation delays of the read word lines and accelerate the data read operation. Activation of each read word line is controlled by a write word line in accordance with a row selection result in a hierarchical manner. A word-line-current control circuit forms and cuts off the current path of a write word line correspondingly to data write and data read.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: August 7, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Hideto Hidaka
  • Patent number: 7254058
    Abstract: A program element has a magnetic layer electrically connected between first and second nodes. At least a portion of the magnetic layer forms a link portion designed to be blown with external laser irradiation. The magnetic layer is provided in the same layer as and with the same structure as a tunneling magneto-resistance element in an MTJ memory cell. An electrical contact between the magnetic layer and respective one of the first and second nodes has the same structure as the electrical contact between the tunneling magneto-resistance element and an interconnection provided in the same metal interconnection layer as respective one of the first and second nodes in the MTJ memory cell.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: August 7, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Hideto Hidaka
  • Patent number: 7254059
    Abstract: A multilevel phase change memory element and operating method and electrodes, which are configured in a parallel structure to form a memory cell. A voltage-drive mode is employed to control and drive the memory element such that multilevel memory states may be achieved by imposing different voltage levels. The provided multilevel phase-change memory element has more bits and higher capacity than that of a memory element with a single phase-change layer.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: August 7, 2007
    Assignee: Industrial Technology Research Institut
    Inventors: Chien-Ming Li, Wen-Han Wang, Kuei-Hung Shen
  • Patent number: 7254060
    Abstract: The nonvolatile semiconductor memory device includes a memory cell array containing a plurality of nonvolatile memory cells and an initial setup data region in which initial setup data specified to determine operation conditions of the device is to be written. The device further includes a detection circuit which detects turn-on of power. The device further includes a readout circuit which reads out the initial setup data from the initial setup data region of the memory cell array upon detecting power-on by the detection circuit. The device further includes a determination circuit which determines whether the initial setup data read out by the readout circuit is effective or ineffective. The device further includes a setup circuit which sets up the device in an operative-prohibiting status when the initial setup data is determined as ineffective by the determination circuit.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: August 7, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Kawai, Kenichi Imamiya, Koji Hosono
  • Patent number: 7254061
    Abstract: A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The data latch circuit latches an output of the tri-state buffer. The data line connects the tri-state buffer and the data latch circuit. The memory device removes charge on the data line using a latch enable signal, which is applied to the tri-state buffer before a read operation.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: August 7, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Seung-Keun Lee
  • Patent number: 7254062
    Abstract: A bit-line selection circuit for a memory device includes a decoding line and a dummy line: The decoding line is between a regulated voltage node, and a programming voltage node generating a programming voltage for a cell in the memory device. The decoding line includes at least one input transistor connected to the regulated voltage node, and is controlled by an enable/disable signal. The dummy line is identical to the decoding line, and is controlled by the enable/disable signal. An equalization circuit is connected between the decoding and dummy lines for setting a current in the dummy line equal to a current in the decoding line. A regulating circuit regulates the programming voltage generated at the programming voltage node in the decoding line. The regulating circuit has a first input for receiving a reference voltage, a second input for receiving a sensed voltage on the programming voltage node in the dummy line, and an output for providing the enable/disable signal.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: August 7, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ignazio Martines, Davide Torrisi
  • Patent number: 7254063
    Abstract: In a reference cell 202, first and second cells 50 and 52 having the same structure as that of a memory cell are provided. A memory cell current IREF1 of the first cell 50 is set to be a minimum value of a memory cell current after an erase operation. A memory cell current IREF2 of the second cell 52 is set to be a maximum value of a memory cell current after a write operation. The read circuit 206 compares a memory cell current Icell with a current (IREF1+IREF2)/2 and outputs a comparison result. A current source for use in erase verification and write verification may be used in place of the first and second cells 50 and 52.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: August 7, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshiki Mori
  • Patent number: 7254064
    Abstract: There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: August 7, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hwan Kim, Yeong-Taek Lee