Patents Issued in September 11, 2007
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Patent number: 7269665Abstract: Techniques are provided to integrate application systems by using an isolated mapping point that is a computer system, a server, or other computing device that includes a mapping data store and performs mapping functions. An isolated mapping point receives data from the sending system, transforms the data as necessary, and sends the transformed data to the receiving system. The isolated mapping point performs the data transformation without accessing data or processes on the sending system or the receiving system. The isolated mapping point is separate (or isolated) from both the sending system and the receiving system. The isolated mapping point uses only data included in the mapping database. The isolated mapping point receives data included in the mapping database received through a well-defined interface.Type: GrantFiled: January 2, 2003Date of Patent: September 11, 2007Assignee: SAP AGInventors: Heinz Pauly, Prasad Kompalli, Karl-Heinz Foerg
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Patent number: 7269666Abstract: Packet sequence numbers of request packets and response packets of transactions transferring data to or from a network interface are tracked. For every request packet transmitted by the network interface, the packet sequence number of the packet is written to a location in a circular send queue pointed to by a write pointer and a valid bit at the location is set. The write pointer is incremented if the packet is a read request packet. Alternatively, a read indicator at the location in the circular send queue pointed to by the write pointer is cleared if the packet is not a read request packet. For every response packet received by the network interface, the packet sequence number of the response packet is checked against the packet sequence number stored at the location in the circular send queue pointed to by the read pointer of the circular send queue.Type: GrantFiled: June 30, 2000Date of Patent: September 11, 2007Assignee: Intel CorporationInventors: Brian M. Leitner, Dominic Gasbarro, Tom Burton, Dick Reohr, Ni Jie
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Patent number: 7269667Abstract: A method for migrating from a source storage system to a target storage system includes defining a volume defined on a device to be migrated in the source storage system as an external volume to the target storage system; causing the host to access the volume on the drive to be migrated through an input/output port of the drive to be migrated as the external volume of the target storage system; blocking the other input/output port of the drive to be migrated while maintaining the access to the external volume of the target storage system; reconnecting the blocked input/output port with an interface in the target storage system; blocking the input/output port through which the external volume is being accessed, and connecting it with the interface in the target storage system; and implementing the drive to be migrated in the target storage system.Type: GrantFiled: August 30, 2006Date of Patent: September 11, 2007Assignee: Hitachi, Ltd.Inventors: Noboru Morishita, Yasutomo Yamamoto
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Patent number: 7269668Abstract: A software and hardware “kit” provides users the ability to seamlessly connect to local area networks at temporary accommodations and remote locations. The “kit” provides the end user with the ability to install wireless network interface cards on a computer, while bypassing the standard “Plug and Play” process, and provides the system configuration necessary to enable the hardware functionality. This will also allow the end user to immediately connect to the local area network, such as a wireless local area network, provided that the user's system is physically located within signal range. This process may be accomplished without the requirement that hardware actually be present and without rebooting the computer system, thus providing a novel improvement over the standard “Plug and Play” process.Type: GrantFiled: September 5, 2002Date of Patent: September 11, 2007Inventors: Darrell J. Redford, G. Jeffery Hall, Mark E. Marrott, Shirlene G. Peck
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Patent number: 7269669Abstract: Multi-media Memory Card (MMC) devices, Secure Digital (SD) devices, and Secure Digital Input Output (SDIO) devices connected to a single host controller with signals multiplexed to allow simultaneous activation of more than one device at a time.Type: GrantFiled: July 7, 2004Date of Patent: September 11, 2007Assignee: Sychip IncInventors: Wei Liu, Feng Mo, Kunquan Sun, Yanbing Yu, Yujie Zhu
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Patent number: 7269670Abstract: An analog Ethernet detector determines if an IEEE 1394b long haul application using Category 5 (CAT 5 UTP) cable, is connected to an Ethernet which share certain pins of the RJ45 connector used to connect devices to the CAT 5 cable. The detector does not require a processor core or clocking and can be built as a completely analog device.Type: GrantFiled: June 5, 2003Date of Patent: September 11, 2007Assignee: Texas Instruments IncorporatedInventors: Scott Sterrantino, Win N. Maung
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Patent number: 7269671Abstract: Systems, methods and computer program products partition a whole program when it does not fit in a device's memory. Minimal, safe program partitions are downloaded from the server on demand into the embedded device just before their execution. Code and data of the program are partitioned such that no information regarding the control flow behavior of the program is leaked out. Thus, by observing the program partitions that are downloaded from the server to the device, an attacker is unable to guess which branches are taken in the program and what is the control flow of the program. This property of tamper resistance is valuable for secure embedded devices, such as smart cards, which could hold sensitive information and/or carry out critical computation such as financial transactions.Type: GrantFiled: June 4, 2003Date of Patent: September 11, 2007Assignees: Georgia Tech Research Corporation, Infineon Technologies AGInventors: Santosh Pande, Tao Zhang, Andre Dos Santos, Franz Josef Bruecklmayr
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Patent number: 7269672Abstract: A design method for a bus system comprising a noise propagation computation step and a connection timing computation step. Based on the cycle of a timing signal, a signal propagation delay in a device unit, signal propagation delays in a timing-signal bus and a data bus, and a setup time in the device unit or device connected on the data bus, the noise propagation computation step computes timing at which, when the device unit is connected on the data bus being active, noise propagates to other device units other than the connected device unit or to the device connected on the data bus. Based on the timing computed in the noise propagation computation step, the connection timing computation step computes connection timing at which the device unit is connected on the data bus.Type: GrantFiled: February 13, 2004Date of Patent: September 11, 2007Assignee: Fujitsu LimitedInventor: Ryohei Nishimiya
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Patent number: 7269673Abstract: A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information.Type: GrantFiled: February 18, 2004Date of Patent: September 11, 2007Assignee: Silicon Image, Inc.Inventors: Ook Kim, Eric Lee, Gyudong Kim, Zeehoon Jang, Baegin Sung, Nam Hoon Kim, Gijung Ahn, Seung Ho Hwang
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Patent number: 7269674Abstract: A disk array apparatus using an SAS can transfer data without lowering a transfer efficiency of data even if rates of a plurality of physical links connected to a controller and storage device are different. A plurality of HDDs are connected to a controller through an expander. Data are transferred from the controller to the expander and then to HDD. In this connection, the controller and the expander transfers a set of transfer data in a plurality of the HDD-side physical links. The controller-side physical link integrates the transfer data, and multiplexes them to transfer. A plurality of HDDs-side physical links separates the transfer data to transfer in parallel.Type: GrantFiled: April 28, 2006Date of Patent: September 11, 2007Assignee: Hitachi, Ltd.Inventors: Takashi Chikusa, Satoru Yamaura, Toshio Tachibana, Takehiro Maki, Hirotaka Honma
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Patent number: 7269675Abstract: A method and device for monitoring a bus system and bus system having at least two users, of which at least one is structured as an authorized user and monitors the data transmission on the bus system, an identifier being transmitted and the identifier being uniquely allocatable to one user for each data transmission on the bus system, the at least one authorized user comparing the identifier with a specified identifier, and if both identifiers are the same taking measures in order to prevent an execution of the data to be transmitted if the data transmission is initiated by a user other than the at least one authorized user.Type: GrantFiled: September 26, 2002Date of Patent: September 11, 2007Assignee: Robert Bosch GmbHInventors: Lambros Dalakuras, Frank Schmidt, Juergen Hirt
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Patent number: 7269676Abstract: A method and apparatus for controlling a device by a serial link from a dual processor system. The configuration of the circuit is simplified and efficiency is enhanced by using independent internal buses and serial link control hardware for each processor and by selecting the active control hardware through arbitration. An MCU and a DSP can operate asynchronously and use their respective internal bus at the same time.Type: GrantFiled: January 7, 2004Date of Patent: September 11, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Seong-Ho Yoon
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Patent number: 7269677Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.Type: GrantFiled: October 29, 2003Date of Patent: September 11, 2007Assignee: Renesas Technology Corp.Inventors: Satoshi Misaka, Shinjiro Yamada
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Patent number: 7269678Abstract: An interrupt controller specifies and outputs the most highly prioritized one of a plurality of interrupt signal requested for output. A CPU executes a process corresponding to an interrupt signal from the interrupt controller and executes OS-provided programs. Based on reception of a request to execute a task level process, the CPU requests the interrupt controller to output an interrupt signal corresponding to the task level process.Type: GrantFiled: March 25, 2005Date of Patent: September 11, 2007Assignee: DENSO CorporationInventor: Tadaharu Nishimura
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Patent number: 7269679Abstract: A method is provided for utilizing four error correcting code (ECC) pin connections of a PCI/PCI-X bus for one of Grant (GNT) and Request (REQ) pin connections. The method determines a mode of the PCI bus to be PCI-X Mode 1, PCI-X Mode 2, or PCI. If the determined mode is PCI-X Mode 2, the four ECC pin connections are used as ECC pin connections, and if the determined mode is PCI or PCI-X Mode 1, each of the four ECC pin connections is used as a GNT pin connection or a REQ pin connection.Type: GrantFiled: June 14, 2005Date of Patent: September 11, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Hanwoo Cho, Richard W. Reeves
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Patent number: 7269680Abstract: A bridge accessible by a host processor can expand access over a first bus to a second bus. The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is coupled between the first bus and the link. The second interface is coupled between the second bus and the link.Type: GrantFiled: May 20, 2000Date of Patent: September 11, 2007Assignee: Tao Logic Systems LLCInventor: Frank W. Ahern
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Patent number: 7269681Abstract: An integrated device (e.g., an integrated PCI bridge device) buffers received PCI bus strobe signals and distributes strobe signals for PCI receive data relative to the PCI data lines, enabling all PCI receive data to be latched using locally-generated PCI strobe signals generated based on the same PCI bus strobe signals. In addition, data line latch modules having primary and secondary flip-flops enable the PCI receive data to be held for an entire clock cycle, optimizing conversion between a PCI clock domain and a local clock domain of the PCI bridge device. A transmission circuit also can be configured to transmit data according to either double data rate (DDR) mode or quad data rate (QDR) mode in an efficient manner.Type: GrantFiled: December 1, 2004Date of Patent: September 11, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Austen John Hypher, Richard W. Reeves, Gerald Robert Talbot
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Patent number: 7269682Abstract: In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments.Type: GrantFiled: August 11, 2005Date of Patent: September 11, 2007Assignee: P.A. Semi, Inc.Inventors: Sridhar P. Subramanian, James B. Keller, George Kong Yiu, Ruchi Wadhawan
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Patent number: 7269683Abstract: A computer has access to a system-formatted data storage unit (DSU) containing a file system and to a raw DSU. A file within the file system constitutes a raw DSU mapping that facilitates access to the raw DSU. The raw DSU mapping appears to be an ordinary file to a storage user, but with the size of the raw DSU. An attempted access to the raw DSU mapping is translated into a corresponding access to the raw DSU. Access to the raw DSU by the storage user may be restricted to a specified region of the raw DSU, by defining an extent within the raw DSU mapping. The raw DSU mapping provides access to the raw DSU with many of the advantages of using a file system, including name persistency, permissions, persistent attributes, locking information for a distributed file system and other extended metadata.Type: GrantFiled: December 21, 2006Date of Patent: September 11, 2007Assignee: VM Ware, Inc.Inventors: Satyam B. Vaghani, Daniel J. Scales
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Patent number: 7269684Abstract: A method and a system is provided for persistently storing and restoring objects of an object oriented environment established on a computer system having a volatile memory and a persistent storage. Pieces of memory, referred to as segments are allocated in the volatile memory. Then, a first list is created that contains first references to said segments. The segments are further divided into blocks. The blocks are indicated by second references. The second references are stored in a second list. In order to store an object present in the volatile memory, a block is allocated. Then an object description is created by saving the object's values of its variables. After saving the object description in the allocated block, a new element is added to the second list containing the particular reference to said created object description. Then, the references of the object descriptions of all other objects referenced in the present object are determined.Type: GrantFiled: August 13, 2001Date of Patent: September 11, 2007Assignee: International Business Machines CorporationInventors: Konstantin Konson, Alexander Terekhov
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Patent number: 7269685Abstract: An apparatus and methods store data in a magnetic random access memory (MRAM) in a fast and efficient manner. Embodiments advantageously decrease the number of clock cycles required to store data by eliminating at least one wait state in a transition from a read state to a write state. Embodiments advantageously enhance the throughput of the MRAM and a related digital circuit, such as a computer system, which advantageously enhances the operating speed of the digital circuit.Type: GrantFiled: September 2, 2004Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventor: Richard W. Swanson
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Patent number: 7269686Abstract: A memory device includes memory cells arranged in multiple blocks. A register is provided to track multiple open pages per block of the memory. In one embodiment, the register is located in the memory device and used to determine if a memory access is to be performed. In another embodiment, the register is located external to the memory and used by a processor and/or chip set to determine if an access request is needed.Type: GrantFiled: December 13, 2005Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventor: Frankie Fariborz Roohparvar
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Patent number: 7269687Abstract: Systems and methods for storing data on a tape medium and coping with defective regions on the tape medium are provided. The method includes: writing a plurality of envelopes of data onto the tape medium, each envelope of data comprising a plurality of blocks of data; detecting a defective region of the tape medium; writing a boundary start field after the defective region, the boundary start field indicating that the defective region has been passed; and writing a boundary end field before the defective region of the tape medium, the boundary end field indicating that the defective region follows the boundary end field.Type: GrantFiled: August 20, 2004Date of Patent: September 11, 2007Assignee: Quantum CorporationInventors: Dwayne A. Edling, Charles Klomp
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Patent number: 7269688Abstract: A method of creating an image file to be additionally written is disclosed to prevent logical inconsistency between the image file and existing recorded data in a target information recording medium. The method of creating an image file of target information to be additionally written in an information recording medium includes: a first step of creating image data of the target information; a second step of obtaining identification information of the information recording medium; and a third step of creating an image file having the image data in association with the identification information.Type: GrantFiled: January 30, 2004Date of Patent: September 11, 2007Assignee: Ricoh Company, Ltd.Inventor: Hiroshi Gotoh
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Patent number: 7269689Abstract: An improved sliding window chunking apparatus and method comprising comparing a fingerprint value of each position in a data set to a second set of criteria, at least in instances when it doesn't satisfy a first set of criteria, and, if the value satisfies the second set of criteria, identifying the position as a potential breakpoint. Subsequently, if a fingerprint value that satisfies the first set of criteria is not found before a maximum chunk size is reached, the potential breakpoint can be designated as a breakpoint. Further improvement is possible by imposing minimum and maximum sizes on chunks. In some instances, more than two sets of criteria may be used to identify additional potential chunks to be used should subsets having fingerprint values satisfying either of the first two sets of criteria not be found.Type: GrantFiled: June 17, 2004Date of Patent: September 11, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kave Eshghi, Hsiu-Khuern Tang
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Patent number: 7269690Abstract: A data processing method for a disk array device capable of achieving a duplex system of data and improving performance of the same device while a quantity of processing for writing into a cache memory (through a switch) is reduced. In the disk array device, a host interface portion comprises a nonvolatile memory portion for saving data written from a host computer/server, and a data transfer control portion for transferring write data from the host computer/server to the nonvolatile memory portion and a global cache memory portion. If a write request is received from the host computer/server, a data transfer control portion transfers the write data from the host computer/server to the nonvolatile memory portion and to the global cache memory portion through a switch portion.Type: GrantFiled: July 21, 2006Date of Patent: September 11, 2007Assignee: Hitachi, Ltd.Inventors: Tetsuya Abe, Mitsuru Inoue
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Patent number: 7269691Abstract: A device for managing removable storage media includes a first management unit and a control unit. The first management unit is adapted to update first media management information which is held in said device and which includes at least a first datum that is used to detect that one removable storage medium has been replaced with a second removable storage medium, when the second removable storage medium is connected to said device, the first datum being information other than a user-input password. The control unit is adapted to test a command from an external device for consistency with the first datum and to execute the command if the first datum is consistent with second media management information contained in the command.Type: GrantFiled: November 29, 2000Date of Patent: September 11, 2007Assignee: Canon Kabushiki KaishaInventor: Shinji Onishi
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Patent number: 7269692Abstract: Techniques for implicitly caching connections to a resource (e.g., a database) are provided. A request for a connection does not specify that available connections are stored in a cache. If available connections are stored in a cache, the connection to the resource is obtained from the cache. Otherwise, a new connection to the resource is opened directly, without a connection caching mechanism.Type: GrantFiled: May 27, 2003Date of Patent: September 11, 2007Assignee: Oracle International CorporationInventor: Rajkumar Irudayaraj
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Patent number: 7269693Abstract: One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.Type: GrantFiled: August 8, 2003Date of Patent: September 11, 2007Assignee: Sun Microsystems, Inc.Inventors: Marc Tremblay, Quinn A. Jacobson, Shailender Chaudhry
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Patent number: 7269694Abstract: One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.Type: GrantFiled: August 8, 2003Date of Patent: September 11, 2007Assignee: Sun Microsystems, Inc.Inventors: Marc Tremblay, Quinn A. Jacobson, Shailender Chaudhry
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Patent number: 7269695Abstract: An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherein each of the first operations depend on at least one of the second operations during use. A first number of the first operations is less than or equal to a maximum. It is ambiguous, for a first received operation in the first virtual channel, whether the first received operation is one of the first operations or the second operations. A total number of the first plurality of buffers exceeds the maximum.Type: GrantFiled: August 31, 2006Date of Patent: September 11, 2007Assignee: Broadcom CorporationInventor: Joseph B. Rowlands
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Patent number: 7269696Abstract: An architecture provides the ability to create and maintain multiple instances of virtual servers, such as virtual filers (vfilers), within a server, such as a filer. A vfiler is a logical partitioning of network and storage resources of the filer platform to establish an instance of a multi-protocol server. Each vfiler is allocated a subset of dedicated units of storage resources, such as volumes or logical sub-volumes (qtrees), and one or more network address resources. Each vfiler is also allowed shared access to a file system resource of a storage operating system. To ensure controlled access to the allocated and shared resources, each vfiler is further assigned its own security domain for each access protocol. A vfiler boundary check is performed by the file system to verify that a current vfiler is allowed to access certain storage resources for a requested file stored on the filer platform.Type: GrantFiled: April 9, 2003Date of Patent: September 11, 2007Assignee: Network Appliance, Inc.Inventors: Mark Muhlestein, Gaurav Banga
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Patent number: 7269697Abstract: A scheduler to manage the reading activity of a plurality of read hubs is described. Each read hub is capable of reading a piece of a packet from a different memory bank within a same cycle of operation so that pieces of different packets can be read from the memory banks within the same cycle of operation. The scheduler: 1) defines each read hub as an active read hub or inactive read hub, wherein an active read hub is engaged to read at least one packet from the memory banks and an inactive read hub is not so engaged; 2) defines each active read hub as a low speed mode read hub or a high speed mode read hub, wherein, a first packet read by a high speed mode read hub is read from the memory banks at a faster rate than a second packet read by a low speed mode read hub; and, 3) dynamically changes the number of active read hubs, the number of low speed mode read hubs and the number of high speed mode read hubs in light of traffic conditions.Type: GrantFiled: May 7, 2003Date of Patent: September 11, 2007Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Rick Reeve, Richard L. Schober, Ian Colloff
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Patent number: 7269698Abstract: The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.Type: GrantFiled: February 28, 2005Date of Patent: September 11, 2007Assignee: Intel CorporationInventors: Herbert H. J. Hum, James R. Goodman
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Patent number: 7269699Abstract: A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode.Type: GrantFiled: December 12, 2003Date of Patent: September 11, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Seong-Jin Jang
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Patent number: 7269700Abstract: A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating pattern of X control values, wherein X is equal to (M?(M mod N))/N+1. A selector circuit sequentially routes X sets of N flag values from the first stage memory to the flag status bus in response to the repeating pattern of X control values. The X sets of N flag values include the flag values associated with the queues actually used.Type: GrantFiled: January 21, 2005Date of Patent: September 11, 2007Assignee: Integrated Device Technology, Inc.Inventors: Mario Au, Jason Z. Mo, Cheng-Han Wu
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Patent number: 7269701Abstract: A computer program for automatically pairing target resources 20 such as volumes or logical units to source resources 20 containing data to be copied. Available target pools 48, 50, 52, 54 of target volumes are determined eligible for copying based on a technical compatibility and a user-defined metric such as recovery point or recovery time. User defined metrics and a policy to implement the metrics may be stored in a medium and selected by a user. The source volumes are prioritized, and progressively larger segments of the eligible target pools are searched for a target volume that satisfies the technical compatibility and user-defined metric. Where subgroups such as nested volumes are present in the source volumes, subgroups are also prioritized for searching. Where no target volume can be paired, the corresponding source volume is marked as processed and a search begins for the next source volume.Type: GrantFiled: October 10, 2003Date of Patent: September 11, 2007Assignee: International Business Machines CorporationInventors: David Michael Shackelford, Gregory Edward McBride, David Randall Blea, Errol Jay Calder, Todd B. Schlomer, Jimmie Lee Brundidge
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Patent number: 7269702Abstract: A trusted data store is provided for use with a trusted element of a trusted operating system on a computing machine. In the trusted data store, a storage medium stores data in a pre-determined arrangement, where the data includes trusted data from the trusted element of the trusted operating system on the computing machine. An access controller writes data to and reads data from the storage medium, and a trust controller is interposed between the computing machine and the access controller. The trust controller allows only the trusted element to perform operations on the trusted data thereof on the storage medium.Type: GrantFiled: June 6, 2003Date of Patent: September 11, 2007Assignee: Microsoft CorporationInventors: Bryan Mark Willman, Paul England, Keith Kaplan, Alan Stuart Geller, Brian A. LaMacchia, Blair Brewster Dillaway, Marcus Peinado, Michael Alfred Aday, Selena Wilson
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Patent number: 7269703Abstract: A method of migrating data from an old storage subsystem to a new storage subsystem in a data processing system which comprises host computers and storage subsystems. There is provided a route-changing phase before the data is migrated from the old storage subsystem to the new storage subsystem. In the route-changing phase, each host computer can access both the old and new storage subsystems and the new storage subsystem writes data into the old storage subsystem in response to a write request from the host computer and reads data from the old storage subsystem and sends the data to the host computer in response to a read request from the host computer.Type: GrantFiled: September 8, 2006Date of Patent: September 11, 2007Assignee: Hitachi, Ltd.Inventor: Naoki Watanabe
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Patent number: 7269704Abstract: The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit is coupled to an external peripheral by an external data bus. The integrated circuit has a processor coupled to an internal data bus. The system comprises the following. An external bus circuit is coupled to the internal and external data busses. The bus interface circuit is configured to receive read and write signals for data request data. In response, the bus interfaces circuit transmits a wait signal until data from the external peripheral is available on the internal data bus. The wait signal indicates that the external and internal data busses are not available for other purposes. After the processor has received or transmits the data, the bus interface circuit stops transmitting the wait signal and transmits a busy signal. The busy signal indicates that the internal data bus is available and the external data bus is not available for other purposes.Type: GrantFiled: May 11, 2005Date of Patent: September 11, 2007Assignee: Atmel CorporationInventors: Eric Matulik, Nicolas Rescanieres, Anne Lafage
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Patent number: 7269705Abstract: A method for pre-allocating memory for object-based cache data is provided in which request for an object having an associated property parameter that defines the memory requirements for the object. In response, a table of allocation buckets is searched for a bucket having the associated property parameter that can at least meet the memory requirements for the requested object. If an object identifier (OID), having a previously allocated physical address in main memory, is identified in the table of allocation buckets then the identified OID is assigned to the object. The object is stored in the object cache with the assigned OID, and the OID is removed from the bucket. Also included is a table of allocation buckets in a computer system in which each of a plurality of buckets is capable of holding object identifiers (OIDs).Type: GrantFiled: April 23, 2004Date of Patent: September 11, 2007Inventors: Matthew L. Seidl, Gregory M. Wright, Mario I. Wolczko
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Patent number: 7269706Abstract: A method, apparatus and computer program product are disclosed for incrementally checkpointing the state of a computer memory in the presence of at least one executing software application at periodic instants. A secure hash function is periodically applied to each partitioned contiguous block of memory to give a periodic block hash value. At each periodic instant, a block hash value for each block is compared with a respective preceding block hash value to determine if said memory block has changed according to whether said block hash values are different. Only changed memory blocks are stored in a checkpoint record. The memory block sizes are adapted at each periodic instant to split changed blocks into at least two parts and to merge only two non-changed contiguous blocks at a time.Type: GrantFiled: December 9, 2004Date of Patent: September 11, 2007Assignee: International Business Machines CorporationInventors: Saurabh Agarwal, Rahul Garg, Meeta S Gupta
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Patent number: 7269707Abstract: A programmable address decoder is common to the on-chip ROM and on-chip RAM. The programmable address decoder conditionally routes accesses to portions of the ROM to the RAM. The ROM address space is mapped to RAM via a set of configuration registers. This permits patched ROM program code and data table to be stored in on-chip RAM. The patched code and configuration data is stored in an off-chip non-volatile memory. This patch code and the configuration to use is loaded into the RAM and configuration registers on system bootstrap procedure.Type: GrantFiled: January 9, 2004Date of Patent: September 11, 2007Assignee: Texas Instruments IncorporatedInventors: Amitabh Menon, Subash Chandar Govindarajan, Venkatesh Natarajan, Vijay Sindagi
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Patent number: 7269708Abstract: A memory controller includes a first memory interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and a second memory interface adapted to be coupled to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory interface and to direct memory transactions having a predefined second characteristic to the second memory interface. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.Type: GrantFiled: April 20, 2004Date of Patent: September 11, 2007Assignee: Rambus Inc.Inventor: Frederick A. Ware
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Patent number: 7269709Abstract: A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled to a memory system. The plurality of channel control circuits are coupled to receive an indication of whether or not the plurality of channels are ganged. Data is transferred for a first command on each of the plurality of channels responsive to the indication indicating that the plurality of channels are ganged. Responsive to the indication indicating that the plurality of channels are not ganged, data is transferred for the first command on a selected channel of the plurality of channels. In some embodiments, the memory controller may be integrated with one or more processors.Type: GrantFiled: October 11, 2002Date of Patent: September 11, 2007Assignee: Broadcom CorporationInventor: James Daniel Kelly
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Patent number: 7269710Abstract: A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an expanded portion. An N-bit program counter increments through instructions stored only in the regular portion. Constants are stored in both the regular and expanded portions. An M-bit page-designator is prepended to an N-bit operand to generate a memory address of N+M bits. Program memory is expanded only when a load instruction retrieves constants from program memory. The page-designator is toggled when an N-bit operand rolls over upon incrementing by the load instruction. A block of constants straddling the boundary between the regular and expanded portions can be retrieved from program memory by executing only the load instruction. When program instructions are executed that do not retrieve constants, a fixed page-designator designates the regular portion.Type: GrantFiled: July 23, 2004Date of Patent: September 11, 2007Assignee: ZiLOG, Inc.Inventor: Stephen H. Chan
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Patent number: 7269711Abstract: Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.Type: GrantFiled: December 29, 2003Date of Patent: September 11, 2007Assignee: Intel CorporationInventors: Rajesh B. Patel, Robert L. Farrell, James E. Phillips, Belliappa Kuttanna, Scott E. Siers, T. W. Griffith
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Patent number: 7269712Abstract: A simultaneous multithreading processor determines, for each thread, the processing time occupied by each thread in the processing pipeline of the processor. Based on the determined processing times, a fetch unit in the processing pipeline determines the thread from which to fetch the next instruction.Type: GrantFiled: January 12, 2004Date of Patent: September 11, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Jang-Ho Cho
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Patent number: 7269713Abstract: A method and apparatus for controlling issue rate of instructions for an instruction thread to be executed by a processor is provided. The rate at which instructions are to be executed for an instruction thread are stored (46) and requests are issued (44) to cause instructions to execute in response to the stored rate. The rate at which instruction requests are issued is reduced in response to instruction executions and is increased in the absence of instruction executions. In a multi-threaded processor, instruction rate is controlled by storing the average rate at which each thread should execute instructions (48). A value representative of the number of instructions available and not yet issued is monitored and is decreased in response to instruction executions (42). Execution of instructions is prevented on a thread if the number of instructions available but not yet issued falls below a defined value.Type: GrantFiled: February 19, 2002Date of Patent: September 11, 2007Assignee: Imagination Technologies LimitedInventors: Adrian John Anderson, Martin John Woodhead
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Patent number: 7269714Abstract: A processor is described which includes a first pipeline, a second pipeline, and a control circuit. The first pipeline includes a first stage at which instruction results are committed to architected state. The first stage is separated from an issue stage of the first pipeline by a first number of stages. The second pipeline includes a second stage at which an exception is reportable, wherein the second stage is separated from the issue stage of the second pipeline by a second number of stages which is greater than the first number. The control circuit is configured to inhibit co-issuance of a first instruction to the first pipeline and a second instruction to the second pipeline if the first instruction is subsequent to the second instruction in program order.Type: GrantFiled: February 4, 2002Date of Patent: September 11, 2007Assignee: Broadcom CorporationInventors: Tse-Yu Yeh, David A. Kruckemyer, Robert Rogenmoser