Patents Issued in February 19, 2008
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Patent number: 7334078Abstract: One aspect of the present invention leads to a method of handling streaming information. The method includes receiving the streaming information and analyzing the streaming information to locate one or more points of interest in the streaming information. An index of the one or more points of interest are generated. The index is delivered to a user separate from the streaming information. Rendering of the streaming information is controlled based on the points of interest.Type: GrantFiled: April 1, 2005Date of Patent: February 19, 2008Assignee: Microsoft CorporationInventors: William G. Parry, Mingtzong Lee, Christopher W. Lorton, Jayachandran Raja, Serge Smirnov
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Patent number: 7334079Abstract: A method for operating a storage system configured to provide a Write Once and Read Many (WORM) function includes receiving a first command at a storage subsystem from a host. At least a portion of the first command is stored on a WORM storage device coupled to the storage subsystem. A second command is received at the storage subsystem. The second command is examined using a command filter, the filter being provided with a predetermined rule for filtering selected types of commands. At least a portion of the second command is stored if the second command satisfies the predetermined rule. The WORM storage device is used to verify the WORM function of the storage system.Type: GrantFiled: December 28, 2006Date of Patent: February 19, 2008Assignee: Hitachi, Ltd.Inventor: Yuichi Yagawa
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Patent number: 7334080Abstract: A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside.Type: GrantFiled: November 15, 2002Date of Patent: February 19, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Stystems Co., Ltd.Inventors: Yoshinori Takase, Keiichi Yoshida, Takashi Horii, Atsushi Nozoe, Takayuki Tamura, Tomoyuki Fujisawa, Ken Matsubara
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Patent number: 7334081Abstract: An RPO algorithm in a HDD coalesces LBA-sequential XOR commands in pipes, and passes the pipes to a lower level execution engine. The execution engine executes XOR reads and write separately to optimize performance using head and/or cylinder skew information to approach the nominal disk data rate.Type: GrantFiled: April 29, 2005Date of Patent: February 19, 2008Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Adam Michael Espeseth, Edward Henry Younk
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Patent number: 7334082Abstract: A method and system to detect an occurrence of a predetermined event within the system, and change a power state of a hard drive (HD) in response to the event, are described. In one embodiment, in response to detecting consecutive HD reads have been satisfied by a non-volatile cache (NVC) of the HD, for at least a predetermined period of time, or detecting that a predetermined quantity of consecutive HD reads have been satisfied by the NVC, spinning down the HD. In an alternative embodiment, in response to detecting a predetermined number of HD data transactions have been serviced by the NVC or the HD, canceling a planned spinning down of the HD or spinning up the HD.Type: GrantFiled: December 30, 2003Date of Patent: February 19, 2008Assignee: Intel CorporationInventors: Andrew S. Grover, Guy Therien, Brian A. Leete
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Patent number: 7334083Abstract: In a library system in which a virtual library apparatus is interposed between a library apparatus and a data processing apparatus, a collecting means collects access states to a logical volume from the data processing apparatus, a database retains the access states, and a restoring means determines a restoration priority of the logical volume on the basis of the access state, reads out the logical volume from a physical volume retaining the logical volume onto a cache according to the restoration priority, thereby restoring the logical volume to be held in the cache. Even immediately after the cache of the virtual library apparatus is replaced with another new cache, it is possible to avoid a case where the response speed to a mount request (processing request) from the data processing apparatus becomes slower than the response speed during the normal operation before replacement of the cache.Type: GrantFiled: February 11, 2005Date of Patent: February 19, 2008Assignee: Fujitsu LimitedInventor: Koichi Doi
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Patent number: 7334084Abstract: Resources of a storage apparatus are utilized effectively by increasing and reducing a capacity of a differential LU used in a snapshot. In a disk array apparatus including a control processor which controls reading and writing of data with respect to a first logical volume which is generated using storage areas of a plural disk drives, performs control such that data in the past stored in the first logical volume is written in a second logical volume as differential data for each generation, and manages the differential data, the control processor manages a pool management table, in which a logical volume usable as the second logical volume is registered, and a pool addition object management table, in which a logical volume which can be added to the second logical volume is registered, and moves the logical volume from the pool addition object management table to the pool management table to thereby increase a capacity of the second logical volume.Type: GrantFiled: September 7, 2006Date of Patent: February 19, 2008Assignee: Hitachi, Ltd.Inventor: Koji Nagata
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Patent number: 7334085Abstract: A method for memory management in an electronic device includes receiving partial content data records at the electronic device, storing the partial content data records in a memory of the electronic device, receiving a full content data record corresponding to one of the partial content data records, determining whether or not sufficient memory is available in the memory of the electronic device to store the full content data record and, if so, writing the full content data record over the corresponding partial content data record stored in the memory; and repeating the receiving and determining until either: full content data records corresponding to each of the partial content data records are received; or a low memory condition is determined in the memory. The partial content data records include key fields of data sufficient for uniquely identifying corresponding full content data records at a second electronic device.Type: GrantFiled: November 23, 2005Date of Patent: February 19, 2008Assignee: Research In Motion LimitedInventors: Piotr K. Tysowski, Michael T. Hardy
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Patent number: 7334086Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: GrantFiled: July 23, 2004Date of Patent: February 19, 2008Assignee: RMI CorporationInventors: David T. Hass, Abbas Rashid
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Patent number: 7334087Abstract: A method of caching contextually variant objects in a common cache. The method can include identifying an object type for a requested object and determining whether the requested object has an object type which is specified among an enumerated set of cacheable object types which can be stored in the common cache. Importantly, each cacheable object type can have an associated context. If the requested object has an object type which is specified among the enumerated set of cacheable object types, a cache key can be computed for the requested object using cache key formulation rules for the associated context. Finally, the requested object can be retrieved from the common cache using the formulated cache key. Notably, in one aspect of the invention, the method also can include the step of invalidating individual objects in the common cache according to corresponding cache policies of associated contexts.Type: GrantFiled: February 8, 2005Date of Patent: February 19, 2008Assignee: International Business Machines CorporationInventors: Gennaro A. Cuomo, Brian Keith Martin, Donald F. Ferguson, Daniel C. Shupp, Goran D. Zlokapa
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Patent number: 7334088Abstract: A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a main memory, wherein each page in the main memory has associated with it a tag, which is used for controling the prefetching of a variable subset of lines from this page as well as lines from at least one other page. And, coupled to the processor is a prefetch controller, wherein the prefetch controller responds to the processor determining a fault (or miss) occurred to a line of data by fetching a corresponding line of data with the corresponding tag, with the corresponding tag to be stored in the prefetch buffer, and sending the corresponding line of data to the cache memory.Type: GrantFiled: December 20, 2002Date of Patent: February 19, 2008Assignee: International Business Machines CorporationInventor: Peter Franaszek
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Patent number: 7334089Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing remote data caches associated with the various clusters in the system. The remote data caches receive data and state information for memory lines held in remote clusters. State information is provided to the remote data cache using various mechanisms including a coherence directory and augmented source done messages.Type: GrantFiled: May 20, 2003Date of Patent: February 19, 2008Assignee: Newisys, Inc.Inventor: David Brian Glasco
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Patent number: 7334090Abstract: Embodiments relate to a method, system, and storage medium for providing information storage services to a service application user via a service provider. The method includes presenting options to the service application user operable for specifying a duration of time for storing an information element at a remote location. The method further includes receiving a selection from the service application user in response to options presented and assigning a storage period to the information element based upon the selection. Embodiments also include a system and a storage medium.Type: GrantFiled: December 17, 2003Date of Patent: February 19, 2008Assignee: AT&T Delaware Intellectual Property, Inc.Inventor: Samuel N. Zellner
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Patent number: 7334091Abstract: The present disclosure includes systems and techniques relating to FIFO queue memory. In general, in one implementation, a queue memory receives and stores information and supports first-in-first-out read and out-of-order read operations with information shifting within the memory relative to a read operation. The queue memory can include a write pointer that increments upon a write operation and decrements upon the read operation, a read pointer that identifies an oldest read entry of the queue memory when the read operation is a first-in-first-out read and that identifies a selected entry of the queue memory when the read operation is an out-of-order read, and a multiplexer operative to select entries of the queue memory responsive to the read pointer.Type: GrantFiled: June 22, 2004Date of Patent: February 19, 2008Assignee: Marvell Semiconductor Israel Ltd.Inventor: Noam Mizrahi
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Patent number: 7334092Abstract: During sampling intervals, pairs of swap scores are assigned to respective pairs of storage devices of a storage system, each swap score pair indicating an amount of system performance improvement for a swap of logical volumes between source and target storage devices of the pair of storage devices. The swap scores are summed over all the intervals. A subset of the storage devices are then selected for a full optimization process based on the summed swap scores, where the full optimization process exhaustively looks for some number of best swaps among the storage devices to improve system performance. By choosing the size of the subset of storage devices, the processing burden required to perform the analysis will be in line with the processing capacity of the processing platform on which the analysis is performed, while achieving system performance improvement commensurate with a worst-case process in which every storage device in the system is analyzed for candidate swaps.Type: GrantFiled: March 23, 2005Date of Patent: February 19, 2008Assignee: EMC CorporationInventors: Hui Wang, Ron Arnan, Tao Kai Lam
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Patent number: 7334093Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.Type: GrantFiled: February 12, 2007Date of Patent: February 19, 2008Assignee: MOSAID Technologies IncorporatedInventors: Alan Roth, Sean Lord, Robert Mckenzie, Dieter Haerle, Steven Smith
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Patent number: 7334094Abstract: A clone splitting technique enables efficient online splitting of blocks shared between a parent virtual volume (vvol) and a clone in accordance with a shared block splitting procedure executing on a storage system. Online splitting of shared blocks denotes allowing execution of read/write operations directed to the clone, as well as to the parent vvol, as the shared blocks are split. The clone splitting technique removes any connection between a clone and its parent vvol, thereby allowing the clone to be used as a first-class volume. Moreover, the technique removes such connection while allowing both the clone and parent vvol to remain available online and writeable (accessible) to clients during the shared block splitting procedure.Type: GrantFiled: April 30, 2004Date of Patent: February 19, 2008Assignee: Network Appliance, Inc.Inventor: Robert L. Fair
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Patent number: 7334095Abstract: A system and method creates a writable clone of a read-only volume. A base snapshot is generated on a source volume on a source storage system and is duplicated as a read-only base snapshot replica on a target volume on a destination storage system. A copy (“clone) is then substantially instantaneously created from the read-only base snap-shot replica, thereby creating a writable clone of a read-only volume.Type: GrantFiled: April 30, 2004Date of Patent: February 19, 2008Assignee: Network Appliance, Inc.Inventors: Robert L. Fair, John K. Edwards
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Patent number: 7334096Abstract: An architecture and apparatus for atomic operations across multi-volume or multi-LUNs in a data storage environment. It is difficult to manage data storage and replication operations occurring across such multi-LUNs. The architecture and apparatus embodiments of the invention overcome these deficiencies and facilitate data storage management and replication operations through library initializations in response to host I/O requests to complete atomic operations. Accordingly, the invention ensures the integrity of the data being managed without introducing significant cost or overhead.Type: GrantFiled: March 31, 2005Date of Patent: February 19, 2008Assignee: EMC CorporationInventors: Michael L. Burriss, Michael P. Wagner, Alan L. Taylor, William P. Hotle
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Patent number: 7334097Abstract: Disclosed herein is a method for controlling a storage device controller connected to a storage device provided with a plurality of storage volumes for storing data respectively and an information processing apparatus for requesting an input/output of data so as to receive an input/output request from the information processing apparatus and execute an input/output processing of the data for each of the plurality of storage volumes. The method brings one (primary) of the plurality of storage volumes into correspondence with another (secondary) in which a copy of data is to be written when the data is written in the primary volume so as to form a pair group consisting of a plurality of pairs, each having such a primary volume and such a secondary volume.Type: GrantFiled: March 27, 2006Date of Patent: February 19, 2008Assignee: Hitachi, Ltd.Inventors: Susumu Suzuki, Masanori Nagaya, Takao Sato
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Patent number: 7334098Abstract: Computer systems may lose data when a failure occurs within a system. To counteract such loss of data a backup system may be employed. Common backup systems make a copy of either of the data on a storage device or the data, which has changed, on a storage device. The process of backing up data may involve storing a relatively large amount of data and so is commonly done infrequently, such as once per day. If a computer's data is backed up only once per day, several hours of data may be lost if a computer system fails. Embodiments of the present invention may be used to prevent this type of data loss by backing up more frequently. In order to back up more frequently less data at a time is backed up. Instead of the data undergoing a wholesale backup infrequently, embodiments of the present invention form a timed log of the storage writes performed by the computer system. The log provides a running picture of activity to the computer storage system.Type: GrantFiled: June 6, 2000Date of Patent: February 19, 2008Assignee: Quantum CorporationInventor: Lloyd Alan Poston
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Patent number: 7334099Abstract: A method and system for managing image files is provided. The image files include a plurality of streams such as a control stream, a data stream, a bitmap stream, and a cluster map stream. An audit trail stream, properties stream and fix-up stream may also be provided. An image driver translates requests from the operating system so that the image can be read, edited or otherwise manipulated.Type: GrantFiled: June 28, 2002Date of Patent: February 19, 2008Assignee: Microsoft CorporationInventors: Wesley A. Witt, Sara J. Schumacher, Kartik N. Raghavan
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Patent number: 7334100Abstract: A storage system includes a network adapter, a channel adapter, a shared memory, a cache memory, a disk adapter, a switch and a storage device. The storage device stores data. The network adapter includes a port connected to a local area network, and a NAS processor and an I/O processor. The NAS processor receives a file access request via the port, and gives instructions to access the data stored in the storage device as well as instructions to back up the data stored in the storage device. The I/O processor transfers access to the data stored in the storage device to the cache memory, and transfers backup instructions for the data stored in the storage device to the shared memory. The channel adapter includes a port and an I/O processor. The I/O processor sends out data stored in the storage device to the device storing backup data, in response to a backup instruction from the network adapter.Type: GrantFiled: December 17, 2004Date of Patent: February 19, 2008Assignee: Hitachi, Ltd.Inventors: Naotaka Kobayashi, Shizuo Yokohata
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Patent number: 7334101Abstract: A method for copying data to multiple remote sites includes transmitting data from a first volume in a primary storage system to a back-up volume provided in a secondary storage system. The primary storage system is located at a primary site, and the secondary storage system is located at a first remote site from the primary site. The data from the first volume in the primary storage system is copied to a second volume in the primary storage system using a point in time (PiT) as a reference point of time for the copying. The second volume is provided with a first time consistent image of the first volume with respect to the reference point of time. The data from the second volume in the primary storage system is transferred to a third volume in a ternary storage system at a second remote site.Type: GrantFiled: August 24, 2006Date of Patent: February 19, 2008Assignee: Hitachi, Ltd.Inventors: Yuichi Yagawa, Naoki Watanabe, Shigeru Kishiro
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Patent number: 7334102Abstract: A data processor (300) is adapted for use in a non uniform memory access (NUMA) data processing system (10) having a local memory (320) and a remote memory. The data processor (300) includes a central processing unit (302) and a communication link controller (310). The central processing unit (302) executes a plurality of instructions including an atomic instruction on a lock variable, and generates an access request that includes a lock acquire attribute in response to executing the atomic instruction on the lock variable. The communication link controller (310) is coupled to the central processing unit (302) and has an output adapted to be coupled to the remote memory, and selectively provides the access request with the lock acquire attribute to the remote memory if an address of the access request corresponds to the remote memory.Type: GrantFiled: May 9, 2003Date of Patent: February 19, 2008Assignee: Advanced Micro Devices, Inc.Inventor: Patrick Conway
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Patent number: 7334103Abstract: A method for breathing of scheduling algorithms for a storage device (110). The method including: (a) computing a worst-case duration of a breathing cycle (P) for the storage device (110); (b) starting a breathing cycle; (c) determining if one of the following becomes true before the end of P: (i) a number of real-time requests is at least a predetermined threshold based on a number of data streams and performance parameters of the storage device; and (ii) a number of pending requests for any single stream becomes more than one; (d) if at least one of (i) and (ii) remain true during the duration of P, starting a subsequent breathing cycle after completion of the breathing cycle; and (e) if both of (i) and (ii) are not true during the duration of P, waiting P time units from the start of the breathing cycle before starting the subsequent breathing cycle.Type: GrantFiled: December 8, 2003Date of Patent: February 19, 2008Assignee: Koninklijke Philips Electronics N.V.Inventors: Johannes H. M. Korst, Hong Li, Robert Jochemsen, Nicolaas Lambert, Gerardus W. T. Van Der Heijden
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Patent number: 7334104Abstract: Memory allocation requests are satisfied from a memory pool or from lookaside lists, based on the memory size requested to be allocated. A method, for each of a number of future differently sized memory allocations, determines which memory allocations are to be satisfied from a lookaside list, and which memory allocations are to be satisfied from a memory pool. For each memory allocation to be satisfied from a lookaside list, a corresponding lookaside list for the allocation is initialized. A table is constructed that has a number of entries corresponding to all the differently sized memory allocations. Each entry corresponding to a memory allocation to be satisfied from a lookaside list points to the lookaside list for that memory allocation.Type: GrantFiled: November 20, 2004Date of Patent: February 19, 2008Assignee: International Business Machines CorporationInventors: Scott A. Piper, Vikas Ahluwalia, Vipul Paul
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Patent number: 7334105Abstract: A method for managing a memory of a computer system to store a data of a first size, comprising the steps of defining chunks of the memory, wherein each chunk is a continuous memory space of a predetermined size. Defining chunk pools for managing the chunks, wherein each chunk pool corresponds to chunks of a particular size and defining unit pools for managing units of the first size, wherein the chunk pool corresponding to the unit pool provides a chunk of the particular size to be separated into the units of the first size, and the data of the first size is stored in the units.Type: GrantFiled: May 6, 2004Date of Patent: February 19, 2008Assignee: Wind River Systems, Inc.Inventors: Kadir Ozdemir, Shankar Jayaraman
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Patent number: 7334106Abstract: In a storage system having a plurality of virtualization apparatuses that allocate a storage area which a storage device has, form a plurality of virtual volumes, and process input-output from a host processor to one of the virtual volumes, a request for completing all the input-output being processed that is received from the host processor and temporarily holding the input-output processing received subsequently is issued to the plurality of virtualization apparatuses, when a completion report of the processing of the input-output in response to the request is received from the plurality of virtualization apparatuses and the completion report is received from all the virtualization apparatuses to which the request was issued, an instruction of an allocation change of the storage area of the storage device is sent to all the virtualization apparatuses, and when the completion report of the allocation change is received from all the virtualization apparatuses, the storage area of the storage device is allocatType: GrantFiled: October 30, 2006Date of Patent: February 19, 2008Assignee: Hitachi, Ltd.Inventors: Kazuyoshi Serizawa, Norio Shimozono, Yasutomo Yamamoto, Naoko Iwami
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Patent number: 7334107Abstract: An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physical address corresponds to a guest domain identified by a guest domain identifier in an input/output (I/O) transaction requested by an I/O device. A register stores an invalidating domain identifier identifying an invalidating domain and an indicator indicating invalidating an entry in the cached entries having a tag.Type: GrantFiled: September 30, 2004Date of Patent: February 19, 2008Assignee: Intel CorporationInventors: Ioannis Schoinas, Rajesh Madukkarumukumana, Gilbert Neiger, Richard Uhlig, Balaji Vembu
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Patent number: 7334108Abstract: A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. Recently retrieved clusters are stored in an on-chip cache, and a cached cluster can be used to translate any virtual address in its range without accessing the address translation table again.Type: GrantFiled: January 30, 2004Date of Patent: February 19, 2008Assignee: NVIDIA CorporationInventors: Colyn S. Case, Dmitry Vyshetsky, Sean J. Treichler
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Patent number: 7334109Abstract: A method and apparatus for breaking complex X86 segment operations and segmented addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations.Type: GrantFiled: December 30, 2004Date of Patent: February 19, 2008Inventors: H. Peter Anvin, Alex Klaiber, Guillermo J. Rozas, Parag Gupta
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Patent number: 7334110Abstract: In a computer system having a scalar processing unit and a vector processing unit, wherein the vector processing unit includes a vector dispatch unit, a system and method of decoupling operation of the scalar processing unit from that of the vector processing unit, the method comprising sending a vector instruction from the scalar processing unit to the vector dispatch unit, wherein sending includes marking the vector instruction as complete if the vector instruction is not a vector memory instruction and if the vector instruction does not require scalar operands, reading a scalar operand, wherein reading includes transferring the scalar operand from the scalar processing unit to the vector dispatch unit, predispatching the vector instruction within the vector dispatch unit if the vector instruction is scalar committed, dispatching the predispatched vector instruction if all required operands are ready, and executing the dispatched vector instruction as a function of the scalar operand.Type: GrantFiled: August 18, 2003Date of Patent: February 19, 2008Assignee: Cray Inc.Inventors: Gregory J. Faanes, Steven L. Scott, Eric P. Lundberg, William T. Moore, Jr., Timothy J. Johnson
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Patent number: 7334111Abstract: The invention provides for a method and related device and control program for use in decoding executable code in a processing system, for example run-time operating system, including bit-shuffling code at run-time, and including the steps of dividing the code into a plurality of sub-portions, identifying sub-portions of the code that can be bit-shuffled prior to the said run-time and bit-shuffling the said identified sub-portions prior to run-time so as to reduce the bit-shuffling required at run-time.Type: GrantFiled: January 11, 2005Date of Patent: February 19, 2008Assignee: NXP B.V.Inventor: Colin I. King
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Patent number: 7334112Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.Type: GrantFiled: November 6, 2003Date of Patent: February 19, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Achmed Rumi Zahir, Cary A. Coutant, Carol L. Thompson, Jonathan K. Ross
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Patent number: 7334113Abstract: The present invention provides a method and system for processing an instruction set, which can be applied to compress the operation part of a sequence of instructions in the instruction set and to perform the corresponding decompression. Upon the compression, the sequence of instructions is divided into a operation part and a register part, then recursively compress consecutive instructions with two operation codes that emerge repeatedly in the sequence of instructions until no further compression can be performed. The compression leads to form a binary tree which constitutes of nodes corresponding to the original operation codes or the ones derived from them in the recursive compression process. Furthermore, a pre-fetch mechanism is used in the present invention to promote the performance upon decompression.Type: GrantFiled: September 7, 2005Date of Patent: February 19, 2008Assignee: National Chung Cheng UniversityInventors: Rong-Guey Chang, Shao-Yang Wang
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Patent number: 7334114Abstract: A system and method of tracing a group of processor events in real-time in order to enable a programmer to debug and profile the operation and execution of code on the processor. This may be accomplished by running one or more traces on the same or different groups of processor events in order to gain a full understanding of how code is being executed by the processor.Type: GrantFiled: May 15, 2006Date of Patent: February 19, 2008Assignee: Texas Instruments IncorporatedInventors: Oliver P Sohm, Gary L. Swoboda, Manisha Agarwala
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Patent number: 7334115Abstract: The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.Type: GrantFiled: June 30, 2000Date of Patent: February 19, 2008Assignee: Intel CorporationInventors: Reynold V. D'Sa, Alan B. Kyker, Slade A. Morgan, Rebecca E. Hebda, Richard A. Weier, Robert F. Krick
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Bit manipulation on data in a bitstream that is stored in a memory having an address boundary length
Patent number: 7334116Abstract: A bit manipulation processor, system and method are provided which reduces the number of operations performed during data processing. An additional register is used as a buffer. The buffer has a bit length which is preferably greater than the address boundaries in a memory or register address. A bitstream can be processed using the buffer by itself or in combination with a standard register, depending upon the particular function to be implemented.Type: GrantFiled: October 6, 2004Date of Patent: February 19, 2008Assignee: Sony Computer Entertainment Inc.Inventor: Eiji Iwata -
Patent number: 7334117Abstract: System and method for loading and/or updating firmware in a device, e.g., an embedded device, operable to be coupled to a host computer system. A first portion of firmware of the device, e.g., a boot loader, may be executable to operate the device, including processing requests from the host computer system and/or enabling the device to execute a second portion of the firmware, e.g., an operating system for the device. The device may be coupled to other devices or instruments. The second portion of the firmware may allow the host computer system to operate and/or control the other devices or instruments through the device. The host computer system may transmit a different version of the second portion of the firmware to the device, e.g., enabling the device to couple to and operate with a specific instrument. The host computer system may not update the first portion of the firmware.Type: GrantFiled: August 4, 2004Date of Patent: February 19, 2008Assignee: National Instruments CorporationInventors: Daniel B. Wilson, Craig A. Aiken
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Patent number: 7334118Abstract: A computer reset method activated by a South Bridge to directly reset a Central Processing Unit (CPU). First, a trigger signal is received. A CPU reset signal is delivered by the South Bridge when receiving the trigger signal. Thereafter, the CPU is reset when receiving the CPU reset signal from the South Bridge via a North Bridge.Type: GrantFiled: May 10, 2005Date of Patent: February 19, 2008Assignee: Via Technologies, Inc.Inventors: Hsiu-Ming Chu, Kuan-Jui Ho
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Patent number: 7334119Abstract: A method, system, and program product that enables a computer user to access their own complete computer environment and software on a separate and distinct host computer. The visiting user's data including files, settings, environment, software, are all packed in a single file.Type: GrantFiled: November 14, 2006Date of Patent: February 19, 2008Assignee: Cisco Technology, Inc.Inventors: Gregoire Alexandre Gentil, Alireza Malekzadeh
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Patent number: 7334120Abstract: A method and apparatus to execute a pre-boot application within an emulated pre-boot environment to test functionality of the pre-boot application. The emulated pre-boot environment is executed within a user mode of an operating system (“OS”) during an OS runtime of the processing system. The pre-boot application interacts with a hardware device of the processing system via a kernel proxy agent. The kernel proxy agent executes in a kernel mode of the OS.Type: GrantFiled: November 14, 2003Date of Patent: February 19, 2008Assignee: Intel CorporationInventors: Michael A. Rothman, Vincent J. Zimmer, Mark S. Doran, Andrew J. Fish, Michael D. Kinney
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Patent number: 7334121Abstract: A flash memory that shares a booting function and a booting program, and an apparatus and method for protecting the same in an AT Attachment Packet Interface (ATAPI) drive. The flash memory includes a first boot zone, where a booting program is stored, a second boot zone, where a backup of the booting program is stored, and a data zone, where an executable and downloaded firmware program is stored, wherein the corresponding booting program in either of the first or second boot zones which has no error is executed when an error is detected in the alternate first or second boot zone. Accordingly, it is possible to restore a flash memory damaged due to some external cause to its original state, thereby reducing costs for replacement of the damaged flash memory.Type: GrantFiled: November 25, 2003Date of Patent: February 19, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Ki-Ju Lee
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Patent number: 7334122Abstract: A system for and method of network booting of an operating system (O/S) on one or more client devices, such as personal computers (PC's), employing a hibernation image. Remote booting of sets of client devices is facilitated by employing virtual disk emulation and, in certain preferred embodiments, broadcasting or multicasting of data residing on a network server which is necessary to appropriately boot and configure the one or more client devices, the data including hibernation, O/S and application files.Type: GrantFiled: August 9, 2005Date of Patent: February 19, 2008Assignee: Ardence, Inc.Inventors: Gintautas Burokas, Kenny Bunch, Robert Lusinsky, Marc Sandusky, Mike Garelick
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Patent number: 7334123Abstract: A computer system including a bus bridge for bridging transactions between a secure execution mode-capable processor and a security services processor. The bus bridge may include a transaction source detector, a configuration header and control logic. The transaction source detector may receive a security initialization transaction performed as a result of execution of a security initialization instruction. Further, the transaction source detector may determine whether the secure execution mode-capable processor is a source of the security initialization transaction. The configuration header may provide storage of information associated with the security services processor. The control logic may determine whether the security services processor is coupled to the bus bridge via a non-enumerable, peripheral bus.Type: GrantFiled: May 2, 2003Date of Patent: February 19, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Dale E. Gulick, Geoffrey S. Strongin, Larry D. Hewitt
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Patent number: 7334124Abstract: Network data files are secure through the operation of an infrastructure gateway-based network file access appliance. Network file data, corresponding to network pocket payload data, are further reduced to a sequence of data blocks that are secured through any combination of block encryption, compression, and digital signatures. File meta-data, including encryption, compression and block-level digital signatures are persistently stored with the file data, either in-band in the file as stored or out-of-band key as a separately stored file or file policy record. File meta-data is recovered with accesses of the file data to support bidirectional encryption and compression and to detect tampering with the file data by comparison against block-level digital signatures.Type: GrantFiled: July 22, 2002Date of Patent: February 19, 2008Assignee: Vormetric, Inc.Inventors: Duc Pham, Tien Le Nguyen, Pu Paul Zhang, Mingchen Lo
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Patent number: 7334125Abstract: An approach for facilitating secure communications among multicast nodes in a telecommunications network is disclosed. A source node sends an encryption key and an identifier to an authoritative node that stores the encryption key and associates the identifier with the encryption key. The source node encrypts data using the encryption key and sends the encrypted data with the identifier in a multicast. The multicast destination nodes retrieve the encryption key from the authoritative node based on the identifier and then decrypt the multicast. A list of administrative nodes, a list of authorized nodes, and an expiration time may be used to manage the encryption key. The authoritative node may be a certificate authority or key distribution center, and the source node may encrypt the multicast using the Internet security protocol (IPsec) or secure socket layer (SSL). Thus, communications among multicast nodes may be efficiently secured in a scalable manner.Type: GrantFiled: November 27, 2001Date of Patent: February 19, 2008Assignee: Cisco Technology, Inc.Inventor: Chinna Narasimha Reddy Pellacuru
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Patent number: 7334126Abstract: The present invention provides authorized users access to sensitive information on internal servers inside a firewall while protecting the information from others. A strong client authentication mechanism is layered on top of a secure communication protocol to allow legitimate users access to an internal server from outside the firewall. A proxy is provided with an external component outside the firewall and an internal component inside the firewall, with a control communication channel established between the two. The external component forwards messages through the firewall to the internal component which handles user authentication and acts as a proxy between the user and the internal servers. Where the returned resource contains document hyperlinks, the links are translated into references to the proxy, permitting the user a seamless experience that is almost exactly the same whether the user is inside or outside the firewall.Type: GrantFiled: February 1, 2000Date of Patent: February 19, 2008Assignee: AT&T Corp.Inventors: Christian A. Gilmore, David P. Kormann, Aviel D. Rubin
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Patent number: 7334127Abstract: A key establishment protocol includes the generation of a value of cryptographic function, typically a hash, of a session key and public information. This value is transferred between correspondents together with the information necessary to generate the session key. Provided the session key has not been compromised, the value of the cryptographic function will be the same at each of the a correspondents. The value of the cryptographic function cannot be compromised or modified without access to the session key.Type: GrantFiled: May 16, 2003Date of Patent: February 19, 2008Assignee: Certicom Corp.Inventor: Marinus Struik