Abstract: An image decrypting apparatus derives spectral reflectance of the face of an original on the basis of obtained original image data, built-in light source data and basis function data, and obtains weighted coefficients of each pixel as object color component data. The apparatus stores a file including the basis function data used at the time of obtaining the spectral reflectance as a key file, and stores a file including the object color component data as an encrypted file. From each of the key file and the encrypted file, the original image data cannot be reproduced. By using the key file and the encrypted file in a correct combination, the original image data can be reproduced. In such a manner, the original image data can be protected.

Abstract: A system and method for detecting if an object has been tampered with comprising a characterizer, a comparator, and indicator, and optionally, a signer. The characterizer generates a first digital characterization of an object at a first time and at least one subsequent digital characterization of the object at at least one subsequent time. The comparator compares the first digital characterization with the at least one subsequent digital characterization, and the indicator generates a pre-selected characterization signal if the first and subsequent digital characterizations don't match. Optionally, the first digital characterization can be accompanied by a first digital signature. The signer optionally verifies the digital signature at the at least one subsequent time.

Abstract: A method for enabling a personal computer to be authenticated by a server is provided. The method comprises the step, which includes for the user in launching the execution of a log-on procedure software, introducing personal identifiers providing access to a signature private key for long-term use relative to the duration of the session. The log-on procedure software produces: identification data of the session Id, a public ephemeral module, a public exponent and at least a pair of ephemeral pubic numbers and ephemeral private numbers related by a generic equation of the type: Gi?Qiv (mod n) or Gi·Qiv?1 (mod n), an ephemeral certificate linking, by means of said signature private key, Id and public ephemeral module. The public ephemeral module is of reduced size relative to the signature private key.

Abstract: A method and a system for authentication and synchronization is disclosed. The user provides a first one time code (OTC) to the authentication manager. If this OTC is within a small access window, the user is directly authenticated and granted access to the system. If the provided OTC is outside the small window but within a big window, the authentication manager saves the first OTC, and a second OTC is required from the user. If the new, second OTC and the first OTC are in sequence, the end user will be authenticated, and admitted access to the system and the requested service.

Abstract: A Feistel encryption apparatus having a plurality of steps of accepting unstirred text, stirring with an extended key, and calculating stirred text for encrypting plaintext step by step, the apparatus is allowed to utilize cryptanalysis conditions held at given predetermined steps, and decryption with higher order differences determined from stirred text at these steps is allowed. The invention can secure all the estimated extended keys including the last-step extended key to be right with a desired probability as well as it allows decryption by less complexity. The invention allows MISTY1 with six rounds without an FL function to be decrypted with 239 of selected plaintext and the complexity of 249 of an FO function. It also allows MISTY1 with seven rounds without the FL function to be decrypted with 239 of selected plaintext and the complexity of 2124 of the FO function.

Abstract: An integrated, modular array of administrative and support services are provided for electronic commerce and electronic rights and transaction management. These administrative and support services supply a secure foundation for conducting transaction-related capabilities functioning over electronic network-s, and can also be adapted to the specific needs of electronic commerce value chains. In one embodiment, a Distributed Commerce Utility having a secure, programmable, distributed architecture provides administrative and support services. The Distributed Commerce Utility may comprise a number of Commerce Utility Systems. These Commerce Utility Systems provide a web of infrastructure support available to, and reusable by, the entire electronic community and/or many of its participants. Different support functions can be collected together in hierarchical and/or networked relationships to suit various business models or other objectives.

Abstract: Obfuscating an application program comprises reading an application program comprising code, transforming the application program code into transformed application program code that uses one of multiple opcode value encoding schemes of a dispatch table associated with the application program, and sending the transformed application program code. Executing an obfuscated application program comprises receiving an obfuscated application program comprising at least one instruction opcode value encoded using one of multiple instruction set opcode value encoding schemes, determining a dispatch table associated with the application program, and executing the application program using the associated dispatch table. The dispatch table corresponds to the one of multiple instruction set opcode value encoding schemes.

Abstract: A recording disc has a lead-in area and a data area. A scrambled version of a SID code word is read out from the lead-in area of the disc. The SID code word represents a producer of the disc. The readout scrambled version is de-scrambled to recover the SID code word. The recovered SID code word is collated with reference SID code words to decide whether or not the disc is legitimate. Main information is read out from the data area of the disc when it is decided that the disc is legitimate. Readout of the main information from the data area of the disc is inhibited when it is decided that the disc is not legitimate.

Abstract: In accordance with certain aspects, a chain of trust is established between a subscriber unit and a content provider. A request is submitted from the subscriber unit to the content provider. A challenge nonce is generated at the content provider and returned to the subscriber unit. At the subscriber unit, an operating system (OS) certificate containing an identity of the operating system from the software identity register, information describing the operating system, the challenge nonce, and a CPU public key is formed, and the OS certificate is signed using a CPU private key. The OS certificate and a CPU manufacturer certificate supplied by a manufacturer of the CPU are passed from the subscriber unit to the content provider, and are evaluated at the content provider to determine whether to reject or fulfill the request.

Abstract: In dealing with degradation in performance of a system unit due to excessive controlling by performing a power consumption control function after power consumption of the system unit actually exceeds a maximum power of a power supply apparatus, the present invention solves the above technological problems, and controls the power consumption of a system unit in a state while making full use of performance of the power supply apparatus.

Abstract: An adaptive digital power control system is disclosed, which implements a digitally controlled, near real-time algorithm to accommodate multiple loop current mode controls for low voltage, high performance computing system power needs. For example, an adaptive digital power control system that is implemented with an FPGA to generate low voltages for high performance computing systems is disclosed, which includes a current and voltage loop compensation algorithm that enables the adaptive digital power control system to dynamically compensate for high current transients and EMI-related noise. The current and voltage loop compensation algorithm uses a combination of linear predictive coding and Kalman filtering techniques to provide dynamic current and voltage compensation, and implement a feed-forward technique using knowledge of the power system's output parameters to adequately adapt to the system's compensation needs.

Abstract: A power management system (100) includes a group of individually powered electronic devices (101-107) connected with a power management controller (109). The power management controller (109) operates to determine the operation and charge of each power source of the electronic devices (101-107) for managing the power source life of at least one of the devices through the use of pre-selected power management algorithms. These include a preprogrammed and predictive algorithm (203, 205) based on anticipated or actual device activity, a priority algorithm (207) based on device priority or a maximize work shift algorithm (209) based on the time period of the user's work shift.

Abstract: A method, an apparatus and a carrier medium storing instructions to implement the method. The method is in a first wireless station of a wireless network, and includes wirelessly receiving a signal corresponding to a packet wirelessly transmitted by a second wireless station. The packet includes a subpacket and a check sequence. The method further includes verifying the integrity of the subpacket, the verifying at least using the check sequence. The method further includes, in the case that the subpacket fails the verifying, reducing the power consumption of at least one component in the first wireless station for a time interval.

Abstract: A system and method for selecting a computer hardware component of a computing system to throttle based on a selection policy is disclosed. A co-thermal control system may receive a first signal indicating a first condition for a plurality of computer hardware components has occurred. The co-thermal control system may choose a course of action at least partially based upon the first signal using a table-based rule generator. The co-thermal control system may output instructions to participating components for the course of action.

Abstract: Methods for activating operations of a communication device coupled to an external communication bus include detecting a communication event on the external communication bus at a wake up circuit while a host controller coupled to the external communication bus is in an inactive state. An interrupt signal is provided to a processor of the communication device that is operating using a first clock signal running at a first clock rate from a first clock responsive to detection of the communication event by the wake up circuit. A clock enable signal is provided from the processor of the communication device, responsive to the interrupt signal, to a second clock in an inactive state. The second clock is coupled to a second circuit of the communication device separate from the processor of the communications device. Active state operations of the second clock are initiated to generate a second clock signal at a second clock rate greater than the first clock rate responsive to the clock enable signal.

Abstract: Routes between data planes are partitioned according to the source and destination data planes. Partitions are distributed according to the source data plane associated with the partition. Each data plane is configured to clear and resynchronize its own routes when a data plane fails. Also, the restarted data plane is configured to restore routes by retrieving partitions that have the restarted data plane as the source data plane.

Abstract: A system and method for controlling peer-to-peer remote copy (PPRC) operations initiated from one or more host devices that desire to store data contents written to a first storage system to a second storage system over a communications link. The system enables receipt and generation of copy services commands from host devices and the determination of whether a received command pertains to a copy service over an established PPRC relationship for that particular customer to enable that customer to perform storage operations effecting data written to a first storage server having source volumes and stored in a remote second storage system having target volumes. The copy services command effecting data contents of source volumes and/or remote target volumes will be enabled if it is determined that said PPRC relationship is already established for that customer; and, prevented if the received copy services command does effect any volume not already in a copy services relationship.

Abstract: A storage system includes an application server that provides an application composed of a plurality of programs, a plurality of first volumes that store data that the programs use, and a plurality of second volumes set in pair states where replicas of the plurality of first volumes are stored. A program for managing the storage system controls a computer to execute the procedures of: identifying any one of the plurality of programs; identifying a first volume that the identified program uses; obtaining every second volume set in a pair state with the first volume; and summarizing the first volume and the obtained second volume for the identified program.

Abstract: A fault-tolerant computer uses multiple commercial processors operating synchronously, i.e., in lock-step. In an exemplary embodiment, redundancy logic isolates the outputs of the processors from other computer components, so that the other components see only majority vote outputs of the processors. Processor resynchronization, initiated at predetermined time, milestones, and/or in response to processor faults, protects the computer from single event upsets. During resynchronization, processor state data is flushed and an instance of these data in accordance with processor majority vote is stored. Processor caches are flushed to update computer memory with more recent data stored in the caches. The caches are invalidated and disabled, and snooping is disabled. A controller is notified that snooping has been disabled. In response to the notification, the controller performs a hardware reset of the processors. The processors are loaded with the stored state data, and snooping and caches are enabled.

Abstract: A backup-type power supply system aims to integrate power output according to different potentials through different power supply modules. Each power supply module includes backup-type N+1 power supply devices and an independent power balance unit to output power in a balanced fashion so that users can add the power supply module of independent potential according requirements. Thereby transformation power loss of the power supply devices can be reduced. The power supply devices can be designed with different specifications and dimensions corresponding to different electronic devices.

Abstract: An embodiment of the invention is a technique to detect data corruption of critical data structures and to repair the corrupted critical data structures. Information data of critical data structures used by a managing module are captured upon initialization of the managing module. The captured information data are considered valid, and stored in a data vault. Critical data structures used by the managing module are monitored for validity during operation of the managing module. A corruption of a critical data structure corresponding to a stored data of the stored captured information data is detected during operation of the managing module. The corrupted data structure is restored to an operational state by using the corresponding stored data in the data vault without interrupting the operation of the managing module.

Abstract: A detection and recovery mechanism is herein disclosed for soft errors corrupting TLB data. The mechanism works with a hardware page walker (HPW) and instruction steering control mechanisms in a processor to provide soft error recovery in the TLB arrays and latches. Through use of the disclosed detection and recovery mechanism, efficient and robust protection from silent data corruption is provided without requiring more expensive built-in redundancy.

Abstract: A system and method for fast system recovery that bypasses diagnostic routines by disconnecting failed hardware from the system before rebooting. Failed hardware and hardware that will be affected by removal of the failed hardware of the system are disconnected from the system. The system is restarted, and because the failed hardware is disconnected, diagnostic routines may safely be eliminated from the reboot process.

Abstract: In accordance with the present invention, the above and other problems are solved by an integrated test framework that can receive measurement commands from a test script, automatically configure and execute any performance metrics required to effectuate the measurements and further manage the operation of the software to be tested. The integrated test framework can interpret script commands directed at any testing tool in a testing tool library accessible to the framework. Furthermore, the integrated test framework can identify and utilize code markers during the testing of software applications that utilize embedded code markers as well as identifying script markers. Thus, the integrated framework allows testing scenarios to be created incorporating both code markers and script markers to control performance testing of the executing software application.

Abstract: A recording-medium controlling apparatus that performs a read-access and a write-access of a recording medium in response to access request from a higher-level apparatus, detects a read error that occurs at a time of the read access, and performs a replacement processing, includes an error detecting unit that tries a plurality of the read accesses to an error location on the recording medium to detect whether the read error recurs a plurality of times; and a replacement processing unit that performs, when the error detecting unit detects that the read error recurs a plurality of times, a replacement processing for the error location.

Abstract: A method of estimating a trouble in a network is disclosed, including the following steps: displaying a model network in which the network is modeled by each combination of a network apparatus and a connection; inputting information of trouble portion in the model network and trouble symptom; registering at least trouble portion, trouble symptom, cause portion, and frequency of past trouble instances occurred in the model network to an instance database; retrieving the instance database using the input trouble portion and trouble symptom as retrieval keys; and estimating and displaying cause of the trouble based on the cause portion and frequency of a retrieved instances record. The past trouble instances accumulated in the instance database can be retrieved by the instance retrieval unit using the trouble portion and trouble symptom as the retrieval key. The network trouble estimation apparatus can estimate the cause portion at high accuracy.

Abstract: In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as “mispredicted not taken” with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.

Abstract: In a method of monitoring the reliability of a data link for a data transmission between a server (2) and a client (8), a control unit (14) is triggered by a trigger signal in such a manner that in response to the arrival of the trigger signal the control unit (14) generates first control data for a predetermined running time which commences anew in response to each trigger signal received. The first control data forms a first control representation (23) on a client display screen (11), which first control representation optically indicates the existence of a reliable data link (4) to a user. The control unit (14) generates, after expiration of the running time, second control data which generates a second control representation (23?) on the client display screen (11) which optically indicates the absence of a reliable data link to the user. A control unit (15) periodically transmits a test message to a test unit (18).

Abstract: Various methods and apparatuses are described in which a repair data container may store a concatenated repair signature for multiple memories having one or more redundant components associated with each memory. A processor contains redundancy allocation logic to execute one or more repair algorithms to generate a repair signature for each memory. The repair data container may store actual repair signatures for each memory having one or more defective memory cells detected during fault testing and dummy repair signatures for each memory with no defective memory cells. The processor may contain logic configured to compress an amount of bits making up the concatenated repair signature, to decompress the amount of bits making up the concatenated repair signature, and to compose the concatenated repair signature for all of the memories sharing the repair data container. The repair data container may have an amount of fuses to store the actual repair signatures for an adjustable subset of the multiple memories.

Abstract: A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.

Abstract: This invention provides a method for creating/writing defect management information of an information recording medium and an apparatus and optical disc based on the method. In the present invention, it depends on the type of data to be reproduced whether or not defective sectors which are detected during reproduction operation are replaced with non-defective sectors. If read-out errors are detected in reproducing non-audio/video data, linear replacement algorithm is applied to the corresponding defective sectors. On the other hand, in case of audio/video data, location information of the corresponding defective sectors is just kept without any sector replacement. Therefore, this invention enables to reproduce audio/video data in real-time regardless of the presence of defective sectors and to avoid writing data to the defective sectors when new data is overwritten to the information recording medium.

Abstract: A coverage circuit for use with a general purpose performance counter (“GPPC”) connected to a bus for capturing test coverage information encoded as N one-hot signals indicative of coverage in a logic design. An OR logic block is included for bit-wise ORing the N one-hot signals with a N-bit mask value stored in a register block so that an N-bit output may be generated by the OR logic block depending on the logic transitions of the one-hot signals. A Multiplexer (MUX) block is provided for selecting the N-bit output from the OR logic block under control of at least one control signal, wherein the N-bit output is operable to be stored into the register block when selected by the MUX block.

Abstract: A level of indirection is utilized when writing to a microprocessor array structure, thereby masking hard faults in the array structure. Among other benefits, this minimizes the use of a backward error recovery mechanism with its inherent delay for recovery. The indirection is used to effectively remove from use faulty portions of the array structure and substitute spare, functioning portions to perform the duties of the faulty portions. Thus, for example, faulty rows in microprocessor array structures are mapped out in favor of substitute, functioning rows.

Abstract: A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system.

Abstract: Methods of performing a sector erase of flash memory devices incorporating built-in self test circuitry are provided. The present invention employs an interactive verification and sector erase algorithm to verify and repeatedly erase the sector until a portion of the groups of each page of the sector are erased or a first maximum number of erase pulses is achieved. The algorithm further includes a word verification and erase operation that sequentially verifies and erases each word of the sector until each word is erased or a second maximum number of erase pulses is achieved. The second maximum number of erase pulses may be based on a function of the first maximum number of erase pulses. The second maximum number of erase pulses may be input to the sector erase algorithm as a multi-bit code. The second maximum number of erase pulses and conversion of the multi-bit code may be based on a binary multiple of the first maximum number of erase pulses.

Abstract: A pin-limited device includes a pattern-recognition circuit that detects a predetermined signal pattern transmitted on a supply pin of the device. The predetermined signal pattern is generated within the acceptable operating voltage range of the IC device (e.g., between the minimum and maximum acceptable system voltage levels utilized to control the internal circuitry of the device). Accordingly, the pin-limited IC device continues to operate within specifications while the predetermined signal pattern is transmitted on the selected power supply pin or pins. A test mode circuit generates a switch control signal in response to the predetermined signal pattern to connect an output pin of the device, for example, to an internal node of the device. The pattern recognition circuit sets a latch when the predetermined signal pattern is detected, and the latch is reset when the device is powered down then powered up.

Abstract: A method for testing a network interface is provided that includes generating a data pattern file based on a pseudocode file and testing the interface using the data pattern file. The pseudocode file defines an order for a plurality of data patterns in the data pattern file. The data pattern file is provided to a testing device that may test the interface using the data pattern file by applying the data patterns from the data pattern file to the interface.

Abstract: The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: A data communication system has a combiner circuit that combines a set of information symbols with error correction codes and that generates a set of product codes that are at least three dimensional. A communication channel receives the set of product codes and provides the set of product codes with errors after a channel delay. A channel detector receives the set of product codes with the errors and generates a channel detector output. An error correction circuit receives the channel detector output and iteratively removes the errors to provide a set of reproduced information symbols with a reduced number of the errors.

Abstract: A network device having a method and computer-readable media includes a processor adapted to receive a first fragment of a packet. The first fragment includes a first portion of a payload of the packet and a header of the packet, the header comprising a checksum field. The processor receives a second fragment of the packet, the second fragment includes a second portion of the payload of the packet. The processor transmits the second fragment of the packet to a network interface controller and subsequently transmits the first fragment of the packet to the network interface controller. The network interface controller includes a checksum adder adapted to calculate a checksum of the second fragment of the packet, and calculate a checksum of the first fragment of the packet after calculating a checksum of the second fragment of the packet. The checksum of the first fragment of the packet includes the checksum of the second fragment of the packet.

Abstract: A method for storing a data block, involving storing the data block in a storage pool, obtaining a data block location, determining a checksum function for the data block, calculating a data block checksum using the checksum function for the data block, and storing a first indirect block in the storage pool, wherein the first indirect block comprises the data block location, the data block checksum, and a checksum function ID corresponding to the checksum function for the data block.

Abstract: A tester unit for evaluating data integrity of a block of data is described. The tester unit comprises a checksum determination facility adapted for deriving a checksum value from a block of data stored in a memory, and a checksum evaluation facility adapted for comparing the derived checksum value with a predetermined checksum value, and for initiating a reload of the block in case the derived checksum value differs from the predetermined checksum value.

Abstract: A method of processing signals received from an electronic device (106, 202) in a cellular network (100, 200) that utilizes variable rate vocoding comprising receiving a first series of low rate frames (318) at the cellular network; receiving a high rate frame (320) that has at least one bit error at the cellular network after receiving the first series of low rate frames, wherein the rate of the high rate frame can be determined; and sending a request (310) to the electronic device to retransmit the high rate frame.

Abstract: A method and apparatus to preserve bandwidth in a communication system are described wherein a receiver receives a first frame of transport blocks from a mobile device and an error detection module connected to the receiver detects whether each transport block contains an error. The error detection module generates an error indicator value to indicate whether each transport block contains an error or does not contain an error. A frame generator connected to the error detection module generates a second frame with the transport blocks that do not contain an error and the error indicator values. A first network interface is configured to send the second frame to a radio network controller. Other embodiments are described and claimed.

Abstract: Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.

Abstract: The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratio's in a single operation, as opposed to the two pass traditionally associated with the Tanner Graph's. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISO's. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.

Abstract: An error correction code generator uses an additional static random access memory (SRAM) or a multi-symbol encoder to improve the encoding efficiency. During the encoding operation, the number of the data access of the dynamic random access memory (DRAM) with the row address switching can be reduced considerably via using the additional SRAM or multi-symbol encoder. Hence, the efficiency of the data access of the DRAM is improved and the encoding time of the error correction code generator is reduced.

Abstract: An apparatus, a carrier medium storing instructions to implement a method, and a method in a node of a wireless network able to receive packets that exactly or substantially conform to a wireless network standard according to which each packet includes a header having bits that have respective correct values in the case that the packet exactly conforms to the standard. The method includes receiving a start-of-packet (SOP) trigger that indicates that a packet may have been received, checking one or more bits in the header to determine whether or not they have their respective correct values, and continuing to process the packet in the case that the checking indicates that the checked bits have their respective correct values. In one implementation, the header includes a first field modulated at a known rate that has one or more reserved bit locations, and a second field modulated at a data rate indicated in the first field.

Abstract: Methods and apparatus for managing, finding and displaying objects such as digital images. Objects are tagged (“associated”) with descriptive textual and numeric data (“metadata”), and stored in a relational database from which they can be selected, sorted, and found. Tags can be defined by name, tag type, and associated attributes. Objects can be tagged by dropping a tag onto the object, or relating a database record for the tag to a database record for the object. Tagged objects can be searched for and displayed according to the degree to which their metadata matches the search criteria. Visual cues can indicate whether displayed objects match all, some but not all, or none of the search criteria. Database object distributions can be displayed as histograms or scatter plots, including timelines, calendars or maps. Object distributions can be used to search for objects or to limit search results for a previous search.