Abstract: Disclosed is a device for measuring the loss factor and/or measuring the phase angle between a voltage and a current and/or recording a voltage decay and/or current decay and/or recording partial discharge processes and/or measuring the propagation time on test objects that are to be tested. Said device comprises a housing in which at least one measuring circuit is arranged for measuring and/or recording purposes. A terminal adapter (12) is provided on the housing (9) to connect the test object that is to be tested directly to the housing (9).

Abstract: A system and method of integrated circuit control for in situ impedance measurement including a system with a plurality of functional partitions in a clocked logic type integrated circuit, the functional partitions having a communication controller and a modulation gate, the modulation gate receiving a clock signal and a modulation signal and generating a modulated clock signal for the functional partition; at least one of the communication controllers receiving an in-band signal and selectively communicating the in-band signal to the other communication controllers; and at least one of the functional partitions having a modulator, the modulator receiving the clock signal and a modulation control signal and generating the modulation signal.

Abstract: This present invention discloses a light-driving system capable of providing an accurate calibration of signal measurement and a method for performing the same, including an automatic power control (APC) circuit which is pre-calibrated for a signal measurement process. By enlarging at least one measured pad of the APC circuit, multiple grounding paths are established via a plurality of probes of a test instrument. An impedance effect predicted on the contact between the probes and the pad is diminished greatly. A voltage value on the pad can be accurately measured. Thus, a reference voltage value input to a first input of a comparator of the APC circuit can be determined on a basis of a specific condition when a ramping voltage value input to a second input of the comparator is substantially equal to a sum of a predetermined reference voltage value and the voltage value of the pad.

Abstract: A method and system to determine freshness and palatability (tenderness, juiciness, and flavor) of live foodstuffs (meat, fish, fowl, fruit and vegetables) including the steps of; utilizing bioelectrical impedance analysis in a biological subject model for measurement and composition analysis; and a system of using the results of the utilizing step procedure to illustrate an objective scale of palatability; a ‘Palatability Index’. Also a method of whole body and regional organ and tissue vitality assessment in a biological entity, human, animal, fruit or vegetable, including the steps of: utilizing bioelectric impedance analysis in a biological model for composition analysis; and using the results of the utilizing step to provide an objective assessment of volume and distribution of fluid and tissues, and electrical health of cells and membranes of the organ or tissue.

Abstract: Provided is a suspended nanowire sensor having good sensing characteristics and suitable for mass production, a method for fabricating the suspended nanowire sensor. The suspended nanowire sensor includes: first and second sensor electrodes formed on upper portions of a substrate and physically separated from each other; and a nanowire sensor material piece extending from the first sensor electrode to the second sensor electrode and physically suspended between the first and second sensor electrodes.

Abstract: An apparatus that estimates the ohmic resistances of N batteries includes voltage and current measurement modules that respectively measure the voltage and current of each of the N batteries. An ohmic resistance estimating module over N+1 time periods receives the voltage and current measurements of each of the N batteries and receives consecutive voltage and current measurements for one of the N batteries. N is a positive integer and the ohmic resistance estimating module estimates the ohmic resistance of the battery that is associated with the consecutive voltage and current measurements.

Abstract: A diagnostic test device comprising means for sampling a liquid biological sample, means for reacting the sample with at least one reagent to provide one or more visible indicia and an optical detector for detecting the presence of said one or more indicia, the device further comprising a releasable tether which is released by contact with the liquid sample, thereby to cause the optical detector to detect the said one or more indicia.

Abstract: Provided is a support member assembly suitable for use in a contact probe head comprising a support member formed with a plurality of holder holes for supporting conductive contact members in a mutually parallel relationship, and a reinforcing member integrally formed with the support member and extending in a part of the support member devoid of any holder holes. The reinforcing member increases the overall mechanical strength of the support member assembly, and prevents the thermal deformation of the support member. Because the holder holes are formed in the support member made of material suitable for forming holes, such as plastic material and ceramic material, the holder holes can be formed at high precision and at low cost.

Abstract: The present invention relates to an apparatus, unit and method for testing image sensor packages, which can automatically test whether the image sensor packages are defective before they are assembled into camera modules. An apparatus for testing image sensor packages according to the present invention comprises a seating unit on which image sensor packages are seated for tests; a testing section having a lens and a light source above the image sensor packages to perform an open and short test and an image test for the image sensor packages; and a controlling and processing unit having a tester module for performing the open and short test and the image test for the image sensor packages.

Abstract: A semiconductor integrated circuit includes a clock generator which generates a first clock, a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock, a data extractor which samples the test data and extracts recovery data, and a detector which detects an error of the recovery data.

Abstract: Reliability of results of a test such as a wafer burn-in test is raised. The present invention is a method for testing a plurality of semiconductor devices in a semiconductor wafer held in a cartridge. Each of the semiconductor devices has electrodes and the cartridge has a lower cartridge portion provided with a chuck holding the semiconductor wafer thereon, and an upper cartridge portion provided with a probe assembly having probes capable of contacting said electrodes. After constituting the cartridge and before placing the cartridge in the thermostatic chamber, a contact check to determine whether or not electrical contact between the electrodes of the semiconductor devices in the cartridge and the probes of the probe assembly is appropriate is performed.

Abstract: Apparatus for testing microelectronic components on a substrate, including a scanner operative to scan a light beam over a plurality of thin film transistors disposed on a substrate, one transistor at a time, so as to induce a photoconductive response in the plurality of transistors, one transistor at a time; current sensing circuitry operative, synchronously with said scanner, to measure an output induced by the photoconductive response associated with a transistor and to generate photoconductive response output values, the photoconductive response output values representing a photoconductive response induced by the light beam, for one transistor at a time from among the plurality of transistors; and diagnostic apparatus operative to analyze the electronic response output values and to characterize each of the transistors in accordance therewith.

Abstract: There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.

Abstract: A quantum computer can only function stably if it can execute gates with extreme accuracy. “Topological protection” is a road to such accuracies. Quasi-particle interferometry is a tool for constructing topologically protected gates. Assuming the corrections of the Moore-Read Model for ?=5/2's FQHE (Nucl. Phys. B 360, 362 (1991)) we show how to manipulate the collective state of two e/4-charge anti-dots in order to switch said collective state from one carrying trivial SU(2) charge, |1>, to one carrying a fermionic SU(2) charge |?>. This is a NOT gate on the {|1>, |?>} qubit and is effected by braiding of an electrically charged quasi particle ? which carries an additional SU(2)-charge. Read-out is accomplished by ?-particle interferometry.

Abstract: DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design methodology can be used in logic circuits, gate arrays, FPGAs, cryptographic processors, etc. In one embodiment, the implementation details of how to create a secure encryption module can be hidden from the designer. The designer is thus, able to write the code for the design of DPA-resistant logic circuits using the same design techniques used for conventional logic circuits. Contrary to other complicated DPA-blocking techniques, the designer does not need specialized knowledge and understanding of the methodology. In one embodiment, the automated design flow generates a secure design from a Verilog or VHDL netlist. The resulting encryption module has a relatively constant power consumption that does not depend on the input signals and is thus relatively independent of which logic operations are performed.

Abstract: An on-die termination circuit of a semiconductor memory apparatus includes a comparator that compares a voltage corresponding to a normal code with a reference voltage to output a comparison signal. A code adjusting unit varies the normal code according to the comparison signal, outputs the varied normal code, and resets the normal code to a predetermined reset code or a variable fuse code.

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile.

Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block. A digital input/output circuit block is coupled to the programmable logic block. A SRAM block is coupled to the programmable logic block. At least one non-volatile memory block is coupled to the programmable logic block. A JTAG port is coupled to the programmable logic block. An analog circuit block including an analog-to-digital converter may be coupled to the programmable logic block and an analog input/output circuit block may be coupled to the analog circuit block.

Abstract: A logic module (400) that is capable of implementing data-path and random logic (command Z in block 42) uses control logic for selectively coupling one or more of the input terminals (10, 12, 14, 16, 18, 40) to the at least one output terminal (20). The control logic comprises a plurality of logic elements (26, 28, 30, 32) arranged to generate a first set of two-input logic functions (f, (a, b)) and a programmable inverter (36) arranged to generate a second set of two-input logic functions, the second set of two-input logic functions being the complement functions of the first set of two-input logic functions. SRAM memory cells (4 bit memory batch (38)) may be used for configuration purposes, realising a compact logic module or block that is also re-programmable.

Abstract: The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-state bus (one bit of data per bus line or wire). The bus keeper and logic control circuit is maintained in isolation from I/O functional driver and is responsive to a tri-state signal (TS), normally provided by the IC or SOC, or the I/O circuit during normal I/O receiver side operation. The inventive bus keeper and logic circuit selectively enables any of a tri-state state, a pull-up state, pull-down state and bus keep mode state at the driver output pad in the presence of the tri-state enable signal, and is disabled when the I/O bus drive buffer circuit is in drive mode.

Abstract: Logic circuits are disclosed that include one or more three-terminal chalcogenide devices. The three-terminal chalcogenide devices are electrically interconnected and configured to perform one or more logic operations, including AND, OR, NOT, NAND, NOR, XOR, and XNOR. Embodiments include series and parallel configurations of three-terminal chalcogenide devices. The chalcogenide devices include a chalcogenide switching material as the working medium along with three electrical terminals in electrical communication therewith. In one embodiment, the circuits include one or more input terminals, one or more output terminals, and a clock terminal. The input terminals receive one or more input signals and deliver them to the circuit for processing according to a logic operation. Upon conclusion of processing, the output of the circuit is provided to the output terminal. The clock terminal delivers a clock signal to facilitate operation of the three-terminal devices included in the instant circuits.

Abstract: A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q<1 (decimal). The numerator (p) and the denominator (q) are supplied to a flexible accumulator module, and a divisor is generated as a result. N is summed with a k-bit quotient to create the divisor. In a phase-locked loop (PLL), the divisor and the reference signal are used to generate a synthesized signal having a frequency equal to the synthesized frequency value.

Abstract: A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.

Abstract: Provided is a semiconductor device capable of evenly distributing an effect of charge on each gate of adjacent MOS transistors, which form a current mirror circuit, during a production process of the semiconductor device, by directly connecting the gates of the adjacent MOS transistors, which form the current mirror circuit, to each other with polysilicon and by further connecting a fuse, which is connected to a substrate, to a gate portion that is connected with the polysilicon, and capable of reducing the effect by dissipating the charge to the substrate. The fuse is cut off during a trimming process.

Abstract: A circuit arrangement comprising a high-side semiconductor switch with a first load terminal connected to a first supply terminal receiving an input voltage, a second load terminal connected to an output terminal providing an output signal, and a control terminal, a floating driver circuit connected to the control terminal for driving the semiconductor switch, a level shifter receiving an input signal and providing a floating input signal dependent on the input signal, a floating control logic receiving the output signal and the floating input signal and providing at least one control signal to the floating driver circuit, wherein the floating control logic comprises means for detecting an edge in the output signal and means for generating the control signal dependent on the result of the edge detection.

Abstract: A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.

Abstract: A frequency conversion device, which may include a radiofrequency (RF) mixer device, includes a substrate and a ferromagnetic film disposed over a surface of the substrate. An insulator is disposed over the ferromagnetic film and at least one microstrip antenna is disposed over the insulator. The ferromagnetic film provides a non-linear response to the frequency conversion device. The frequency conversion device may be used for signal mixing and amplification. The frequency conversion device may also be used in data encryption applications.

Abstract: A spread spectrum clock generator is provided which improves the spread spectrum effect with little increasing the circuit cost by modifying the shape of a triangular wave used for frequency modulation by a simple method. The output signal of the modulation waveform generating circuit has such a modulation waveform as indicated by solid lines in FIG. 2A. The modulation waveform is input to a VCO (voltage-controlled oscillator). In response to the modulation waveform, the oscillation frequency of the VCO is modulated, and the output clock that varies its frequency as illustrated in FIG. 2B is obtained. The frequency transition of the output clock involves such temporal variations as indicated by solid lines in FIG. 2C.

Abstract: An on-chip clock multiplier for outputting a fast clock that is approximately a predetermined multiple n of a slow clock. The multiplier utilizing a high-speed oscillator to generate a high-frequency base signal. A lower frequency signal is generated using the high-frequency base signal as a function of the output of a rollover counter that counts from a seed value to a terminal value. A saturation counter is used to determine whether no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. If not, the lower frequency signal is iteratively slowed by changing the seed value until no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. When this iteration is done, the fast clock having a frequency that is approximately n times the frequency of the slow clock is output.

Abstract: A circuit for generating non-overlapping clock signals includes a programmable delayed reference clock signals circuit to produce a plurality of delayed reference clock signals and a plurality of delay clock signal generators, operatively connected to the programmable delayed reference clock signals circuit, to generate non-overlapping clock signals. Each delay clock signal generator includes a latch or flip-flop to control a delay in a rising edge of a clock signal and to output a first signal, another latch or flip-flop to control a delay in a falling edge of a delayed clock signal and to output a first signal, and a logic circuit to generate the clock signal from the first and second signals. The latches or flip-flops independently control a delay in the rising edge of the clock signal in response to one of the plurality of delayed reference clock signals.

Abstract: The present invention provides a control device capable of performing feedback control so that a signal-wavelength input to a control target object becomes a specific signal-wavelength, using an input signal whose duty value is other than 50%. Accordingly, the control device according to the present invention is a control device for performing feedback control so that a signal-wavelength input to a control target object (500) becomes a specific signal-wavelength, the control device including a control unit (100) that performs feedback control so that the signal-wavelength input to the control target object (500) becomes the specific signal-wavelength, using an input signal input to the control target object (500), the input signal whose duty value is other than 50%.

Abstract: Compound MOS capacitors and phase-locked loop with the compound MOS capacitors are disclosed. In the phase-locked loop, the compound MOS capacitors of the loop filter are HV (high voltage) devices, and the voltage control oscillator is a LV (low voltage) device. The compound MOS capacitor comprises a HV PMOS capacitor having a base coupled to a source terminal of a low voltage source and a HV NMOS capacitor having a base coupled to a ground terminal of the low voltage source. The gates of the HV PMOS capacitor and the HV NMOS capacitor are connected together to receive a control voltage. The capacitance of the compound MOS capacitor is near constant in any control voltage.

Abstract: A charge pump circuit including an input rail, an output rail, a voltage rail, a control line, an MOS input transistor including a gate and a channel connected between the input rail and the voltage rail, and an MOS output transistor including a gate and a channel connected between the output rail and the voltage rail. The gate of the input transistor is connected to the gate of the output transistor and a switch connects the channel of the output transistor to the voltage rail in response to a signal on the control line. The channel of an input cascode transistor connects the channel of the input transistor to the input rail and the channel of an output cascode transistor connects the channel of the output transistor to the output rail. The gate of the input cascode transistor is connected to the gate of the output cascode transistor.

Abstract: Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion.

Abstract: A differential latch comprising a data holding transistor, the differential latch comprising: a resetting transistor that is connected to a gate electrode of the data holding transistor and is controlled by a reset signal; and a switching transistor that is connected to the gate electrode of the data holding transistor and is controlled by a switch signal, being an inverted version of the reset signal.

Abstract: System and method for providing stable control for power systems. According to an embodiment, the present invention provides an apparatus for providing one or more control signals for a power system. The apparatus includes an input terminal for receiving an electrical energy, which can be characterized by a first input voltage. The apparatus includes a control component that is configured to generate a first control signal based on at least information associated with the first input voltage. The apparatus additionally includes an output terminal for sending the first control signal. Moreover, the apparatus includes a timing component that is coupled to the control component. The control component is configured to process at least information associated with a first value of the first input voltage at a first time and a first reference voltage and to generate a second control signal.

Abstract: A digital delay architecture and a digital delay method are provided. The digital delay architecture includes at least one shifter, at least one adder connected to the at least one shifter and a plurality of registers storing at least an output of the at least one adder and an original sampled signal. The plurality of registers are selectable to define a fractional delay value.

Abstract: A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.

Abstract: An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection.

Abstract: A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit outputs a switching signal when detecting the abnormal waveform pulse in the second clock. A selector outputs the first clock instead of the second clock as the output clock based on the switching signal. A delay circuit delays the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector.

Abstract: A high-speed serial link receiver includes variable offset comparators with centrally controlled offset cancellation. The receiver includes a comparator stage to receive a high-speed differential input signal. Comparator elements of the comparator stage have first and second current sources to provide current to corresponding differential amplifier half-circuits. An offset cancellation controller provides an offset cancellation signal for setting current provided by one of the current sources to at least partially offset an output offset between the differential amplifier half-circuits. A receiver system may be comprised of a plurality of receiver units for receiving a corresponding plurality of channels over high-speed serial links. A state machine may sequentially determine an offset cancellation code for the comparator elements of the receiver units.

Abstract: A level shift circuit that converts a level of an input signal having a logic level at a first input electric potential and a logic level at a second input electric potential and that generates an output signal having a logic level at a first output electric potential corresponding to the first input electric potential and a logic level at a second output electric potential corresponding to the second input electric potential.

Abstract: A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mode, without external clock, and can be implemented on a portion of silicon area needed for other DPWM solutions. In addition it has low power consumption and provides a good linearity of the input-to-output characteristic, also not characteristic for other architectures.

Abstract: The disclosure provides a method for reducing an amount of simultaneous switching outputs (SSO) of a device. The method of reducing the amount of simultaneous switching outputs can include driving outputs of the device to a first set of values, scrambling a second set of values to reduce an amount of simultaneous switching outputs resulting from the switching of the first to the second set of values, and driving the outputs of the device to the scrambled second set of values. Further, the method can include descrambling the scrambled second set of values back to the second set of values.

Abstract: A capacitive proximity switch includes an electrically conductive sensor area, which is covered by an electrically-insulating cover plate, as part of a capacitor having a capacitance which varies as a result of proximity. An associated evaluation circuit is provided, and an electrically-conducting body, via which the sensor area is connected to the evaluation circuit and which is arranged between the electrically-insulating cover plate and a mount disposed at a distance therefrom. A domestic appliance includes such a proximity switch. At least one electronic component of the evaluation circuit is arranged on the mount such that it protrudes into a cavity, which is surrounded by the electrically conductive body.

Abstract: A low noise voltage reference circuit is described. The reference circuit utilizes a bandgap reference component and may include at least one of a current shunt or filter to reduce high and low noise contributions to the output. Further modifications may include a curvature correction component.

Abstract: A reference voltage generator and an integrated circuit including the reference voltage generator. The reference voltage generator includes a band gap reference circuit and a start-up circuit. The band gap reference circuit provides a reference voltage to a load. The start-up circuit increases the provided reference voltage by providing a boosting current to the load based on a difference between the provided reference voltage and a target reference voltage responsive to a start-up signal, thereby reducing a time in which the provided reference voltage reaches the target reference voltage. Therefore, the reference voltage generator is configured to provide a target reference voltage within a predetermined time.

Abstract: A circuit includes an OPAMP-less bandgap voltage generating core circuit connected between a regulated voltage and a ground reference to generate an output bandgap voltage. A preregulator circuit generates the regulated voltage from an unregulated supply voltage. The preregulator circuit includes a negative feedback loop operable to stabilize the regulated voltage and a current source operable to source current for the regulated voltage, the current source mirroring a PTAT current of the OPAMP-less bandgap voltage generating core circuit. The core circuit further includes a negative feedback loop and a positive feedback loop, the negative and positive feedback loops functioning to equalize two internal voltages within the core.

Abstract: An integrated circuit comprises an assembly of switched capacitors operated under control of a system clock signal. It further comprises a signal driver for generating a binary output signal at an output pad. The system clock signal is suppressed for a certain time period after each transition of the output signal, thereby preventing voltage droop generated by the transition to introduce noise in the signals of the assembly of switched capacitors.