Abstract: A screen display apparatus for controlling the size each display area to appropriately display content information of each display area into one display screen. The screen display apparatus includes a selection accept block for accepting selection of first content information displayed in a first display area, a content information acquisition block for acquiring the content information associated with the selected first content information, this content information being second content information located on a layer below the first content information, and, in order to allocate a second display area for displaying the second content information to the display screen, a display area control block for controlling either or both of the first display area and the second display area.

Abstract: An interface for a medical record database allows multiple different applications to be opened accessing the records of a common and/or different patients. For those applications accessing the records of a common patient, a visual indication is provided indicating whether or not records of the same patient are being accessed to prevent the user from mistakenly comparing the records of different patients.

Abstract: A graphical user interface is disclosed which achieves an easy search for a desired item upon scrolling. Plural first icons representing first items of a high hierarchy are arrayed along a direction of a display screen, and plural second icons representing second items of a low hierarchy which belong to a selected one of the first items are arrayed along an intersecting direction with the selected first item positioned at the intersecting position. The selected noticed icon from among the plural second icons is displayed emphatically at a fixed position on the display screen, and explanation information of the noticed item icon is displayed in the proximity of the display position of the noticed icon. In response to a scrolling instruction, scrolling is executed while explanation information of the second icons other than the noticed item icon is displayed.

Abstract: Techniques for generating a static representation of time-based media information. A static representation is generated that comprises a timeline representing the duration of the time-based media information. Occurrences of one or more events that occur in the time-based representation are indicated along the timeline in the static representation. The static representation may be printed on a paper medium.

Abstract: A system that interacts with objects in a user interface of a computer system. During operation, the system receives a selection of an object displayed within the user interface from a user, wherein the selected object contains a plurality of sub objects. In response to the selection, the system determines whether the user is moving the selected object with a specified motion. If so, the system performs a transformation on the selected object, wherein the transformation is associated with the specified motion.

Abstract: A system and method are provided for notifying a user about the occurrence of at least one predetermined event associated with an uninterruptible power supply (UPS) in operable communication with the system. The system comprises a worker module and a user interface module. The worker module determines whether the predetermined event has occurred and, responsive to said determination, the user interface module generates an user interface providing information relating to an operating parameter of the UPS. The user interface comprises at least one of a graphical portion and an alphanumeric portion.

Abstract: A notepad computer with a page display region displaying a page of a document on which a user can write using a pen or stylus type writing tool is provided. Associated with the page is an interface that can be used with the pen. The interface includes a core task tool region adjacent to the page where tool icons are partially visible until the pen is brought near one of the icons. The tool icon becomes fully visible when the pen is within the region of the icon. The tool when activated can pop-up a radial pop-up menu located at an edge of the document where all the menu choices are located in a semi-circle away from the edge so that the users hand while holding the pen and making a selection does not block the choices. A page flipping tool is located in a corner of the page and is an explicit two-stroke menu allowing selection of a next or previous page.

Abstract: A method, system, and program are provided for managing flexible events within an electronic calendar. A calendaring controller schedules fixed events requiring a fixed time slots and flexible events that are flexible for scheduling over a particular time period for a particular duration, wherein the particular time period is greater than the particular duration. The calendaring controller sets each flexible event at a particular time slot within the particular time period for the particular duration. Responsive to the calendaring controller detecting a request for a new event for an additional time slot overlapping the particular time slot, the calendaring controller repositions the flexible event to at least one other time slot of the particular duration during the particular time period to allow for scheduling the new event during the additional time slot.

Abstract: Photomask patterns are represented using contours defined by mask functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to rectilinear patterns), robustness against process variations, as well as restrictions imposed relating to practical and economic manufacturability of photomasks. An accurate, slower merit function may be used to determine adjustment parameters for a faster, approximate merit function. The faster merit function may be used for iteration and adjusted based on the adjustment parameters.

Abstract: Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result. In another aspect, linear performance specifications are included for accurately calculating voltages. In yet other aspects of the invention, three special types of convex optimization problems are disclosed for enabling the above use of exponents of design parameters which provide efficient and accurate calculations of a virtually unlimited array of circuit parameters and performance characteristics.

Abstract: There is described methods and circuits for trimming a temperature coefficient of change of a parameter of at least one electrical component while maintaining a substantially constant parameter value, the method comprising applying a heating cycle to trim said parameter value away from a target parameter value and back to said target parameter value, whereby the temperature coefficient of change is modified after applying said heating cycle.

Abstract: A method and system of determining a localized measure of regional pattern density in a fabrication process of a chip are disclosed. In one embodiment, the method includes determining pattern density values for each cell of a plurality of cells of interest; averaging the pattern density values for each cell within a first selected region about a target cell to determine the localized measure of regional pattern density for the target cell; storing the localized measure of regional pattern density for the target cell; and repeating the averaging and the storing for each of the plurality of cells. The simplification of data allows for a localized measure of regional pattern density determination in much less time than conventional techniques.

Abstract: A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit.

Abstract: A method of enhancing yield of semiconductor integrated circuit includes determining multiple experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole, forming test patterns representing each of the experimental values on a wafer and calculating experimental value-based systematic fault rates from the test patterns; converting the experimental value-based systematic fault rates of the hole into the experimental value-based systematic fault rates, calculating a length of a side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values, and calculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of the sides of the hole calculated for the respective experimental values in the desired layout.

Abstract: A circuit design program product to cause a computer to execute a circuit design process based on a test point insertion, includes: a step for making reference to a netlist to extract a plurality of equivalent faults fj; a step for searching a number n(fj) of test point required for a number of the equivalent fault keeping equivalent relation with a search object equivalent fault fj with each of a plurality of equivalent faults as the search object equivalent fault to become a predetermined number and a insertion position G(fj); a step for calculating probability p(fj) of a single stuck-at fault being included in a set of equivalent faults including at least a search object equivalent fault fj at an occasion when the relevant stuck-at fault takes place in the circuit; a step for calculating a parameter e(fj) derived by an equation: e(fj)=p(fj)/n(fj) on each pattern of an insertion position G(fj); and a step for determining the insertion position G(fmax) giving the maximum value among the calculated parameters

Abstract: Some aspects provide determination of mutual capacitances among a plurality of floating nets and a plurality of non-floating nets, determination of a self-capacitance of each of the plurality of non-floating nets based on the mutual capacitances, and, for each of the plurality of non-floating nets, association of a ground capacitance with a non-floating net that is substantially equal to a determined self-capacitance of the non-floating net. Aspects may further provide performance of a timing study of a capacitor network including the plurality of non-floating nets using the ground capacitance determined for each of the plurality of non-floating nets.

Abstract: The invention relates to a method and system for the design and implementation of state machine engines. A first constraints checking step checks a state transition function created by a designer against constraints imposed by the implementation technology in order to detect all portions of the state transition function that are in conflict with the constraints. A subsequent conflict resolution step tries to determine one or more suggested ways to meet the conflicting constraints, by investigating how the original state transition function can be modified such that all constraints are met. A final presentation and selection step provides the designer textual and/or graphically results of the constraints check and suggested modifications. The modifications can be accepted interactively, or the state transition function can be changed manually. In the latter case, the modified state transition function will be processed starting again with the constraints checking step.

Abstract: A method and apparatus for floor-plan region creation and placement is provided. Design information may be received. Module area may be estimated for each module in an integrated circuit. Individual module may be selected for regioning, and region size and dimensions for module may be determined. Region parameters may be adjusted prior to final placement and placement may be verified.

Abstract: Stitched integrated circuit (IC) chip layout methods, systems and program products are disclosed. In one embodiment, a method includes obtaining from a first entity a circuit design for an IC chip layout that exceeds a size of a photolithography tool field at a second entity, wherein the IC chip layout includes for at least one stitched region of a plurality of stitched regions: a boundary identification identifying a boundary of the at least one stitched region at which stitching occurs and a type indicator indicating whether the at least one stitched region is one of: redundant and unique; dissecting the IC chip layout into stitched regions indicated as unique or redundant at the second entity; and generating a photolithographic reticle at the second entity based on the plurality of stitched regions, the photolithographic reticle having a size that fits within the size of the photolithographic tool field at the second entity.

Abstract: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.

Abstract: A semiconductor integrated circuit includes: a first boundary cell having a first power source wiring, a second power source wiring and a first pseudo power source wiring; a first circuit cell having a third power source wiring connected with the first power source wiring, a second pseudo power source wiring connected with the first pseudo power source wiring, and a first circuit formed of a first circuit transistor; and a first switching transistor having a first electrode connected with the second power source wiring, a second electrode connected with the first pseudo power source wiring, and a gate electrode, wherein the first switching transistor is operated to be turned “ON” and “OFF” according to a control signal inputted to the gate electrode of the first switching transistor and an absolute value of a threshold voltage of the first switching transistor is larger than an absolute value of a threshold voltage of the first circuit transistor.

Abstract: A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the reference level for the current data being latched so that the data eye is maximized.

Abstract: A multilayered board data input unit inputs design data of a multilayered circuit board provided with through holes penetrating and mutually connecting solid-layer conductors disposed in a multilayer manner. A limitation rule setting unit sets a limitation rule for limiting the number of solid-layer conductors to be connected to the through holes. A separation processing unit separates connections of the solid-layer conductors to the through holes in the design data based on the limitation rule. At this time, when a solid-layer conductor to be separated from the through holes is selected as a candidate, the separation processing unit determines whether the solid-layer conductor is isolated by separation, when the solid-layer conductor is not isolated, determines isolation, and when the solid-layer conductor is isolated, stops separation.

Abstract: An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple personalities for re-using silicon resources (like arrays of large multipliers in DSP applications) from moment-to-moment for implementing different hardware algorithms. In a general purpose FPGA device or fabric, this fast reconfigurability is normally implemented by special reconfiguration support circuitry and/or additional configuration memory. Unfortunately, this flexibility requires a large amount of programmable routing resource and silicon area—limiting the viability in volume production applications. This invention describes how multi-program FPGA functionalities may be migrated to smaller die by constructing implementations with a hybrid FPGA/ASIC interconnect structure.

Abstract: A method of manufacturing an exposure mask includes generating or preparing flatness variation data relating to a mask blanks substrate to be processed into an exposure mask, the flatness variation data being data relating to change of flatness of the mask blank substrate caused when the mask blank substrate is chucked by a chuck unit of an exposure apparatus, generating position correction data of a pattern to be drawn on the mask blanks substrate based on the flatness variation data such that a mask pattern of the exposure mask comes to a predetermined position in a state that the exposure mask is chucked by the chuck unit, and drawing a pattern on the mask blanks substrate, the drawing the pattern including drawing the pattern with correcting a drawing position of the pattern and inputting drawing data corresponding to the pattern and the position correction data into a drawing apparatus.

Abstract: A memory is encoded with a data structure that represents a pattern having a range for one or more dimensions and/or positions of line segments therein. The data structure identifies two or more line segments that are located at a boundary of the pattern. The data structure also includes at least one set of values that identify a maximum limit and a minimum limit (i.e. the range) between which relative location and/or dimension of an additional line segment of the pattern in a portion of a layout of an integrated circuit (IC) chip, represents a defect in the IC chip when fabricated. In most embodiments, multiple ranges are specified in such a range defining pattern for example a width range is specified for the width of a trace of material in the layout and a spacing range is specified for the separation distance between two adjacent traces in the layout.

Abstract: Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to rectilinear patterns), robustness against process variations, as well as restrictions imposed relating to practical and economic manufacturability of photomasks.

Abstract: A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image.

Abstract: A method and system for assessing a software generation environment (SGE). The SGE has a plurality of SGE characteristics. At least one query is generated for each SGE characteristic. Each query has a plurality of response choices and each response choice has a numerical score. A selected response choice is received for each query. A SGE score is computed and displayed for each SGE characteristic. The SGE score for each SGE characteristic is equal to a summation of the numerical scores associated with the selected response choices for the SGE characteristic. A total score is computed and displayed, wherein the total score is equal to a summation of the SGE scores.

Abstract: A method for modeling business transformation includes steps of: constructing a first analysis model based on at least one legacy-business-process-model; and analyzing the first analysis model in conjunction with at least one business-process-reference-model. The method further includes deriving a second analysis model in response to analyzing the first analysis model in conjunction with the at least one business-process-reference-model and refining the second analysis model to obtain a design model.

Abstract: Reliability is evaluated in constructing a component based-on application and an application for realizing reliability required can be constructed efficiently. A run-time history such as an occurrence frequency of errors, a recovery time required at error occurrence, and a processing capacity at preventive maintenance is added per software component to a run-time history list having been recoded per execution environment such as an application ID, combined component IDs, and executed hardware ID. From these pieces of information, an interval of performing preventive maintenance recommended per software component during system construction is calculated. By comparing reliability per software component and reliability required for the system, advisability is determined and conformance is evaluated. An execution schedule for preventive maintenance and a processing capability are calculated about the entire component-based application created by combining the software components.

Abstract: Device interoperability format and method for assembling self-contained executable device interoperability software application package conforming to an interoperability format that is completely self-contained and sufficient to carry out an intended purpose of the application on a plurality of connected or intermittently connected devices, the executable device interoperability software application package when executed allowing the plurality of devices to interoperate with each other. Method of forming a linearly contiguous binary encoded part images, and packaging the formed part images together into an executable device interoperability software application package. Computer program product for execution on a computer, information appliance, or other device. Data structure for self-contained executable device interoperability software application package.

Abstract: A method for analyzing a target system that includes obtaining a plurality of characteristics from the target system using a characteristics extractor, wherein the plurality of characteristics is associated with a characteristics model, storing each of the plurality of characteristics in a characteristics store using a tracking mechanism, and analyzing the target system by issuing a query to the characteristics store to obtain an analysis result, wherein the query uses tracking information associated with the tracking mechanism.

Abstract: Techniques and tools relating to annotating program source code facilitate inferring annotations from source code based at least in part on a description (or specification) generated with a programmable tool. Described techniques and tools provide flexibility in annotation inference across different code bases and program states or properties of interest, and can reduce the overhead of adding annotations to “legacy” source code. For example, a specification is generated with a programmable specification tool that is separate from an inference engine. In the inference engine, one or more annotations for a computer program are inferred based at least in part on the specification.

Abstract: A graphics rendering engine within a software development tool is used to perform software debug operations by analyzing the status of instructions within various stages of a superscalar processor pipeline. The debug operations are carried out using code breakpoints selected by a user through a graphical user interface. Once a line of code is selected, the processor pipeline can be examined by designating a highlighted color, for example, for certain stages and corresponding instructions that will proceed to the next stage, and not designating stages and corresponding instructions that will not proceed. This allows a user to visually examine the efficiency of the instruction throughput at select regions in the sequence of instruction addresses. Armed with the information, a user can then modify the sequence if desired.

Abstract: Described are embodiments for developing a message-passing application program. The program is constructed using stages having a plurality of asynchronous functions, or operations. The operations communicate with other operations of other message-passing programs in a distributed computing environment. The operations also communicate with other operations on other stages of the message-passing application. In order to reduce deadlock errors, a behavioral type signature is appended to the declaration of each operation of the message-passing application program. The behavioral type signature specifies behavioral properties for each operation, such as when an operation should send a message to another operation. A type checker utilizes typing rules and the behavioral type signature to extract an implementation model of each function. The type checker then compares the implementation model to the behavioral type signature to determine whether the asynchronous function conforms to the behavioral type signature.

Abstract: Apparatus, methods and articles of manufacture for software demonstration are disclosed. Apparatus include a server that provides, via a network, a program or programs to be demonstrated to a user. The user uploads the code that the program will execute. Results are then supplied after execution, and may be made available to the user in a number of ways. Methods and articles of manufacture are also disclosed.

Abstract: Overall system performance improvements resulting from improvements to individual system components may be predicted by analyzing the effects of artificial performance degradations inserted into the individual components. Measuring and analyzing a negative overall system effect caused by negative changes to an individual component may predict a positive overall system performance improvement resulting from an improvement to the individual component of similar magnitude to the inserted negative changes. System performance prediction may be used to analyze and predict system performance changes related to various computing resources, such as execution time (speed), memory usage, network bandwidth, file I/O, and/or disk storage space, among others.

Abstract: The invention relates to a computer program interpreter and a method for the same, using statistics to group (SR89, SR17 . . . SR6; SR4, SR34 . . . SR16) frequently used service routines (SR) in the same program function and to control encoding of instructions. Frequently used service routines are assigned shorter codes thus enhancing the performance of a simulator or emulator.

Abstract: A new system service table is dynamically generated to allow dynamic insertion of code between the caller of a native operating system function, in user or kernel mode, and the operating system's implementation of the native operating system function. The dynamically inserted code has full access to the function parameters, such as arguments. The new system service table has encoded values that are relative to the base address of the new system service table and which include the function addresses of the native operating system functions corresponding to original system service table entries in the original system service table.

Abstract: A computer program implemented method controls interruption of execution of tasks running in a multi-processing computer system to permit user intervention. The system includes a repository of data identifying preselected tasks for interruption and identifying the user defined circumstances for such interruption. It also has a plurality of task caches for storing subsets of the repository data for respective tasks. According to the method, the repository is scanned during an initiation phase of any task for data relevant to the task. Any such relevant data is stored in the respective task cache. The task is then executed and if a defined circumstance for the task arises by reference to the task cache, the task is interrupted to enable user intervention. This can include updating the repository to redefine the circumstances for interruption. Execution is then resumed and the respective task cache refreshed with any relevant repository updates.

Abstract: A system and method are presented that persist assembly bind information for applications at each stage of execution of the assembly policy. New assembly bind history files are created and persisted to disc when changes in assembly bind policy results in a change in the assemblies with which the application binds. This persisted information is used to reconfigure assembly binds to a prior state when operation of the application conformed to a user's desires. Since this assembly bind reconfiguration is on a per application basis, only the binding of the selected application is affected. Likewise, the assembly bind history files are associated with a particular user to allow personalized execution of applications on a system.

Abstract: An environment for developing clientside/serverside code is disclosed. The environment supports programming in an event-driven paradigm while the execution of the resultant programs are executed in a serial execution paradigm. Through shielding the developer from complex scripting segments, the environment provides the developer with the suggestion that that resultant execution model is event-driven.

Abstract: A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation.

Abstract: An integrated circuit card includes a storage device to store one or more code files and one or more data files, and control logic. The control logic implements an ICC runtime environment that executes an applet in response to a command identifying both a code file and a data file received from a host system.

Abstract: A code placement technique that organizes code units to at least reduce layout conflicts among caller/callee code units. A code preparation environment determines those code units of a code representation that have overlapping memory mappings with their counterpart caller/callee code units. To at least reduce the layout conflicts, or overlapping memory mappings, the code preparation environment arranges the caller/callee code units to eliminate the layout conflicts among the caller/callee code units.

Abstract: Selected regions of native instructions translated in a DBT environment from non-native instructions are compressed based on the independent compression of different fields of selected instructions using compression tables to reduce a length of selected fields. The regions of compressed instructions are stored and de-compressed into the native instructions during subsequent execution using de-compression tables. Specifically, for native instructions of a selected region, selected types of opcodes and/or operands may be compressed independently. The types may be selected by profiling the opcodes using benchmark programs and creating an opcode conversion table prior to compression, and scanning of the operands and creating an operand conversion table during compression of the opcodes.

Abstract: A method and system for performing version-based class loading. In one embodiment, a first version is sought to continue running an application, where a first class is associated with the first version being sought. A first class loader capable of loading the first class is created. The first class is then loaded using the first class loader.

Abstract: Uninstalling a patch applied to a software product installed on a computer. A current state of a software product is identified. A desired state of the software product is determined. The desired state of the software product represents a state of the software product when a patch applied to the software product is removed from the software product. The patch is removed from the software product to transition the software product from the identified current state to the determined desired state.

Abstract: An agent installer operates to install an agent on a plurality of host computer systems using a bulk automated installation process that identifies at least one agent to be installed on a plurality of host computer systems and performs prerequisite checking of each of the plurality of host computer systems to determine which host computer systems of the plurality of host computer system are capable of supporting operation of the at least one agent. For each host computer system of the plurality of host computer systems that is capable of supporting operation of the at least one agent, the agent installer performs an automated bulk agent installation operation to install the at least one agent on that host computer system.