Abstract: An emissive device includes a substrate having a substrate surface; a chiplet adhered to the substrate surface, the chiplet having one or more connection pads; a bottom electrode formed on the substrate surface, one or more organic or inorganic light-emitting layers formed over the bottom electrode, and a top electrode formed over the one or more organic or inorganic light-emitting layers; an electrical conductor including a transition layer formed over only a portion of the chiplet and only a portion of the substrate surface, the transition layer exposing at least one connection pad, the electrical conductor formed in electrical contact with the exposed connection pad and the bottom electrode; and an LED spaced from the chiplet and including a layer of light-emissive material formed over the bottom electrode and a top electrode formed over the light-emissive layer.

Abstract: Provided is a flat panel display apparatus including a sealant which has a small effective width and is able to effectively attach a substrate and an encapsulation substrate. The flat panel display apparatus includes the substrate, a display unit disposed on the substrate, the encapsulation substrate disposed facing the substrate so that the display unit is disposed on inner side of the encapsulation substrate, and the sealant attaching the substrate and the encapsulation substrate, wherein an end surface of the sealant facing the substrate contacts a silicon oxide layer disposed on the substrate.

Abstract: In the field of opto-electronic technology, a three-dimensional (3D) light-emitting diode (LED) light-emitting plate is described. The 3D LED light-emitting plate includes an aluminum substrate. The aluminum substrate is vertically disposed. Notches are formed on an upper side of the aluminum substrate in a thickness direction. LED chips are mounted in the notches. A flexible circuit layer is disposed on a surface of the aluminum substrate. Each LED chip is connected to a circuit of the flexible circuit layer by a gold wire. A fluorescent colloid light-emitting shell is disposed outside each LED chip correspondingly. A cavity is formed between the LED chip and the fluorescent colloid light-emitting shell. A lower portion of the fluorescent colloid light-emitting shell is fixed on the aluminum substrate.

Abstract: A circuit structure of a package carrier including a plurality of chip pads, a first electrode, a second electrode, a third electrode and a fourth electrode is provided. These chip pads are arranged in an M×N array. A first bonding pad, a second bonding pad, a third bonding pad and a fourth bonding pad are disposed clockwise in the peripheral area of each chip pad in sequence. The orientations of each of the first, second, third, and fourth bonding pads of the (S?1)th row rotated by 90 degrees are equal to the orientations of each of the first, second, third and fourth bonding pads of the Sth row, respectively. The first electrode is connected with each first bonding pad. The second electrode is connected with each second bonding pad. The third electrode is connected with each third bonding pad. The forth electrode is connected with each forth bonding pad.

Abstract: A light emitting device comprises a first conductive semiconductor layer, a plurality of light emitting cells separated on the first conductive semiconductor layer, a phosphor layer on at least one of the light emitting cells, and a plurality of second electrodes electrically connected to the light emitting cells.

Abstract: A light-emitting device structure comprises a substrate having a first region and a second region outside the first region, a first conductive type semiconductor layer positioned on the first region, a light-emitting structure positioned on the first conductive type semiconductor layer, a second conductive type semiconductor layer positioned on the light-emitting structure, and a wall structure positioned on the second region.

Abstract: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a light emitting structure including a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; an electrode layer on the plurality of compound semiconductor layers; and a channel layer including protrusion and formed along a peripheral portion of an upper surface of the plurality of compound semiconductor layers.

Abstract: Provided are a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises a plurality of compound semiconductor layers, a first electrode, a second electrode layer, and a conductive support member. The plurality of compound semiconductor layers comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The first electrode is formed under the compound semiconductor layer. The second electrode layer is formed on the compound semiconductor layer. The second electrode layer has an unevenness. The conductive support member is formed on the second electrode layer.

Abstract: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a dot type conductive layer on the compound semiconductor layers; and an electrode layer on the dot type conductive layer.

Abstract: A hybrid organic light emitting diode employing fluorescent family of blue light-emitting OLED and phosphorescent family of red and green light emitting OLED, each family being electrically isolated for driving current in to them independent of each other and thus prevent overloading the phosphorescent family when fluorescent family of OLED is driven at high current density. The electrical isolation built in to the device gives long life for the hybrid OLED and yields high brightness. The independent driving also yields additional advantage of varying the color temperature of white light from the device and thus enables the device to function as a variable color OLED lamp.

Abstract: A light-emitting device in accordance with an embodiment of the present invention includes a semiconductor light-emitting element, and a member in the periphery of the semiconductor light-emitting element is made of a material whose color, transparency or adhesiveness changes over time as it is subjected to light or heat emitted by the semiconductor light-emitting element.

Abstract: Provided is a light-emitting element including an anode over a substrate, a layer containing a composite material in which a metal oxide is added to an organic compound, a light-emitting layer, and a cathode having a light-transmitting property. The anode is a stack of a film of an aluminum alloy and a film containing titanium or titanium oxide. The film containing titanium or titanium oxide is in contact with the layer containing a composite material.

Abstract: This application discloses a light-emitting device comprising a light-emitting stack layer, a first transparent conductive layer disposed below the light-emitting stack layer, a transparent dielectric barrier layer disposed below the first transparent conductive layer, a second transparent conductive layer disposed below the transparent dielectric barrier layer and a metal reflective layer disposed below the second transparent conductive layer wherein an omni-directional reflector (ODR) comprises the metal reflective layer and the second transparent conductive layer. Besides, the first transparent conductive layer is ohmically connected with the light-emitting stack layer.

Abstract: A light emitting device package is provided. The light emitting device package comprises a package body, a light emitting device on the package body, and a light-transmitting light guide member under the light emitting device.

Abstract: Embodiments of the present invention relate to a formulation for use in the fabrication of a light-emitting device, the formulation including a population of semiconductor nanoparticles incorporated into a plurality of discrete microbeads comprising an optically transparent medium, the nanoparticle-containing medium being embedded in a host light-emitting diode encapsulation medium. A method of preparing such a formulation is described. There is further provided a light-emitting device including a primary light source in optical communication with such a formulation and a method of fabricating the same.

Abstract: Provided is a light emitting device. The light emitting device includes: a plurality of lead frame units spaced apart from each other, each of the lead frame units being provided with at least one fixing space perforating a body thereof in a vertical direction; a light emitting diode chip mounted on one of the lead frame units; and a molding unit that is integrally formed on top surfaces of the lead frame units and in the fixing spaces to protect the light emitting diode chip.

Abstract: An LED is bonded to a circuit board. The circuit board comprises a chip mounting area, a bonding pad, and a connecting portion. The LED is mounted on the chip mounting area with an adhesive, and the bonding pad is connected with an electrode of the LED. Moreover, the connecting portion is positioned between the chip mounting area and the bonding pad. One side of the connecting portion is connected with the chip mounting area and another side is connected with the bonding pad. With a hollow portion of the connecting portion, the adhesive will be prevented from flowing to the bonding pad.

Abstract: Provided is a light emitting diode (LED) manufactured by using a wafer bonding method and a method of manufacturing a LED by using a wafer bonding method. The wafer bonding method may include interposing a stress relaxation layer formed of a metal between a semiconductor layer and a bonding substrate. When the stress relaxation layer is used, stress between the bonding substrate and a growth substrate may be offset due to the flexibility of metal, and accordingly, bending or warpage of the bonding substrate may be reduced or prevented.

Abstract: A side-view type light emitting device includes a package body, a lead frame, and a light emitting diode (LED). The package body has a first surface provided as a mount surface, a second surface disposed on a side opposite to the first surface, and lateral surfaces disposed between the first surface and the second surface. The package body includes a recessed portion disposed on a lateral surface corresponding to a light emitting surface of the lateral surfaces. The lead frame is disposed in the package body. The LED chip is mounted on a bottom surface of the recessed portion. Protrusion parts protruding toward the LED chip are disposed in regions adjacent to the LED chip of facing inner sidewalls of the recessed portion, respectively.

Abstract: The invention relates to: a light-emitting device which includes a first flexible substrate having a first electrode, a light-emitting layer over the first electrode, and a second electrode with a projecting portion over the light-emitting layer and a second flexible substrate having a semiconductor circuit and a third electrode electrically connected to the semiconductor circuit, in which the projecting portion of the second electrode and the third electrode are electrically connected to each other; a method for manufacturing the light-emitting device; and a cellular phone which includes a housing incorporating the light-emitting device and having a longitudinal direction and a lateral direction, in which the light-emitting device is disposed on a front side and in an upper portion in the longitudinal direction of the housing.

Abstract: A light emitting diode includes a substrate, a compound semiconductor layer including a light emitting layer formed on the substrate, a first electrode formed on an upper surface of the compound semiconductor layer, and a second electrode formed on the substrate or a semiconductor layer which is exposed by removing at least a portion of the compound semiconductor layer. The first electrode includes a wiring electrode provided on the compound semiconductor layer in contact therewith, an ohmic electrode provided on the compound semiconductor layer in contact therewith, a translucent electrode formed over the compound semiconductor layer to cover the wiring electrode and the ohmic electrode, and a bonding pad electrode connected to the wiring electrode, at least a portion of the bonding pad electrode being exposed from an opening of the translucent electrode to the exterior.

Abstract: An optical semiconductor apparatus can be configured by mounting an optical semiconductor element on a package substrate using a solder paste. The optical semiconductor apparatus can include a package substrate and a metal die pad formed on the substrate, and an optical semiconductor element bonded to the die pad with a solder material. The substrate can be made of a ceramic base material. A plurality of through holes can be formed in the substrate so that the through holes penetrate both the substrate base material and the die pad. Each of the through holes can have an inner surface where the ceramic base material is exposed. Each through hole can have an opening diameter greater than or equal to 40 ?m and less than or equal to 100 ?m. The plurality of through holes can be formed such that the total area of the openings of the through holes is 50% or less of the bonded area between the optical semiconductor element and the die pad including the through holes covered with the solder material.

Abstract: Disclosed herein is a substrate with chip mounted thereon, including: a solder pattern having a plan-view shape in which projected parts are projected radially from a central part; and a chip fixed in the state of being aligned to the central part of the solder pattern.

Abstract: A light emitting device includes a light-emitting portion including a metal part including a metal able to be bonded to a solder material, and a heat dissipation member that includes aluminum, aluminum alloy, magnesium or magnesium alloy and a bonding portion processed to be bonded to the solder material. The metal part of the light-emitting portion is bonded via the solder material to the bonding portion of the heat dissipation member. The solder material includes a material unable to be directly bonded to the heat dissipation member, the metal part of the light-emitting portion is formed by metalizing an insulation of ceramic or semiconductor, and the bonding portion includes a thermal expansion coefficient between that of the heat dissipation member and that of the insulation.

Abstract: A semiconductor material includes a matrix semiconductor includes constituent atoms bonded to each other into a tetrahedral bond structure, and a heteroatom Z doped to the matrix semiconductor, in which the heteroatom Z is inserted in a bond so as to form a bond-center structure with an stretched bond length, and the bond-center structure is contained in a proportion of 1% or more based on the heteroatom Z.

Abstract: Embodiments relate to a semiconductor light-emitting structure. The semiconductor light-emitting structure according to embodiments comprises a plurality of compound semiconductor layers; a current spreading layer comprising a multi-layered transparent electrode layer on the plurality of compound semiconductor layers and a metal layer between the transparent electrode layers; and a second electrode electrically connected to the current spreading layer.

Abstract: A light emitting device includes a gallium oxide based substrate, a gallium oxynitride based layer on the gallium oxide based substrate, a first conductivity-type semiconductor layer on the gallium oxynitride based layer, an active layer on the first conductivity-type semiconductor layer, and a second conductivity-type semiconductor layer on the active layer.

Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.

Abstract: A semiconductor device is formed on a semiconductor substrate, which is comprised of: a base substrate; and a multilayer being formed on the base substrate and having a surface serving for an interface with the semiconductor device, the multilayer including alternating layers of a first compound semiconductor and a second compound semiconductor materially distinguishable from the first compound semiconductor, one selected from the group consisting of the first compound semiconductor and the second compound semiconductor being doped with one selected from the group consisting of carbon and transition elements.

Abstract: A semiconductor device includes a transistor, a conductive pad, and a contact. The conductive pad is electrically connected to the transistor. The conductive pad may include, but is not limited to, a first region and a second region. The contact is electrically connected to the conductive pad. At least a main part of the first region overlaps the transistor in plan view. At least a main part of the second region does not overlap the transistor in plan view. At least a main part of the contact overlaps the second region in plan view. The at least main part of the contact does not overlap the first region in plan view. The at least main part of the contact does not overlap the transistor in plan view.

Abstract: A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.

Abstract: A substrate composed of hexagonally crystalline SiC is prepared such that its main surface is in the direction at which the minimum angle between the main surface and a plane perpendicular to the (0001) plane is one degree or less, for example, in the direction at which the minimum angle between the main surface and the [0001] direction, which is perpendicular to the (0001) plane, is one degree or less. A horizontal semiconductor device is formed on one main surface of the substrate prepared by the foregoing method. Thus, it was possible to improve the value of breakdown voltage significantly over the horizontal semiconductor device in which the main surface of the substrate composed of hexagonally crystalline SiC is in the direction along the (0001) direction.

Abstract: A semiconductor device includes a three-dimensional structure that extends in a channel direction, a stress film having residual stress acting on a first side surface of the three-dimensional structure, a gate insulating film that is formed over a second side surface of the three-dimensional structure, and a gate electrode that covers the three-dimensional structure with the gate insulating film interposed therebetween and extends in a direction in which the first and second side surfaces are opposite to each other. The three-dimensional structure has a channel region between a source electrode and a drain electrode.

Abstract: Embodiments of the present invention are directed to an image sensor having pixel transistors and peripheral transistors disposed in a silicon substrate. For some embodiments, a protective coating is disposed on the peripheral transistors and doped silicon is epitaxially grown on the substrate to form lightly-doped drain (LDD) areas for the pixel transistors. The protective oxide may be used to prevent epitaxial growth of silicon on the peripheral transistors during formation of the LDD areas of the pixel transistors.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device, including: a semiconductor substrate; a transistor that is formed on the semiconductor substrate; an interlayer insulating film that is formed on the semiconductor substrate so as to cover the transistor and that has a through hole formed thereinside so as to reach the transistor; a plug lower-electrode that is formed in the through hole and that is connected to the transistor; a ferroelectric film that is formed on the plug lower-electrode; and an upper-electrode that is formed on the ferroelectric film.

Abstract: A semiconductor memory device has a plurality of first cell selection MOS transistors of a first conductivity type formed on a first element region and connected in series between a bit line and a plate line; a plurality of first ferroelectric capacitors connected to the first cell selection MOS transistors in parallel in one-to-one correspondence; a plurality of second cell selection MOS transistors of the first conductivity type formed on a second element region and connected in series between a bit line and a plate line; and a plurality of second ferroelectric capacitors connected to the second cell selection MOS transistors in parallel in one-to-one correspondence, wherein the first ferroelectric capacitors and the second ferroelectric capacitors are disposed alternately on the first element region and the second element region in the first direction.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device, including a TC unit series-type FeRAM in which a plurality of memory cells, each of the memory cells comprising a memory transistor and a ferroelectric capacitor connected each other in parallel, are serially connected, including, a first electrode over and electrically connected to one of a source and a drain in the memory transistor, a second electrode opposed to the first electrode over and electrically connected to the other of the source and the drain in the memory transistor, a third electrode on both sidewalls of the second electrode other than an under portion of the second electrode, and a ferroelectric film between the first electrode and the two electrodes, the second electrode and the third electrode, wherein the ferroelectric capacitor comprises the first and the third electrode, and the ferroelectric film.

Abstract: An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.

Abstract: System and method for self-aligned etching. According to an embodiment, the present invention provides a method for performing self-aligned source etching process. The method includes a step for providing a substrate material. The method also includes a step for forming a layer of etchable oxide material overlying at least a portion of the substrate material. The layer of etchable oxide material can characterized by a first thickness. The layer of etchable oxide material includes a first portion, a second portion, and a third portion. The second portion is positioned between the first portion and the third portion. The method additionally includes a step for forming a plurality of structures overlying the layer of etchable oxide material. The plurality of structures includes a first structure and a second structure.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor layer as a channel, a conductive layer which is formed on a surface of the semiconductor layer with a first insulating layer and a second insulating layer interposed therebetween and functions as a control gate electrode; and a plurality of first charge storage layers formed between the first insulating layer and the second insulating layer. The plurality of first charge storage layers are formed in isolation from one another along a surface of the first insulating layer. The first insulating layer is formed so as to protrude towards the semiconductor layer at a position where each of the first charge storage layers is formed.

Abstract: A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the substrate and the gate electrode; a charge tunneling layer between the charge trapping layer and the substrate; and a charge blocking layer between the gate electrode and the charge trapping layer. The charge trapping layer includes a first charge trapping layer having a first energy band gap and a second charge trapping layer having a second energy band gap that is different than the first energy band gap. The first and second charge trapping layers are repeatedly stacked and the first and second energy band gaps are smaller than energy band gaps of the charge tunneling layer and the charge blocking layer.

Abstract: A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity region. The single crystalline semiconductor pattern has a pillar shape substantially perpendicular to the substrate. A second impurity region may be formed in an upper portion of the single crystalline semiconductor pattern. The gate insulation layer structure may include a charge storage pattern, the gate insulation layer structure on a sidewall of the single crystalline semiconductor pattern. The gate electrode may be formed on the gate insulation layer structure and opposite the sidewall of the single crystalline semiconductor pattern. The gate electrode has an upper face substantially lower than that of the single crystalline semiconductor pattern.

Abstract: A technique capable of improving the memory retention characteristics of a non-volatile memory is provided. In particular, a technique of fabricating a non-volatile semiconductor memory device is provided capable of enhancing the film quality of a silicon oxide film even when a silicon oxide film as a first potential barrier film is formed with a plasma oxidation method to improve the memory retention characteristics of the non-volatile memory. After a silicon oxide film, which is a main component of a first potential barrier film, is formed with a plasma oxidation method, plasma nitridation at a high temperature and a heat treatment in an atmosphere containing nitric oxide are performed in combination, thereby forming a silicon oxynitride film on the surface of the silicon oxide film, and segregating nitrogen to an interface between the silicon oxide film and a semiconductor substrate.

Abstract: In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

Abstract: A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for GS clamp diodes and avalanche protection for GD clamp diodes.

Abstract: In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.

Abstract: In one embodiment, a contact structure for a semiconductor device having a trench shield electrode includes a gate electrode contact portion and a shield electrode contact portion within a trench structure. Contact is made to the gate electrode and the shield electrode within or inside of the trench structure. A thick passivating layer surrounds the shield electrode in the contact portion.

Abstract: In one embodiment, a structure for a semiconductor device having a trench shield electrode includes a control pad, control runners, shield runners, and a control/shield electrode contact structure. The structure is configured to use a single level of metal to connect the various components. In another embodiment, a shield runner is placed in an offset from center configuration.

Abstract: A semiconductor component that includes an edge termination structure and a method of manufacturing the semiconductor component. A semiconductor material has a semiconductor device region and an edge termination region. One or more device trenches may be formed in the semiconductor device region and one or more termination trenches is formed in the edge termination region. A source electrode is formed in a portion of a termination trench adjacent its floor and a floating electrode termination structure is formed in the portion of the termination trench adjacent its mouth. A second termination trench may be formed in the edge termination region and a non-floating electrode may be formed in the second termination trench. Alternatively, the second termination trench may be omitted and a trench-less non-floating electrode may be formed in the edge termination region.

Abstract: Provided are a semiconductor device and a method for manufacturing the same. In the method, a first conductive type buried layer and a first conductive type drift region are formed on a semiconductor substrate. A gate dielectric and gate electrode are formed in a first trench that extends into the first conductive type drift region. An oxide layer is formed on the semiconductor substrate, and first conductive type source regions are formed at sides of the gate electrode in a second conductive type well on the first conductive type drift region. An interlayer dielectric, the oxide layer, and the second conductive type well are selectively etched, forming a second trench. A tungsten plug is formed on a barrier layer in the second trench. Aluminum is buried on the tungsten plug to form a source contact. A drain electrode layer is formed connected to the first conductive type buried layer.