Abstract: Multi-stack semiconductor packages and application technologies are provided. The multi-stack semiconductor package may include stacked semiconductor packages which may include a topmost semiconductor package and a bottommost semiconductor package. Each of the unit semiconductor packages may include a substrate, a semiconductor chip formed on the substrate, a molding material filled around the semiconductor chip on the substrate, and an adhesive layer formed on the semiconductor chip and the molding material. The semiconductor chip and the substrate of a semiconductor package may each include conductive vias providing an electrical connection between the semiconductor packages. The substrate of the upper semiconductor package stacked in an upper portion may be directly adhered onto the adhesive layer of the lower semiconductor package stacked in a lower portion.

Abstract: Wafer-level chip scale (WLCSP) semiconductor packages and methods for making and using the same are described. The WLCSP semiconductor packages contain a grid array of land pads rather than solder balls or solder bumps. The land pads can be provided directly on a semiconductor wafer by using a leadframe interconnect structure that has been formed from a leadframe. The land pads can be used to mount the WLCSP to a circuit board. Such a configuration allows the formation of a thinner chip scale semiconductor package using a simpler manufacturing process, thereby reducing costs and improving performance. Other embodiments are described.

Abstract: A semiconductor package has a substrate. An opening is formed through the substrate. A first RF shield is formed around a perimeter of the opening. A first die is attached to the first surface of the substrate and positioned over the opening.

Abstract: A carrier substrate has a mounting location with a number of electrical connection pads on a top side and external contacts connected thereto on an underside. A metal frame encloses the connection pads of the mounting location. A MEMS chip has electrical contacts on an underside. The MEMS chip is placed on the mounting location of the carrier substrate in such a way that the MEMS chip is seated with an edge region of its underside on the metal frame. Using a flip-chip process, the electrical contacts of the MEMS chip are connected to the connection pads of the carrier substrate by means of bumps the metal frame is connected to the MEMS chip such that a closed cavity is formed between MEMS chip and carrier substrate.

Abstract: There is provided a semiconductor device including: plural bit cells each including the same circuit; plural electrodes supplied with power from outside, wherein each of the respective plural electrodes is mounted above the same circuit within the plural bit cells. Further, there is provided a semiconductor package including: the semiconductor device; a substrate mounted with the semiconductor device; an external input terminal formed on the substrate; an external output terminal formed on the substrate; an input wiring pattern connecting the semiconductor device mounted above the substrate and the external input terminal; an output wiring pattern connecting the semiconductor device mounted above the substrate and the external output terminal; and plural power supply lines, arranged without contact with each other on the same face of the substrate, and connecting the plural electrodes mounted to the semiconductor device to the corresponding electrode from the plural external power input electrodes.

Abstract: A power semiconductor module comprising: a substrate, a plurality of conductor tracks arranged thereon, the conductor tracks being electrically insulated from one another, and including power semiconductor components arranged thereon; a connecting device, composed of an alternating layer sequence of at least two electrically conductive layers and at least one electrically insulating layer disposed therebetween, for the circuit-conforming connection of the power semiconductor components, the conductor tracks and/or external contact devices. The electrically conductive layers form connecting tracks and at least one transformer is formed integrally with, and thus from the constituent parts of, the connecting device. The transformer is composed of at least one transmitter coil and at least one receiver coil, which are in each case arranged coaxially with respect to one another and are formed with spiral windings.

Abstract: Leadframe-free semiconductor packages and methods for making and using the same are described. The semiconductor packages contain an interconnect structure comprising an array of land pads. The interconnect structure is formed from and routed using a printable or wirebondable conductive material and is not formed using any etching procedure. A solderable mask covers the interconnect structure except for the land pads. A die containing an integrated circuit device is connected to the interconnect structure by either a wirebonding process or by a flipchip process. The land pad arrays can contain a solder connector, such as a solder ball or bump, that can be used to connect the semiconductor package to a printed circuit board. Other embodiments are described.

Abstract: An integrated circuit substrate includes an integrated circuit chip having a plurality of electrically conductive pads on a surface thereof and a printed circuit board mounted to the integrated circuit chip. The printed circuit board includes an alternating arrangement of first and second electrically conductive bond fingers. These first and second bond fingers are elevated at first and second different heights, respectively, relative to the plurality of electrically conductive pads. The printed circuit board also includes a first plurality of electrically insulating pedestals supporting respective ones of the first electrically conductive bond fingers at elevated heights relative to the second electrically conductive bond fingers. First and second pluralities of electrical interconnects (e.g., wires, beam leads) are also provided.

Abstract: A semiconductor device includes: a semiconductor carrier with a top surface on which a plurality of electrodes are disposed; and a semiconductor element electrically connected through a plurality of bump electrodes to the plurality of associated electrodes. The plurality of electrodes are substantially uniformly spaced.

Abstract: In the power semiconductor module, a wiring metal plate electrically connects between power semiconductor elements joined to the circuit pattern, and between the power semiconductor elements and the circuit pattern. Cylindrical main terminals are joined, substantially perpendicularly, to the wiring metal plate and the circuit pattern, respectively. A cylindrical control terminal is joined, substantially perpendicularly, to one of the power semiconductor elements.

Abstract: Provided is a semiconductor device in which a connection between connection terminals and land of the semiconductor device can be checked with the semiconductor device kept in a sound condition, the connection not being allowed to be checked with a semiconductor chip. The semiconductor device of the present invention includes: a package substrate; a semiconductor chip mounted on the package substrate; a first land formed in a first principal surface of the package substrate; a second land formed in a second principal surface of the package substrate; first connection terminals connected to the second land and having the connection thereto not allowed to be checked with the semiconductor chip; a connection interconnection for connecting the first land and the second land; a second connection terminal formed in the second principal surface of the package substrate; and a branch interconnection for connecting the connection interconnection and the second connection terminal.

Abstract: A microelectronic package (31) has a microelectronic device, which is encapsulated in a quantity of material (27), and a lead frame element (15) for enabling the microelectronic device to be electrically contacted from outside of the package (31). The lead frame element (15) comprises at least two elongated members (11) comprising electrically conductive material and a filling material (12) comprising electrically insulating material, wherein the members (11) are partially embedded in the filling material (12). The lead frame element (15) is manufactured by providing elongated members (11), positioning the members (11) according to a predetermined configuration, providing filling material (12) to spaces (13) which are present between the members (11), and possibly removing portions of the filling material (12) and the members (11) in order to expose the electrically conductive material of the members (11).

Abstract: A device including a semiconductor chip. One embodiment provides a device, including a metal layer having a first layer face. A semiconductor chip includes a first chip face. The semiconductor chip is electrically coupled to and placed over the metal layer with the first chip face facing the first layer face. An encapsulation material covers the first layer face and the semiconductor chip. At least one through-hole extends from the first layer face through the encapsulation material. The at least one through-hole is accessible from outside the device.

Abstract: [Summary] [Object] To suppress warpage of a ceramic substrate, and to prevent a reduction in radiation efficiency. [Means for Settlement] A power semiconductor module includes a module casing fitted with a radiator, and a common unit retained by the module casing. The common unit has: a ceramic substrate having a circuit surface disposed with a semiconductor element, and a radiation surface brought into abutting contact with the radiator; and a package formed by exposing the radiation surface and sealing the circuit surface with heat resistant resin. The circuit surface and the radiation surface are respectively formed of metal layers 51 formed on the ceramic substrate, and the metal layer 51 forming the radiation surface has: by forming a buffer pattern 512 including a groove part extending along a circumferential part thereof, a radiation pattern 510 formed on an inner side of the buffer pattern 512; and an outer peripheral pattern 511 formed on an outer side of the buffer pattern 512.

Abstract: A heat dissipation device is provided. The heat dissipation device includes an integrated heat spreader and a base plate coupled to the integrated heat spreader, wherein tile base plate comprises a plurality of metal pellets to dissipate heat from the integrated heat spreader.

Abstract: The power semiconductor module includes: a circuit substrate; power semiconductor elements joined to element mounting portions of the wiring pattern on the circuit substrate; the cylindrical external terminal communication section joined to the wiring pattern; circuit forming means for connecting between portions that require electrical connection therebetween; and transfer molding resin for sealing these components. The cylindrical external terminal communication section is a metal cylinder, and the cylindrical external terminal communication section has a hole filled with gel.

Abstract: Cooling structures and methods, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a cooling structure for a semiconductor device includes at least one channel defined between a first workpiece and a second workpiece. The second workpiece is bonded to the first workpiece. The at least one channel is adapted to retain a fluid.

Abstract: A pressing portion of a fixture is put on a lid of a semiconductor package, and anchor portions on the opposite sides of the pressing portion are opposed to a baseplate. Two screw members are passed individually through opening parts formed spanning the pressing portion and anchor portions and threadedly engage with a heat sink through the baseplate. If the screw members are tightened in this state, the anchor portions are pressed by the baseplate, and the pressing portion presses the lid of the semiconductor package, whereby the baseplate is fixed to the heat sink in pressure contact with it.

Abstract: A semiconductor die includes a semiconductor substrate, electrodes provided on the semiconductor substrate, an isolating layer provided on the electrodes, an upper protective layer provided on the electrodes and the isolating layer, pads provided on the upper protective layer and connectors inserted through the upper protective layer and used to connect the electrodes to the pads. The area of the pads is larger than that of the electrodes.

Abstract: An electronic device includes: a wiring board having first and second regions; a plurality of first lands in the first region; a plurality of second lands in the second region; and an insulator covering the wiring board. More heat is applied to the first region than the second region. The second land is smaller in volume than the first land. The insulator has a plurality of openings being adjacent to the plurality of first lands and the plurality of second lands. Each of the plurality of openings has substantially the same area.

Abstract: Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18?); etching (104) via cavities (29) partly through the wafer (18?) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18?) with its front side (35) facing a support structure (40); thinning (107) the wafer (18?) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.

Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

Abstract: An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).

Abstract: An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer.

Abstract: In a wiring structure of a semiconductor device and a method of manufacturing the same, a wiring structure includes a contact pad, a contact plug, a spacer and an insulation interlayer pattern. The contact pad is electrically connected to a contact region of a substrate. The contact plug is provided on the contact pad and is electrically connected to the contact pad. The spacer faces an upper side surface of the contact pad and sidewalls of the contact plug. The insulation interlayer pattern has an opening, the contact plug and the spacer being provided in the opening. The spacer of the wiring structure may prevent the contact pad from being damaged by a cleaning solution while forming a contact plug to be connected to a capacitor.

Abstract: In a wiring structure between steps in which a step portion is covered by an insulating slope formed by providing and drying droplets of an insulating ink in which an insulating material is dispersed in a dispersion medium and a wiring line formed by drying and firing provided droplets of a conductive ink in which a conductive material is dispersed in a dispersion medium is laid out between the steps and passes on a top surface of the insulating slope, the structure includes a liquid repellent layer formed of a liquid repellent material repelling the dispersion medium in the insulating ink, and a plurality of dot lines including a plurality of dots that is formed by hardening arranged droplets of a resin ink including a resin material. In the structure, the liquid repellent layer covers a surface including the step portion where the wiring line to be laid out.

Abstract: A semiconductor module is disclosed, including a substrate and at least one semiconductor component in bottom contact with the substrate. The semiconductor component including a main current branch sandwiched between the bottom and top of the semiconductor component. The side edges of a barrier layer zone coincide with the side edge portions of the semiconductor component between the top and the bottom. The space above the substrate and to the side of the semiconductor component is packed with an insulating compound at least up to the level of the top of the semiconductor component. Topping the semiconductor component and parallel thereto is a patterned or unpatterned metallization connected to a contact pad on the top of the semiconductor component.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a circuit part, a pad metal aligned over the circuit part to electrically connect the circuit part, and a metal layer interposed between the pad metal and the circuit part to electrically connect the pad metal to the circuit part. A buffer layer including an insulating layer with metal patterns having a slit shape formed therein is formed within the metal layer.

Abstract: Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations.

Abstract: There is provided a method of manufacturing the semiconductor apparatus, including: forming through-hole which penetrates a semiconductor substrate at a point that corresponds to a location of an electrode pad; forming an insulating film on a rear surface of the semiconductor substrate, including the interior of the through-hole; forming an adhesion securing layer from a metal or an inorganic insulator on a surface of the insulating film at least in an opening portion of the through-hole; forming a resist layer to serve as a mask in bottom etching on the adhesion securing layer; performing bottom etching to expose the electrode pad; removing the resist layer to obtain the insulating film free of surface irregularities that would otherwise have been created by bottom etching; forming a barrier layer, a seed layer, and a conductive layer by a low-temperature process; and performing patterning.

Abstract: In a method for manufacturing a semiconductor device, insulation resistance of the porous film is stabilized, and leakage current between adjacent interconnects provides an improved reliability in signal propagation therethrough. The method includes: sequentially forming over a semiconductor substrate a porous film and a patterned resist film; forming a concave exposed surface of the substrate; forming a non-porous film covering the interior wall of the concave portion and the porous film; selectively removing the non-porous film from the bottom of the concave portion and the non-porous film by anisotropic etch; forming a barrier metal film covering the porous film and the interior wall; and forming a metallic film on the barrier metal film to fill the concave portion. The anisotropic etch process uses an etching gas with mixing ratio MR, 45?MR?100, where MR=((gaseous “nitrogen” containing compound)+(inert gas))/(gaseous “fluorine” containing compound).

Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

Abstract: There is provided a semiconductor device including: plural first output pads formed along one edge of an outer periphery of a substrate; plural second output pads formed along at least one of an edge at an opposite side of the substrate from the one edge, and an edge adjoining the one edge; plural internal circuits, each of which is provided with an output terminal connected with an output pad of one of the first output pads and the second output pads; plural first lines, each of which connects one of the output terminals of the internal circuits with one of the plurality of first output pads; and plural second lines, each of which connects one of the output terminals of the internal circuits with one of the plural second output pads, resistance values per unit of wiring length being lower in the second lines than in the first lines.

Abstract: A two-sided substrateless multichip module including at least one die layer having at least one die. At least one bottomside interconnect layer is coupled to a bottom surface of the at least one die. At least one topside interconnect layer is coupled to a top surface of the at least one die. One or more embedded electrical connections is configured to provide an electrical interconnection between the at least one bottomside interconnect layer and the at least one die and/or the at least bottomside interconnect layer and the at least one topside interconnect layer and/or the at least one topside interconnect layer and the at least one die, wherein the at least one bottomside interconnect layer includes one or more electrical contacts on a bottom surface of the multichip module and the at least topside interconnect layer includes one or more electrical contacts on a top surface of the multichip module.

Abstract: A bonding pad structure for an optoelectronic device. The bonding pad structure comprises a carrier substrate having a bonding pad region and an optoelectronic device region. An insulating layer is disposed on the carrier substrate, having an opening corresponding to the bonding pad region. A bonding pad is embedded in the insulating layer under the opening to expose the top surface thereof. A device substrate is disposed on the insulating layer corresponding to the optoelectronic device region. A cap layer covers the device substrate and the insulating layer excluding the opening. A conductive buffer layer is disposed in the opening to directly contact the bonding pad. The invention also discloses a method for fabricating the same.

Abstract: A microelectronic device wafer includes an adhesive molded in-situ on the wafer. Adhesives and wafers are positioned in molds and a method that includes drawing in the molds at least a partial vacuum and partially curing the adhesive provides an in-situ molded adhesive that is positioned on the wafer. The adhesives can be in liquid, solid, or other forms prior to molding. During molding, the adhesive can be partially cured by heating or irradiating.

Abstract: The invention relates to a method and a device for the metered release of irritants by means of a propellant and/or solvent gas in anti-people defense rooms. The invention describes a method and a device for a metering controller for releasing irritants by means of a propellant and/or solvent gas in anti-people defense rooms while complying with health limits. After a first dose (TE), subsequent dosages (TN) are carried out in time intervals, so that both a hazardous limit of a concentration of the irritants in the room (1) is not exceeded and that also a sufficiently effective concentration is always met, and the concentration-lowering losses (SF, SV) arising from the agent, system and environment are compensated for. The concentration losses are detected metrologically and/or as parameter-dependent variables (SF, Sv) and made available as a program solution of the control device (7).

Abstract: A method of manufacturing an optical member by mixing isocyanate terminal prepolymer component (A) and aromatic diamine component (B), and immediately after mixing, casting a mixture into a casting mold to obtain a molded article. A method of manufacturing a plastic lens by mixing said components (A) and (B), immediately after mixing, casting a mixture into a casting mold and polymerizing it to obtain a molded article. A gasket for molding plastic lenses comprised of a cylindrical member. A casting mold for molding plastic lenses using this gasket and a monomer casting jig.

Abstract: A method and apparatus used for forming a lens master for forming lenses on a wafer. The method includes using an inverted lens pin mold in conjunction with a dispense method to create both concave and convex lens masters for making lens stamps containing lens-shaped cavities. The lens-shaped cavities are used to imprint a plurality of lenses into a curable material.

Abstract: A method for manufacturing a plastic lens includes: disposing a pair of plastic lens molding dies in such a way that the dies face each other and are spaced apart from each other by a predetermined distance; forming a frame between the pair of dies; injecting a polymerizable composition into the space surrounded by the frame and the pair of dies; and polymerizing the polymerizable composition in the space to form a plastic lens.

Abstract: The present invention relates to lipid based nanoparticles or liposomes that are sensitive to ultrasonic energy, compositions containing these particles, methods for delivering one or more active agents using the particles, and methods for preparing the particles. The nanoparticles and liposomes encapsulate active agents such as chemotoxins, genes, virus vectors, proteins, peptides, antisense oligonucleotides, carbohydrates, and stem cells. The particles contain an aqueous core, at least one active agent located within the aqueous core, and a lipid bilayer or membrane that encapsulates the active agent within the aqueous core. The lipid bilayer may comprise a primary phospholipid and a lysolipid that preferably have different acyl chain lengths, making the lipid bilayer sensitive to ultrasound. Ultrasound may be used to track the particles as they move throughout the body. When the ultrasonic energy reaches a certain pressure, the lipid bilayer will break apart, releasing the active agent.

Abstract: Provided are a method for forming polyurea microcapsules containing a saturated alcohol as a dispersion medium, and microcapsules prepared using the method. According to the method, suspensions, in which microcapsules are dispersed in a saturated alcohol dispersion medium as a core material, may be used to prepare microcapsules. Diverse and fine color expression may be obtained from various response characteristics in the display applications. In addition to superior processibility, excellent thermal stability, solvent resistance, and chemical stability may be achieved by using polyurea in microcapsules as a wall material according to one embodiment of the present invention.

Abstract: The apparatus for manufacturing solid particles at a nano level includes a chamber for isolation from an external space, a monoaxial rotary disk disposed in the chamber, a receiving surface at one end of the rotary disk, a material supply mechanism for supplying the material to the receiving surface, a rotary mechanism for applying a centrifugal force to the rotary disk so that the raw material supplied to the receiving surface is produced into a thin film and atomized and scattered from the outer peripheral edge, and a control mechanism for the temperature in the chamber that controls the temperature at least at the outer peripheral edge of the receiving surface and on the side nearer to the center of rotation to a temperature lower than a volatilization temperature of a volatile solvent and the temperature at the outer side therefrom to the volatilization temperature of the volatile solvent or higher.

Abstract: A venting device for venting a cavity of an injection mold via a venting opening of the injection mold which cavity can be filled with an injection molding material is provided. The venting device comprising a housing which has a through-opening and is designed and intended for an arrangement on an injection mold in such a way that air which is present in the cavity and which escapes from a venting opening of the injection mold when injection molding material is introduced into the cavity can exhaust through the through-opening of the housing into an exterior space surrounding the injection mold. A valve pin extending longitudinally along a direction of extent and being mounted in the housing movably along its direction of extent. The valve pin is designed for being moved from a venting position, in the direction of the cavity into a first cleaning position.

Abstract: The present disclosure relates to methods and apparatuses for continuous firing of shaped bodies in one cycle, in particular a continuous method for heat treatment and/or control oxidation of shaped bodies by passing them through a roller hearth furnace on furnace trays.

Abstract: Honeycomb shapes are extruded from plasticized ceramic powder mixtures by methods that include reducing the core temperature of the charge of the plasticized mixture during transit through the extruder, such methods being carried out utilizing apparatus comprising twin-screw extruders incorporating actively cooled screw elements, whereby temperature-conditioned charges of plasticized material that exhibit reduced core-to-periphery temperature differentials are delivered for extrusion.

Abstract: An apparatus for forming a shaped article having a first surface with a first surface profile and a second surface with a second surface profile is provided. The apparatus includes a first end mold having a cavity formed therein, where the cavity is defined by a surface having at least a portion of the first surface profile. The apparatus includes an intermediate mold having a hole formed therein. The intermediate mold is distinct from the first end mold and is configured for stacking against the first end mold such that the hole is aligned with the cavity. The apparatus includes a second end mold having a protuberance formed on a surface thereof. The protuberance is defined by a surface having at least a portion of the second surface profile and is sized for insertion into the hole and cavity.

Abstract: Disclosed herein are methods of making shaped bodies, such as carbon-based, inorganic cement, or ceramic bodies. Methods disclosed herein may comprise applying a bidirectional gas flow to at least one heat treatment and/or controlled oxidation step. Also disclosed herein are methods of making shaped bodies comprising a single-step controlled oxidation firing process. Further disclosed herein are shaped bodies made by a process comprising applying a bi-directional gas flow to at least one heat treatment and/or controlled oxidation step, and shaped bodies made by a single-step controlled oxidation firing process. Further disclosed herein is a bidirectional gas flow furnace for the heat treatment and/or the controlled oxidation of a shaped body.

Abstract: The invention relates to a continuous method for the direct production of multilayer mold bodies from a highly condensed polyester melt.

Abstract: On producing a ferrite sintered body, there is used a ferrite powder having a median diameter D50 [?m] in a range from 0.1 to 0.8 ?m, a degree of spinel formation in a range from 45 to 90%, and a remanent magnetization Br per unit mass [emu/g] satisfying the following formula after application of the maximum magnetic field of 15 kOe:_0.05?Br?2.0(ln.D50)+6.3. The above ferrite powder allows producing a homogeneous ferrite sintered body generating very few cracks by gel casting.