Abstract: A cellular phone. The cellular phone comprises a connector, a first memory module, a second memory module, and a controller. The connector is used for physically connecting the cellular phone to an external device. The first memory module stores phone data. The second memory module stores application data received from the external device. The controller determines whether the connector is connected to the external device. If the connector is not connected to the external device, access right of both the first and second memory modules is granted exclusively to the cellular phone. If the connector is connected to the external device, access right of the first memory is granted exclusively to the cellular phone, and access right of the second memory module is granted exclusively to the external device.

Abstract: Transferring data elements from a source to a destination includes providing a transmission queue at the source, where data elements in the transmission queue are transferred from the source to the destination, determining an optimal length for the transmission queue, where the optimal queue length is inversely proportional data latency time at the destination, and, if the optimal length is greater than an instantaneous length of the transmission queue, adding data elements to the transmission queue. Adding data elements may include adding a number of elements corresponding to a difference between the optimal length and the instantaneous length of the transmission queue. Determining optimal length may include dividing a constant by the data latency time at the destination. Transferring data elements may also include providing a network between the source and the destination.

Abstract: A method comprises providing a free buffer pool in a memory including a non-negative number of free buffers that are not allocated to a queue for buffering data. A request is received to add one of the free buffers to the queue. One of the free buffers is allocated to the queue in response to the request, if the queue has fewer than a first predetermined number of buffers associated with a session type of the queue. One of the free buffers is allocated to the queue, if a number of buffers in the queue is at least as large as the first predetermined number and less than a second predetermined number associated with the session type, and the number of free buffers is greater than zero.

Abstract: An apparatus and method is provided to facilitate Input/Output (I/O) transfer in resource limited storage environment. Scatter gather list, segment and memory data buffer allocation are dynamically managed. I/O transfer performance is increased through the use of a data cut-through buffer mechanism.

Abstract: A method for defining a cycle time for a transmission cycle on a system bus of a monitoring and/or control system having at least one communication module and at least one input/output module, which is connected to the communication module via the system bus for transmitting measurement and/or control signals and is intended to input and/or output measurement and/or control signals to field applications, the at least one communication module having a time control unit for controlling a transmission cycle which is constantly repeatedly carried out and has defined communication times for the communication and input/output modules which are connected to the system bus, comprises measuring the signal propagation times on the system bus and defining the cycle time for a transmission cycle on the system bus on the basis of the longest signal propagation time measured.

Abstract: A process for configuring a computing device to operate with a peripheral device having a configuration control and that is coupled to the computing device via a network, including: detecting activation of the configuration control at the peripheral device; receiving information associated with a user of the computing device at the peripheral device; outputting information from the peripheral device dependent on the received information; and configuring the computing device to operate with the peripheral device using the outputted information.

Abstract: A communication converter includes: a first communication interface making capable of communicating with a medical control device through a predetermined communication cable; a second communication interface making capable of making a connection to a signal distribution unit which is provided in a housing device capable of housing one or more communication converters, and distributes a signal from the medical control device to each of the communication converters; a switch unit for switching communication lines to either a communication line through the first communication interface or a communication line through the second communication interface; a detection unit for detecting whether or not the signal distribution unit is connected to the second communication interface; a switch control unit for controlling the switch unit based on a detection result; and a third communication interface making capable of performing communications with a medical device.

Abstract: A KVM switch system with external control functionality is described. A KVM switch is able to be controlled from an external device. The external device can either include a single button dedicated to controlling the desktop KVM switch or indicate a state of the KVM switch. The external device can be connected to the desktop KVM switch through a plurality of communication media. The external device can be small in size and attached to an object on a user's desktop.

Abstract: Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.

Abstract: A system for setting addresses includes a master device, a plurality of slave devices, and a bus. The master device includes a broadcasting module, a reading module, a responding module, an address assigning module, and a first judging module. Each slave device includes a performing module and a requesting module. The broadcasting module is configured to send messages to the slave devices. The performing module is configured to put the slave device be in an address setting mode. The reading module is configured to read a time assignment for each slave device from a timing module. The requesting module is configured to send an address request. The responding module is configured to respond to the address request. The address assigning module is configured to assign an address to the slave device. The first judging module is configured to check if all the time windows for the slave devices have elapsed.

Abstract: A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system.

Abstract: A bus of a SoC (system on chip) includes a system arbiter for controlling not only a command arbiter but also a read information arbiter, a write data control circuit, a write complete notice arbiter and the like. A sequential table containing a series of system operations including activation processing and application processing and an operation clock information circuit or the like that becomes effective when a SoC bus region is divided by an operation clock frequency are utilized in assignment of priority of buses of the system arbiter. Thus, the information transfer efficiency of the whole system bus and the information transfer efficiency of every transfer originator can be improved.

Abstract: An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in a plurality of execution environments (EE) selectively wherein a said execution environment (EE) is activated or suspended, a first configuration register (SCR) coupled to the processing circuit (2610) for identifying the interrupt request as an ordinary interrupt request IRQ when the execution environment (EE) is activated (EE_Active); and a second configuration register (SSM_FIQ_EE_y) for associating an identification of that execution environment (EE) with the same interrupt request, the processing circuit (2610) coupled (5910) to the second configuration register (SSM_FIQ_EE_y) to respond to the same interrupt request as a more urgent type of interrupt request when that execution environment (EE) is suspended (5920).

Abstract: In a device control apparatus, a processor that operates according to software, an OS storage unit stores Operating Systems that operate on the processor, and a storage unit stores privileged software which operates on the processor. The privileged software calls one of the Operating Systems when the processor receives an interrupt from a device, and the Operating System controls the device. Furthermore, a detecting unit detects an interrupt to the processor, a judging unit judges whether the Operating System has called the privileged software from the storage unit in a first predetermined time from detection of the interrupt, and a resetting unit resets the processor when the judging unit judges that the Operating Systcm 9em has not called the privileged software from the storage unit.

Abstract: An interrupt control circuit includes: a section that generates an interrupt signal for requesting an interrupt in response to occurrence of a plurality of interrupt causes; a section that generates an interrupt vector signal for indicating a storing destination of an interrupt processing program corresponding any of the plurality of interrupt causes; a section that outputs the interrupt signal and the interrupt vector signal to an interrupt process executing circuit; and a section that controls the interrupt signal and an output value of the interrupt vector signal in sync with an interrupt acceptance signal input from the interrupt process executing circuit, the interrupt acceptance signal representing a condition in which an interrupt process is acceptable.

Abstract: A support identification device comprising a support (BPA), e.g. a rack or backplane of a telecommunication system, and an identity receiver (PCB), e.g. a printed circuit board or card, coupled to an identity transmitter or connector of the support. The identity transmitter has several read pins (id1-id4=R1-R4) each at a logical level (0, 1) to indicate (identify) the type of support. The card (PCB) further has write terminals (W1, W2) coupled to dynamic terminals (D1, D2) of the support (BPA). These dynamic terminals are coupled to one or more of the read pins (id1-id4). The card is also provided with a program that sets the write terminals at a first logical level, reads a first logical level at each read pin (R1-R4), then sets the write terminals at a second logical level, reads a second logical level at each read pin, and determines from the difference between the first and the second read logical levels to which write terminal each read terminal is coupled, or not.

Abstract: Embodiments of the invention include a method, apparatus and system for managing SAS zoning, using connector grouping. A connector grouping management application is configured to allow connectors on the edge of the ZPSDS to be grouped into defined zones. The defined zones are used to create a minimal number of zone groups and to configure the respective permissions of the zone groups. The connector grouping application then compares all existing zone groups for phys common to more than one zone group. The connector grouping application removes all phys common to more than one zone group from the respective zone groups and moves the common phys to a new zone group. The zone groups are processed in this manner until no zone groups have common phys. Once all zone groups have been processed accordingly, information associated with the resulting zone groups and their respective permissions are transferred to the zone manager.

Abstract: The invention relates to a system and method for controlling implementation of a command to a memory device. In the method, it comprises the following steps: monitoring an instruction stream destined for the memory device for an assertion of a command for the memory device; if the command is detected, evaluating whether the command is a restricted command; and if the command is a restricted command, preventing assertion of the command on the memory device.

Abstract: A memory buffer for an FB-DIMM having a first input/output interface for communicating with a memory controller at a first payload data rate and a second input/output interface for communicating with memory packages at a second payload data rate, wherein a relation of the first payload data rate to the second payload data is greater than 10.

Abstract: A recording apparatus for recording data in individual blocks each made of plural given regions on an optical disc is disclosed. The recording apparatus may have (i) a detection portion which detects a finally recorded region on the disc by detecting for each of the given regions as to whether or not data is recorded and (ii) a recording control portion which records dummy data from a region next to the finally recorded region detected by the detection portion to the final region of a block located behind the finally recorded region by at least one region and then starting to record data from the head region of the subsequent block.

Abstract: Herein described is at least a method and system for improving the performance of a disk drive. A cache work queue and a disk work queue operate together as a dual work queue to facilitate efficient processing of one or more read/write operations performed by the disk drive. In a representative embodiment, the disk drive controller comprises a host interface, a cache buffer, and a disk drive media interface. The disk drive controller comprises the necessary circuitry to execute one or more host commands provided by a host computer. Further, the disk drive controller may facilitate the generation of the cache work queue and the disk work queue. The disk drive controller executes one or more host commands that are received through the host interface such that the cache work queue and disk work queue are employed when a read or write operation is performed.

Abstract: A method and related computer program product for achieving high performance I/O write rates in a redundant array using a fully recoverable communication queue stored in NVRAM on a RAID controller comprising, receiving an I/O write request from an application, determining if the I/O request is an inline write command, writing inline write commands into a command queue stored in NVRAM, notifying the application generating the I/O request of command completion and requesting the operating system for further I/Os.

Abstract: A system and method manages lock state information in a storage system. A meta-data volume node includes a lock state database which is a comprehensive source for lock state information about data containers in the system. A plurality of data volume nodes include local lock caches, which contain information about locks. Lock state messaging between the meta-data volume node and the data volume nodes is used to assign locks and to update local lock caches. The meta-data volume node is configured to determine whether input/output requests should be allowed or denied and to instruct the data volume nodes of this input/output operation result. Lock information is also sent to the data volume nodes for storage in local lock state caches to the extent the data volume nodes have the network capacity locally.

Abstract: Provided is a storage subsystem configuration management method for use in a computer system, comprising: obtaining storage configuration information and hardware resource use information; determining, based on the obtained hardware resource use information, a configuration of a storage subsystem so that a load is not concentrated on a specific hardware resource; transmitting a configuration change instruction to make a change to the determined configuration to the storage subsystem; and making a configuration change based on the configuration change instruction received from the management computer through the first interface.

Abstract: Data hologram recycling systems, methods and computer program products are configured to arrange data for storage in the intermediate data storage as data segments which are replicas of holographic storage segments for destaging to the holographic data storage, and to determine retrieval for recycling of the destaged holographic storage segments to which aggregated requests for deletion are directed. The retrieval determination may be based on a plurality of policies.

Abstract: A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directly accessible to the plurality of processing units. The shared memory may be a cache memory that stores instructions and/or data. The shared memory includes a multitude of banks, a first subset of which may store data and a second subset of which may store instructions. A conflict detection block resolves access conflicts to each of the of the banks in accordance with a number of address bits and a predefined arbitration scheme. The conflict detection block provides each of the processing units with sequential access to the banks during consecutive cycles of a clock signal.

Abstract: A method and system for dynamic distributed data caching is presented. The method includes providing a cache community comprising at least one peer. Each peer has an associated first content portion indicating content to be cached by the respective peer. A client may be allowed to join the cache community. A peer list associated with the cache community is updated to include the client. The peer list indicates the peers in the cache community. A respective second content portion is associated with each peer based on the addition of the client.

Abstract: A prefetching technique referred to as future execution (FE) dynamically creates a prefetching thread for each active thread in a processor by simply sending a copy of all committed, register-writing instructions in a primary thread to an otherwise idle processor. On the way to the second processor, a value predictor replaces each predictable instruction with a load immediate instruction, where the immediate is the predicted result that the instruction is likely to produce during its nth next dynamic execution. Executing this modified instruction stream (i.e., the prefetching thread) in another processor allows computation of the future results of the instructions that are not directly predictable. This causes the issuance of prefetches into the shared memory hierarchy, thereby reducing the primary thread's memory access time and speeding up the primary thread's execution.

Abstract: In one embodiment, the present invention includes a method for routing an early request for requested data on a bypass path around a transaction processing path of a first agent if the requested data is not present in a cache memory of the first agent, and opportunistically transmitting the early request from the first agent to a second agent based on load conditions of an interconnect between the first agent and the second agent. In this way, reduced memory latencies may be realized. Other embodiments are described and claimed.

Abstract: One embodiment of the present invention provides a system that facilitates efficient transactional execution. During operation, the system executes a starvation-avoiding transaction for a thread, wherein executing the starvation-avoiding transaction involves: (1) placing load-marks on cache lines which are loaded during the starvation-avoiding transaction; (2) placing store-marks on cache lines which are stored to during the starvation-avoiding transaction; and (3) writing a timestamp value into metadata for load-marked and store-marked cache lines. While the thread is executing the starvation-avoiding transaction, the system prevents other threads from executing another starvation-avoiding transaction. Whereby the load-marks and store-marks prevent interfering accesses from other threads to the cache lines during the starvation-avoiding transaction.

Abstract: Snoop filtering methods and apparatuses for systems utilizing memory are contemplated. Method embodiments comprise receiving a request for contents of a memory line by a home agent, comparing an address of the memory line to a range in a set of adaptive ranges, and snooping an I/O agent for the contents upon a match of the address within the range. Apparatus embodiments comprise a range table, a table updater, a receiver module, and a range comparator. The range tables allow for the tracking of memory addresses as I/O agents assert ownership of the addresses. Employing a range-based snoop filtering approach may allow home agents to track a collection of addresses, in adaptable ranges, instead of tracking precise addresses which may require large quantities of memory to implement.

Abstract: Provided are a method, system and program for selecting storage clusters to use to access storage. Input/Output (I/O) requests are transferred to a first storage cluster over a network to access storage. The storage may be additionally accessed via a second storage cluster over the network and both the first and second storage clusters are capable of accessing the storage. An unavailability of a first storage cluster is detected when the second storage cluster is available. A request is transmitted to hosts over the network to use the second storage cluster to access the storage. Hosts receiving the transmitted request send I/O requests to the storage via the second storage cluster if the second storage cluster is available.

Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Abstract: A computer implemented method for reducing communication signaling protocol latency. An acceptable level of latency is specified. Automatic memory management activities are monitored based on specified parameters to calculate a level of activity that determines whether a reduction of activity is required.

Abstract: An information storage arrangement that combines rewriteable storage with one-time programmable (OTP) storage is managed in a manner that makes judicious use of the OTP storage. It is therefore possible to exploit the economic advantage associated with OTP storage, while also avoiding storage capacity losses that would otherwise be associated with OTP storage.

Abstract: An automated data storage library accesses data stored on storage media contained in cartridges in response to commands from an external host. The cartridges include cartridge memory and a component in the library includes a cartridge memory interface for reading data from and/or writing data to the cartridge memory. When a cartridge is to be stored in the library, the library modifies the contents of the cartridge memory such that the data stored on the cartridge becomes inaccessible, thereby preventing access to the data outside of the library. To perform an authorized access, the library restores the contents of the cartridge memory or provides a correction or correction algorithm to allow access to the data without removing the access protection of the storage media. The cartridge memory may also or alternatively include an identifier which permits access to the data only by the identified physical and/or logical library(s).

Abstract: A non-volatile memory device includes an input/output terminal mixing section configured to couple data input/output terminals of the memory device to data input/output terminals of a page buffer in accordance with a user selection. A user data authenticating section is configured to transmit a control signal to the input/output terminal mixing section so that the input/output terminal mixing section couples the data input/output terminals of the memory device to the data input/output terminals of the page buffer in accordance with the user selection. A spare cell is configured to store the coupling configuration of the data input/output terminals of the memory device and the data input/output terminals of the page buffer in accordance with the user selection.

Abstract: A method for securing a memory area comprising data blocks, wherein at least two control bits are associated with each data block, is provided. The method comprises a step of reading the control bits associated with a current data block intended to be replaced with the new data block, before the writing of a new data block in the memory area. A securing action for securing the memory area is begun if the two control bits have the same value. Upon each write of a new data block in the memory area, control bits having opposite values are written in the memory area. The method may be applied, for example, to the securization of a binary counter.

Abstract: Procedures and systems for avoiding undesired trespass may be deployed in host processors that use storage arrays with automated fail-back and fail-over functions. In one embodiment, a method may synchronize path records in a storage array with path records in a host processor. The method may detect a failure of a first data path through a first controller on the storage array to a logical unit (LUN) on the storage array. In response to the failure, the host processor may initiate a failover on the storage array of the LUN, so that the LUN is accessed through a backup controller on the storage array. The host processor may also issue commands to pin the failed-over LUN to the backup controller. For example, the host processor may issue commands to set the default owner of the LUN to be the backup controller.

Abstract: In an information processing system including a computer device, and a storage device storing data used by the computer device, the region in which the data is held is managed in association with a change, over the passage of time in the performance and availability required of the data holding region. The computer device includes a storage device managing unit for managing the storage device which stores data used by the computer device. The storage device managing unit periodically monitors temporal characteristics information, and moves data, if the storage region having functional characteristics corresponding to the temporal characteristics information is different from the storage region to which the data is currently assigned.

Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.

Abstract: A multi-stage technique invalidates and replaces loadable physical volume block numbers (pvbns) stored in indirect blocks of a dual vbn (“flexible”) virtual volume (vvol) of a storage system to enable efficient image transfers and/or fragmentation handling of the flexible vvol. Each loadable pvbn of a pvbn/virtual vbn (vvbn) block pointer pair is converted into a special block pointer having a predefined reserved value that provides a temporary “pvbn_unknown” placeholder until replaced by a real (actual) pvbn. The technique further allows the storage system to serve data from the flexible vvol using the placeholders while the actual pvbns are computed, thereby eliminating latencies associated with completion of actual pvbn replacement for the pvbn_unknown placeholders.

Abstract: A mechanism is disclosed for storing one or more chunk-specific sets of executable instructions at one or more predetermined offsets within chunks of a chunked heap. The mechanism provides for storing a chunk-specific set of executable instructions within a portion of a chunk, where the set of executable instructions begins at a predetermined offset within the range of virtual memory addresses allocated to the chunk. The set of executable instructions, when executed, is operable to perform one or more operations that are specific to the chunk.

Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread start (Tstart) instruction, which causes the control processor to pause its instruction fetching. A local PE instruction memory (PE Imem) is associated with each PE and contains local PE instructions for execution on the local PE. Local PE Imem fetch, decode, and execute logic are associated with each PE. Instruction path selection logic in each PE is used to select between control processor distributed instructions and local PE instructions fetched from the local PE Imem. Each PE is also initialized to receive control processor distributed instructions. In addition, local hold generation logic is associated with each PE. A PE receiving a Tstart instruction causes the instruction path selection logic to switch to fetch local PE Imem instructions.

Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

Abstract: A method and system for avoiding various hazards for instructions which are propagating through a microprocessor pipeline. When a plurality of instructions exist within the pipeline which read and write the same value, a vector is established to distinguish the older from the newer instructions. Further, before instructions are dispatched for execution, pointers are generated which identify the particular instruction which had the operand or parameter value needed. Accordingly, by monitoring both the recent vector and pointers, dated dependency hazards can be avoided.

Abstract: Embodiments of the invention provide a processor for executing instructions. In one embodiment, the processor includes circuitry to receive a load instruction and a store instruction to be executed in the processor and detect a conflict between the load instruction and the store instruction. Detecting the conflict includes determining if load-store conflict information indicates that the load instruction previously conflicted with the store instruction. The load-store conflict information is stored for both the load instruction and the store instruction. The processor further includes circuitry to schedule execution of the load instruction and the store instruction so that execution of the load instruction and the store instruction do not result in a conflict.

Abstract: An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to selectively disable storing of the results in the register file under control of the instructions.

Abstract: A data processing system includes a plurality of functional units that selectively execute instructions. A register file includes a plurality of registers that store data corresponding to the instructions. A reorder buffer communicates with the register file and stores the data, includes at least one bypassable buffer location, and includes at least one non-bypassable buffer location.