Abstract: An image sensor including a substrate and an interlayer dielectric layer divided into a pixel region and a logic pad region. An image sensor may include at least one of the following: a color filter, an over coating layer, and a micro lens sequentially formed over the interlayer dielectric layer in the pixel region; a top conductive layer formed over the interlayer dielectric layer of the logic pad region; an etch stop layer formed over the interlayer dielectric layer in the logic pad region and on the sides and a portion of an upper surface of a top conductive layer; and a first and second protective layers sequentially formed over the etch stop layer.

Abstract: A method is disclosed which includes providing an imager substrate comprised of at least one imager device, providing a transparent substrate, forming a plurality of standoff structures on one of the imager substrate and the transparent substrate, the standoff structures having a width, forming an adhesive material having an initial thickness on a surface on at least one of the standoff structures, the adhesive material having an initial width that is less than the width of the standoff structures, and urging one of the imager substrate and the transparent substrate toward the other until such time as the imager substrate and the transparent substrate are in proper focal position relative to one another, the urging causing the initial thickness of the adhesive material to be reduced to a final thickness that is less than the initial thickness.

Abstract: Embodiments relate to an image sensor and a method for manufacturing the same. According to embodiments, a semiconductor substrate may include a pixel part and a peripheral part. A photo diode pattern may be formed over the pixel part having a height that is greater than a height of a surface of an interlayer dielectric film over the peripheral part. A device isolation film and a metal layer may be provided over the photodiode and over interlayer dielectric film over the peripheral part. A planarization layer may be provided and may compensate for a height difference so that a first metal film pattern connected to the photo diode pattern and a second metal film pattern connected to the metal wire in peripheral part may be simultaneously formed by patterning the planarization layer and metal film.

Abstract: An image sensor including a first region where a pad is to be formed, and a second region where a light-receiving element is to be formed. A pad is formed over a substrate of the first region. A passivation layer is formed over the substrate of the first and second regions to expose a portion of the pad. A color filter is formed over the passivation layer of the second region. A microlens is formed over the color filter. A bump is formed over the pad. A protective layer is formed between the bump and the pad to expose the portion of the pad.

Abstract: An image device which includes reflowed color filters. Reflowed color filters may be formed by heat treating preliminary color filters. When preliminary color filters are reflowed, color filters of different colors may be formed continuous with each other. Contiguous color filters in an image device may reduce manufacturing costs, maximize optical efficiency, minimize noise, and/or minimize crosstalk.

Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor can comprise a substrate, a metal pad, and a sulfur layer. The substrate can include a pixel region and a pad region. The metal pad can be formed of a material containing sulfur and can be disposed in the pad region of the substrate. The sulfur layer can be formed from the sulfur of the metal pad and provided on a top surface of the metal pad.

Abstract: A pillar-type phase change memory element comprises first and second electrode elements and a phase change element therebetween. A second electrode material and a chlorine-sensitive phase change material are selected. A first electrode element is formed. The phase change material is deposited on the first electrode element and the second electrode material is deposited on the phase change material. The second electrode material and the phase change material are etched without the use of chlorine to form a second electrode element and a phase change element. The second electrode material selecting step, the phase change material selecting step and the etching procedure selecting step are carried out so that the phase change element is not undercut relative to the second electrode element during etching.

Abstract: A sputtering target, including a sputtering layer and a support structure. The sputtering layer includes an alkali-containing transition metal. The support structure includes a second material that does not negatively impact the performance of a copper indium selenide (CIS) based semiconductor absorber layer of a solar cell. The sputtering layer directly contacts the second material.

Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors, as well as us of patterned substrates to grow oriented nanowires. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrificial growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

Abstract: A phase change memory device includes a silicon substrate having a phase change cell region. A plurality of phase change cell are formed in the phase change region of the silicon substrate. A contact comprising a first contact and a second contact is formed on each of the phase change cells. A plurality of bit lines are electrically connected to the contacts. A contact plug is formed on the silicon substrate in a region outside of the phase change cell region, and a word line is formed over the silicon substrate and is connected to the contact plug.

Abstract: A method for making semiconductor chips having coated portions can include mounting the chips in lead frames, stacking the lead frames in an orientation in which a portion of one lead frame masks a portion of a chip mounted on another lead frame but leaves another portion of the chip mounted on the other lead frame exposed to receive a coating, and depositing a coating on the stacked lead frames using, for example, an evaporative coating machine. In this manner, the coating is deposited on exposed portions of chips, such as its edges, and is not deposited on masked portions of chips, such as bond pads.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a stack board with a side having a connect contact next to a connect edge and a top contact next to a top edge perpendicular to the connect edge, and a bottom contact on an opposite side; mounting a circuit assembly having an assembly end next to the connect contact and an edge pad over the stack board; connecting the edge pad with the stack board; and applying an edge encapsulant over the connect contact and over the assembly end with the edge encapsulant extending no more than half the width of the stack board.

Abstract: A first semiconductor element is bonded on a substrate. A complex film formed of integrated dicing film and adhesive film is affixed on a rear surface of a semiconductor wafer which is to be second semiconductor elements, the dicing film having a thickness within a range of not less than 50 ?m nor more than 140 ?m and a room temperature elastic modulus within a range of not less than 30 MPa nor more than 120 MPa, and the adhesive film having a thickness of 30 ?m or more and a room temperature elastic modulus before curing within a range of not less than 500 MPa nor more than 1200 MPa. The semiconductor wafer together with the adhesive film is divided into the second semiconductor elements. The second semiconductor element is picked up from the dicing film to be bonded on the first semiconductor element.

Abstract: A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration.

Abstract: A method of manufacturing an integrated circuit (IC) device is disclosed. A wafer including multiple dies is processed to form solder bumps at the bond pad locations. A conductive substrate is patterned for routing traces and connection pads and partially etched. Routers are formed to electrically route a connection pad to the interior of its corresponding routing terminals. The etched connection pads corresponds to the plurality of bond pad locations of the IC chip. The bumped IC chip is aligned and attached to the conductive substrate through the connection pads and solder bumps. The attached IC chip and the first side of the conductive substrate are then encapsulated. Un-processed conductive material is then removed from a second side of the substrate, opposite the first side, to expose the routers and routing terminals.

Abstract: The present invention provides a mountable integrated circuit package system comprising: providing an inner integrated circuit package including a first external interconnect having a shoulder; connecting an intraconnect between a second external interconnect and the shoulder; and forming an outer encapsulation over the inner integrated circuit package, the intraconnect, and partially exposing the first external interconnect on a top encapsulation side of the outer encapsulation and the second external interconnect on a bottom encapsulation side of the outer encapsulation.

Abstract: The present invention relates to affixing components of optical packages. The optical packages can include an optical component, such as a TO-Can. The TO-Can can house an optical transmitter and/or an optical receiver. Another optical component of the optical package can be a barrel for aligning the TO-Can with an optical fiber. The TO-Can can be affixed within an open end of the optical barrel using a bonding substance, such as an epoxy, that has wicking properties. The wicking properties cause the bonding substance to enter a gap between the optical barrel and the TO-Can by capillary action. Use of the bonding substance with wicking properties creates a more robust optical package in a cost effective manner.

Abstract: A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through-chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at least one of the at least two chips and at least partially into another of the at least two chips so as to form a tube extending between the one and the other of the chips, and an amount of working fluid hermetically sealed within the tube, the working fluid having a volume and being at a pressure such that the working fluid and tube will operate as a heat pipe and transfer heat from the stack of chips to the working fluid.

Abstract: The aim the disclosed process is to ensure maximum precision both at the level of the manufacturing of an electronic assembly from a chip with small dimensions as well as the level of the placement of such an assembly on an insulating substrate. This aim is achieved by a placement process on a support, called substrate, of at least one electronic assembly consisting of a chip including at least one electric contact on one of its faces, said contact being connected to a segment of conductive track, and said placement being carried out by means of a placement device holding and positioning said assembly on the substrate, comprising the following steps: formation of a segment of conductive track having a predetermined outline, transfer of the track segment onto the placement device, seizing of the chip with the placement device carrying the track segment in such a way that said track segment is placed on at least one contact of the chip.

Abstract: To provide a method for manufacturing a highly-reliable semiconductor device, which is not damaged by external local pressure, with a high yield, a semiconductor device is manufactured by forming an element substrate having a semiconductor element formed using a single-crystal semiconductor substrate or an SOI substrate, providing the element substrate with a fibrous body formed from an organic compound or an inorganic compound, applying a composition containing an organic resin to the element substrate and the fibrous body so that the fibrous body is impregnated with the organic resin, and heating to provide the element substrate with a sealing layer in which the fibrous body formed from an organic compound or an inorganic compound is contained.

Abstract: A structure fabrication method. The method includes providing a structure. The structure includes (a) a substrate layer, (b) a first fuse electrode in the substrate layer, and (c) a fuse dielectric layer on the substrate layer and the first fuse electrode. The method further includes (i) forming an opening in the fuse dielectric layer such that the first fuse electrode is exposed to a surrounding ambient through the opening, (ii) forming a fuse region on side walls and bottom walls of the opening such that the fuse region is electrically coupled to the first fuse electrode, and (iii) after said forming the fuse region, filling the opening with a dielectric material.

Abstract: The present invention provides a manufacturing method for forming an integrated circuit device and to a corresponding integrated circuit device. The manufacturing method for forming an integrated circuit device comprises the steps of: forming a first level on a substrate; forming a second level above the first level; forming a cap layer on the second level which covers a first region of the level and leaves a second region uncovered; and simultaneously etching a first contact hole in the first region and a second contact hole in the second region such that the etching is selective to the cap layer in the second region and proceeds to a greater depth in the first region.

Abstract: The present invention relates to a method for repairing a semiconductor device. The method includes cutting a fuse without creation of residue by transforming the fuse into a nonconductor of high resistance by oxidizing the fuse by irradiating the fuse with an oxygen ion beam instead of a laser in a blowing process. The method includes transforming a fuse corresponding to a defective cell among a plurality of fuses formed in an upper portion of a semiconductor substrate into an oxide film.

Abstract: An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current.

Abstract: A step of forming a through hole in a semiconductor substrate, or a step of polishing the semiconductor substrate from its back surface requires a very long time and causes decrease of productivity. In addition, when semiconductor substrates are stacked, a semiconductor integrated circuit which is formed of the stack is thick and has poor mechanical flexibility. A release layer is formed over each of a plurality of substrates, layers each having a semiconductor element and an opening for forming a through wiring are formed over each of the release layers. Then, layers each having the semiconductor element are peeled off from the substrates, and then overlapped and stacked, a conductive layer is formed in the opening, and the through wiring is formed; thus, a semiconductor integrated circuit is formed.

Abstract: A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.

Abstract: A four-mask process thin film transistor (TFT) array substrate and a method for fabricating the same is disclosed, which prevents a semiconductor tail from being formed. An open area is thus obtained and wavy noise is prevented from occurring.

Abstract: A method for fabricating a thin film transistor (TFT) is provided. A substrate having a gate, a dielectric layer, a channel layer and an ohmic contact layer formed thereon is provided. Next, a metal layer is formed over the substrate covering the ohmic contact layer. Next, the metal layer and the ohmic contact layer are simultaneously etched by a wet etching process to form a source/drain and expose the channel layer. Because the wet etching process can be used to selectively etch the ohmic contact layer, damage to the underlying channel layer may be negligible. Thus, the reliability of the device may be promoted. Furthermore, the process may be simplified, the production yield and the throughput of TFT may be increased.

Abstract: An active matrix organic EL display device includes pixels each having an organic EL element (7a) and a pixel circuit (3) including a polysilicon TFT for controlling the organic EL element (7a) arranged adjacently in each of the regions partitioned into a matrix shape by data line (12) and gate line (11) that intersect each other. The organic EL element (7a) has a cathode (7) arranged in at least a region that excludes a space above the polysilicon TFT. The cathode (7) is arranged continuously over two or more adjacent pixels in the direction of gate line (11).

Abstract: Method for providing a transistor that includes the steps of providing a silicon on insulator layer, providing a silicon oxide insulation layer, providing a dielectric layer, removing at least a portion of the silicon oxide insulation layer and the dielectric layer to form a gate stack, and forming a gate electrode. The gate electrode covers a portion of the gate stack.

Abstract: A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.

Abstract: A method for fabricating a PMOS transistor is disclosed herein. In one embodiment, the method can include forming a gate insulation layer and a polysilicon layer over a semiconductor substrate; asymmetrically etching the polysilicon layer; doping the asymmetrically etched polysilicon layer with a P-type dopant; diffusing the dopant in the asymmetrically etched polysilicon layer towards the semiconductor substrate; planarizing the asymmetrically etched polysilicon layer; forming a gate metal layer over the planarized polysilicon layer; forming a hard mask, which delimits a region to be formed with a gate of the PMOS transistor, over the gate metal layer; forming a gate stack by patterning the gate metal layer, the planarized polysilicon layer, and the gate insulation layer; and forming a source/drain in the semiconductor substrate at both sides of the gate stack.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: In order to manufacture a highly reliable and compact TFT, it is an object of the present invention to provide a method for manufacturing a semiconductor device for forming a gate electrode, a source wiring and a drain wiring with high reliability, and a semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film is formed over a substrate having an insulated surface, a gate insulating film is formed over the semiconductor film, a gate electrode is formed over the gate insulating film, and a nitride film is formed over the surface of the gate electrode by nitriding the surface of the gate electrode by using high-density plasma.

Abstract: The present invention provides a thin film transistor having excellent formability and processability, and particularly a thin film transistor using plastics as a substrate; an organic semiconductor as an active layer; and SiO2 thin films formed by coating as a sealing layer and a gate insulating layer, and a process for producing the same. The present invention provides a field-effect type thin film transistor having an active layer of an organic semiconductor, comprising on a plastic substrate, a sealing layer of a SiO2 thin film formed by coating; a gate electrode; a gate insulating layer of a SiO2 thin film formed by coating; gate and drain electrodes; and a semiconductor active layer. The high-quality SiO2 thin film is obtained by using a silicon compound as a starting material and irradiating a coated thin film of the solution of the starting material with light in an oxygen atmosphere.

Abstract: A composite dielectric layer including a nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The need to form and remove two separate dielectric material layers is obviated. The nitride layer protects the oxide layer to alleviate oxide damage during a pre-silicidation PAI (pre-amorphization implant) process thereby preventing oxide attack during a subsequent HF dip operation and preventing nickel silicide spiking through the attacked oxide layer during silicidation.

Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

Abstract: Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

Abstract: Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.

Abstract: A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.

Abstract: A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21a) in the cell array region, gate oxide film (21b) for a high-voltage circuit and gate oxide film (21c) for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film (22). After that, device isolation grooves (13) are formed and buried with a device isolation insulating film (14). The first-layer polycrystalline silicon film (24) is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film (24) is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film (22) and the second-layer polycrystalline silicon film (24).

Abstract: A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater than the first ratio. A first device having a first polarity uses the first mesa as a channel and benefits from the enhanced vertical crystallographic orientation. A second device having a second polarity different from the first polarity uses the second mesa as a channel and benefits from the enhanced horizontal crystallographic orientation.

Abstract: By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

Abstract: A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern.

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.

Abstract: A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.

Abstract: A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions.

Abstract: A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.

Abstract: A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment.