Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

Abstract: A method of manufacturing a semiconductor wafer having at least one device trench extending to a first depth position includes providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer having first and second main surfaces disposed on the first main surface of the semiconductor substrate and determining an etch ratio. The least one device trench and at least one monitor trench are simultaneously formed in the first main surface of the semiconductor material layer. The at least one monitor trench is monitored to detect when it extends to a second depth position. A ratio of the first depth position to the second depth position is generally equal to the etch ratio.

Abstract: Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating structure. A transistor is positioned in each of the plurality of semiconductor regions. Each of the transistors includes a gate that has a first lateral dimension and an end that has a position relative to its border. A voltage source is electrically coupled to the transistors whereby levels of currents flowing through the transistors are indicative of the positions of the ends of the gates relative to their borders.

Abstract: In a method and structure for current balancing the emitter current in a multi-finger n-emitter of a BJT or BSCR, back-end or polysilicon resistors are applied between the emitter fingers and the power rail, with the resistors chosen to be larger the closer the emitter fingers are to the collector.

Abstract: A method of measuring a film thickness is disclosed. The method includes a step of forming a ferroelectric capacitor on a substrate, a step of forming an insulating film to cover the ferroelectric capacitor, and a step of optically measuring the thickness of the insulating film on an electrode of the ferroelectric capacitor.

Abstract: Light-emitting devices, light-emitting apparatuses, image display apparatuses and methods of manufacturing same are provided. The devices and apparatuses include a transparent electrode that is connected directly to light output surfaces so as to cover the whole areas of the light output surfaces. The transparent electrode is formed to be larger in area than the light output surfaces, and are securely electrically connected to n-type semiconductor layers including the light output surfaces.

Abstract: A nitride-based light emitting device is manufactured by using a single-crystal nitride-based semiconductor substrate. A seed material layer is deposited on a first substrate where organic residues including a natural oxide layer are removed from an upper surface of the first substrate. A multifunctional substrate is grown from the seed material layer. The single-crystal nitride-based semiconductor layer including a nitride-based buffer layer is formed on the multifunctional substrate. The seed material layer primarily assists the growth of the multifunctional substrate, which is essentially required for the growth of the single-crystal nitride-based semiconductor substrate. The multifunctional substrate is prepared in the form of a single-crystal layer or a poly-crystal layer having a hexagonal crystalline structure.

Abstract: An LED assembly includes a heat sink and a submount. The heat sink has a top mating surface that is solder wettable, and the submount has a bottom mating surface that is solder wettable. The top and the bottom mating surfaces have substantially the same shape and area. The submount is soldered atop the heat sink. During solder reflow, the molten solder causes the submount to align with the top mating surface of the heat sink. The LED assembly may further include a substrate having a top mating surface, and the heat sink may further include a bottom mating surface. The top and bottom mating surfaces have substantially the same shape and area. The heat sink is soldered atop the substrate. During solder reflow, the molten solder causes the heat sink to align with the top mating surface of the substrate.

Abstract: A chip coated LED package and a manufacturing method thereof. The chip coated LED package includes a light emitting chip composed of a chip die-attached on a submount and a resin layer uniformly covering an outer surface of the chip die. The chip coated LED package also includes an electrode part electrically connected by metal wires with at least one bump ball exposed through an upper surface of the resin layer. The chip coated LED package further includes a package body having the electrode part and the light emitting chip mounted thereon. The invention improves light efficiency by preventing difference in color temperature according to irradiation angles, increases a yield, miniaturizes the package, and accommodates mass production.

Abstract: A method for producing a light-emitting device comprising: a step of electrically connecting a first electrode provided on one main surface of a semiconductor substrate (element substrate) through a light-emitting layer, and a first lead of a lead frame, so as to oppose each other; a step of electrically connecting a second electrode provided on the rear surface of a surface provided with the light-emitting layer of said element substrate, and a second lead of the above-described lead frame; a step of encapsulating a connecting part of said first electrode and said first lead, and said second electrode, and an electrode part of the second lead, with a transparent resin; and a step of producing a discrete edge by cutting said first lead and the second lead from said lead frame; wherein a film of joining material (joining material film) made of an alloy or a single metal, is formed on the first electrode of said light-emitting element, and a pattern to reduce spreading of said joining material is formed on an e

Abstract: A method of manufacturing a vertical structure light emitting diode device, the method including: sequentially forming a first conductivity type III-V group compound semiconductor layer, an active layer, and a second conductivity type III-V group compound semiconductor layer on a substrate for growth; bonding a conductive substrate to the second conductivity type III-V group compound semiconductor layer; removing the substrate for growth from the first conductivity type III-V group compound semiconductor layer; and forming an electrode on an exposed portion of the first conductive III-V group compound semiconductor layer due to the removing the substrate for growth, wherein the bonding a conductive substrate comprises partially heating a metal bonding layer by applying microwaves to a bonding interface while bringing the metal bonding layer into contact with the bonding interface.

Abstract: There is provided a method of manufacturing a light emitting diode chip, the method including: providing a light emitting diode chip; forming a phosphor layer on a top of the light emitting diode chip; and forming phosphors of a lattice structure on the phosphor layer by an inkjet process using an ink containing phosphor powder. There is also provided A method of manufacturing a light emitting diode package, the method including: forming a phosphor layer with a predetermined thickness; forming phosphors of a lattice structure on the phosphor layer by an ink jet process using an ink containing phosphor powder; and disposing the phosphor layer having the phosphors of the lattice structure formed thereon on a top of the light emitting diode chip.

Abstract: A method of fabricating a semiconductor device is provided. First, a first electrode is formed over a first region of a substrate. Then, a dielectric layer covering the first electrode is formed over the substrate. After that, a plurality of openings is formed on the first region of the substrate. Thereafter, a conductive layer covering the dielectric layer and the openings is formed over the substrate. Then, the conductive layer in the bottom of the openings is removed to form second electrodes. After that, the dielectric layer between the second electrode and the first electrode is removed.

Abstract: A liquid crystal display (LCD) device and its fabrication method includes providing a substrate divided into pixel part and pad parts; forming a gate electrode and a gate line at the pixel part through a first masking process; forming a first insulation film; forming an active pattern and source and drain electrodes at an upper portion of the gate electrode of the pixel part and forming a data line substantially crossing the gate line to define a pixel region through a second masking process; forming a pixel electrode directly electrically connected with the drain electrode at the pixel region of the pixel part through a third masking process; and attaching first and second substrates. A pixel electrode is formed to directly electrically connect with a drain electrode by selectively etching a transparent conductive film without forming a contact hole.

Abstract: The present invention provides an optical element which can reliably acquire a difference of refractive indices between a member under a photonic crystal layer and the crystal layer without using such a stacking technique as in conventional processes; a method for manufacturing the optical element; and a semiconductor laser device with the use of the optical element. The optical element has the first layer 500 and the second layer 400 formed on a substrate 100, wherein the second layer includes pores and has a refractive-index periodically changing structure in which a refractive index periodically changes in an in-plane direction; and the first layer has an oxidized region with a lower refractive index than the refractive index of the second layer, in a lower side of the pores of the second layer.

Abstract: A semiconductor light-emitting element has a laminated section which has an active layer made of a semiconductor, and first and second clad layers each being disposed to sandwich the active layer and made of a semiconductor, a pair of first high-reflection layers each being disposed to sandwich the active layer in a first direction orthogonal to the laminated direction of the laminated section, and a low-reflection layer and a second high-reflection layer each being disposed to sandwich the active layer in a second direction orthogonal to the laminated direction and crossing to the first direction.

Abstract: Aimed at stably forming sheared surfaces of leads of semiconductor devices, and at raising ratio of formation of plated layers onto the sheared surfaces of the leads, a lead cutter has a die 106, and a cutting punch 110 having a cutting edge at least on the surface facing the die, wherein clearance T between the die 106 and the cutting punch 110 is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of the leads to be cut and plated layers formed on the upper and the lower surfaces thereof.

Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.

Abstract: This invention provides a method of forming at least one pressure switch thin film device. The method includes providing a substrate and depositing a plurality of thin film device layers as a stack upon the substrate. An imprinted 3D template structure is provided upon the plurality of thin film device layers. The plurality of thin film device layers and the 3D template structure are then etched and at least one thin film device layer is undercut to provide a plurality of aligned electrical contact pairs and adjacent spacer posts. A flexible membrane providing a plurality of separate electrical contacts is deposited upon the spacer posts, the separate electrical contacts overlapping the contact pairs. The spacer posts provide a gap between the electrical contacts and the contact pairs.

Abstract: A micro-electro-mechanical systems (MEMS) device includes a back-plate substrate, having an intended region formed with a plurality of perforating holes. A first structural dielectric layer, disposed on the back-plate substrate, wherein the dielectric layer having an opening above the intended region. An etching stop layer, disposed over the first structural dielectric layer. A second structural dielectric layer, formed over the back-plate substrate. The etching stop layer and the second structural dielectric layer form at least a part of a micro-machine diaphragm, and cover over the opening of the first structural dielectric layer to form a chamber between the micro-machine diaphragm and the back-plate substrate.

Abstract: The present invention provides a front-illuminated avalanche photodiode (APD) with improved intrinsic responsivity, as well as a method of fabricating such a front-illuminated APD. The front-illuminated APD comprises an APD body of semiconductor material, which includes a substrate and a layer stack disposed on a front surface of the substrate. The layer stack includes an absorption layer, a multiplication layer, and a field-control layer. Advantageously, a back surface of the APD body is mechanically and chemically polished, and a reflector having a reflectance of greater than 90% at the absorption wavelength band is disposed on the back surface of the APD body. Thus, incident light that is not absorbed in a first pass through the absorption layer is reflected by the reflector for a second pass through the absorption layer, increasing the intrinsic responsivity of the front-illuminated APD.

Abstract: Provided is an image sensor. The image sensor can include a first substrate comprising a pixel portion in which a readout circuitry is provided and a peripheral portion in which a peripheral circuitry is provided. An interlayer dielectric including lines can be formed on the first substrate to connect with the readout circuitry and the peripheral circuitry. A crystalline semiconductor layer can be provided on a portion of the interlayer dielectric corresponding to the pixel portion through a bonding process. The crystalline semiconductor layer can include a first photodiode and second photodiode. The first and second photodiodes can be defined by device isolation trenches in the crystalline semiconductor layer. A device isolation layer can be formed on the crystalline semiconductor layer comprising the device isolation trenches. An upper electrode layer passes through the device isolation layer to connect with a portion of the first photodiode.

Abstract: A method for making lens modules includes the steps of: a) providing a wafer including an array of sensor chips; b) mounting a plurality of lens assemblies on the sensor chips, respectively, thereby defining a plurality of intersecting spacing grooves among the lens assemblies; c) forming substrate layer by filling in the spacing grooves with a resin material; and d) cutting the wafer and the substrate layer along intersecting cutting lines each extending along one of the spacing grooves and each intervening the lens assemblies, the substrate layer being divided into a plurality of barrels respectively surrounding the lens assemblies. A lens module made by the method is also disclosed.

Abstract: A method of manufacturing partially light transparent thin film solar cells generally includes forming a solar cell structure stack and forming multiple openings through the solar cell structure stack. The solar cell structure stack includes a flexible foil substrate, a contact layer formed over the flexible foil substrate, a Group IBIIIAVIA absorber layer formed over the contact layer and a transparent conductive layer formed over the Group IBIIIAVIA absorber layer. A terminal structure including at least one busbar and a plurality of conductive finger patterns is deposited onto a top surface of the transparent conductive layer forming a semi-transparent solar cell.

Abstract: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.

Abstract: An image sensor includes a lower metal interconnection, an interlayer dielectric, a first substrate, a photodiode, an upper electrode and an amorphous silicon layer. The lower metal interconnection and the interlayer dielectric are formed over the first substrate including a pixel region and a peripheral region. The photodiode is formed over the pixel region of the first substrate. The upper electrode layer is connected to the photodiode. The amorphous silicon layer is formed between the photodiode and the interlayer dielectric.

Abstract: Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a first semiconductor layer over a substrate, and forming a second semiconductor layer over the first semiconductor layer, wherein an amorphous nitrided silicon adhesion layer is located between and adheres the first and second semiconductor layers.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

Abstract: A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias.

Abstract: Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips.

Abstract: The invention provides a Wafer Level Chip Size Packaging (WLCSP) target and a method for forming it. A WLCSP target is formed by recombining single chips, wafer parts each including two or more chips or half finished packaging targets which have been subjected to at least one previous step of packaging onto a first substrate, or bonding a wafer part which is formed by dicing a whole wafer and includes at least two chips to a second substrate for bonding. Thus, a wafer with a larger size can be packaged through the WLCSP on a WLCSP apparatus with a smaller size while benefiting from the advantages of the WLCSP, the WLCSP apparatus remains applicable within a longer period of time, the cost is lowered, and enterprises may keep up with the development of the market and the increase of the wafer size without having to update the WLCSP apparatus substantially.

Abstract: In a flip shop mounting method by no-flow underfill in which resin 54 is pre-coated on a substrate 52, and a semiconductor 50 with bump is mounted on the substrate 52 to join a pad electrode 53 on the substrate 52 to the bump 51, the substrate 52 is placed on an upper surface of a base 11 of a reflow jig 10, the resin 54 highly filled with filler 55 is applied onto the substrate 52, the semiconductor 50 with bump is mounted at a predetermined position over the substrate 52, a press plate 21 is placed on an upper portion of the semiconductor 50, a spacer 13 is interposed between a lower surface of the press plate 21 and an upper surface of the base 11 to regulate an amount of press force of the press plate 21, and horizontal movement of the press plate 21 is regulated by positioning guide pins 15 on the upper surface of the base 11.

Abstract: A method, system, and apparatus for transfer of dies using a die plate having die cavities is described herein. The die plate has a planar body. The body has a plurality of cells or cavities which are open at the first surface of the body. Each cell has a hole extending from the bottom surface of the cell to a second surface of the body. A wafer or support structure can be positioned to be closely adjacent to each other. A suction can be applied to the second surface of the die plate so that a plurality of dies can be transferred into a plurality of cells of the die plate. The dies can subsequently be transferred from the die plate having die cavities to one or more destination substrates or surfaces, by a punching mechanism.

Abstract: A memory card and method for fabricating the same are disclosed, which includes mounting and electrically connecting at least a chip to a circuit board unit having a predefined shape of a memory card; attaching a thin film to the surface of the circuit board unit opposed to the surface with the chip mounted thereon; covering the circuit board unit and the thin film by a mold so as to form a mold cavity having same shape as the circuit board unit but bigger size; filling a packaging material in the mold cavity so as to form an encapsulant encapsulating the chip and outer sides of the circuit board unit, thus integrally forming a memory card having the predefined shape. The present invention eliminates the need to perform a shape cutting process by using water jet or laser as in the prior art, thus reducing the fabricating cost and improving the fabricating yield.

Abstract: A cavity semiconductor package has a pre-molded leadframe construction. The leadframe is formed by molding around a die pad, and plural terminal lands. The leadframe has a hole for an acoustic port, such that the package can be soldered on a back side of a printed circuit board and have air access to a sensor die in the package from a front side of the printed circuit board via the acoustic port. The leadframe may also have a hollow or concave recess that defines an acoustic cavity in conjunction with the sensor die or printed circuit board.

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the conductive layer. The chips are electrically connected to the conductive layer by a plurality of bonding wires. At least one molding compound is formed to encapsulate the conductive layer, the patterned solder resist layer, the chips and the bonding wires. A part of the conductive layer exposed by the patterned solder resist layer is removed so as to form a patterned conductive layer. Then, the molding compound and the patterned conductive layer are separated.

Abstract: Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size are possible. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.

Abstract: A method for manufacturing a thin film transistor (TFT) is disclosed. The method is achieved by forming and defining a source and a drain of a thin film transistor through two lithographic processes cycles so that the channel length (L) of the thin film transistor can be reduced to 1.5 to 4.0 ?m. Besides, the Ion current of the thin film transistor is increased as the channel length (L) is decreased. Therefore, the component area of the thin film transistor is decreased as the channel width (W) is decreased. Thus, the aperture ratio of the TFT-LCD can be increased due to the decreased component area of the thin film transistor.

Abstract: A method of fabricating a CMOS thin film transistor includes: providing a substrate; forming an amorphous silicon layer on the substrate; performing a first annealing process on the substrate and crystallizing the amorphous silicon layer into a polysilicon layer; patterning the polysilicon layer to form first and second semiconductor layers; implanting first impurities into the first and second semiconductor layers; implanting second impurities into the first or second semiconductor layer; and performing a second annealing process on the semiconductor layers to remove the metal catalyst remaining in the first or second semiconductor layer, on which the second impurities are implanted, wherein the first impurities are implanted at a dose of 6×1013/cm2 to 5×1015/cm2, and the second impurities are implanted at a dose of 1×1011/cm2 to 3×1015/cm2.

Abstract: The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type substrate by a doping process using a mask. The second type bar doped regions are diffused to form a second type continuous region by annealing. The second type continuous region is adjoined with the first type well regions. A second type dopant concentration of the second type continuous region is smaller than a second type dopant concentration of the second type bar doped regions. A second type source/drain region is formed in the second type well region.

Abstract: Semiconductor devices and a fabricating method therefore are disclosed.

Abstract: Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.

Abstract: A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a first metal layer that is in contact with the first silicon pattern and the exposed first portion of the silicon substrate; and forming a first gate, a first junction, a second gate, and a second junction by performing a heat treatment to silicify the respective first and second silicon patterns and the silicon substrate.

Abstract: A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.

Abstract: A method for manufacturing memory cells is provided. First, a substrate is provided, wherein a liner layer and a material layer have already been sequentially formed on the substrate. Thereafter, a patterned mask layer is formed on the substrate. Then, the patterned mask layer is trimmed. Subsequently, a portion of the material layer, a portion of the liner layer and a portion of the substrate are removed by using the patterned mask layer as a mask to define a plurality of fin-structures in the substrate. Afterward, the patterned mask layer is removed and a plurality of isolation structures among the fin structures is formed. The surface of the isolation structures is lower than that of the fin structures. Following that, charge trapping structures are formed on the substrate, covering the fin structures. Succeeding, a portion of the charge trapping structures is removed to expose the material layer. Then, the treatment process turns the material layer into a protection layer.

Abstract: A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.

Abstract: A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

Abstract: A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons, the first work function is greater than the second work function. When the majority carriers of the split-gate memory device are holes, the first work function is less than the second work function. First and second current electrodes in the substrate are separated by a channel that underlies the control gate and select gate. The differing work functions of the control gate and the select gate result in differing threshold voltages for each gate to optimize device performance. For an N-channel device, the select gate is P conductivity and the control gate is N conductivity.

Abstract: A semiconductor memory device includes gate electrodes extending in a first direction above a surface of a substrate. The semiconductor memory device also includes a reinforcement insulation film formed in a line shape and extending in a second direction crossing the gate electrodes in a plane view viewed from above the surface of the substrate, and connected to adjacent gate electrodes. Further, the semiconductor memory device includes an interlayer dielectric film provided between the adjacent gate electrodes, and having a void inside.

Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.