Abstract: A tower includes a base configured to sit upon a surface. A light source is coupled to the base and is positioned a first horizontal distance from a center of the base. The light source is configured to produce light therefrom when energized. The tower includes a cylindrical outer body that is coupled to and positioned a second distance from the center of the base, wherein the second distance is greater than the first distance. The outer body is oriented to extend vertically from the surface and is configured to allow light from the light source to pass therethrough. A plurality of leaves are coupled to an outer surface of the outer body and are configured to hang therefrom. The leaves are configured to freely move with respect to the outer body when air flow is applied thereto, wherein light from the light source is viewable through the outer body when the leaves move.

Abstract: A light-emitting device pressure ring structure includes a mounting base for mounting, a circuit board accommodated in the mounting base and having electrode pins connectable to an external power source, a holder member insertable in the mounting base, a light-emitting unit fixedly mounted in the holder member with a bottom heat sink thereof suspending outside the holder member and tubular electrodes thereof connectable to the electrode pins of the circuit board for power input, and a pressure ring cap detachably threaded onto the mounting base to hold down the holder member and to keep the heat sink of the light-emitting unit outside the mounting base for quick dissipation of waste heat from the light-emitting devices of the light-emitting unit.

Abstract: A divided LED lamp includes an LED assembly, a casing assembly, LED electronics, power and signal cables, a control panel including a display screen and operation buttons, and a bracket for mounting the lamp. The casing assembly includes a first casing member and a second casing member. At least one cable tube is formed between the first casing member and the second casing member. The power and signal cables that connect the LED assembly received in the first casing member and the LED electronics received in the second casing member are received through the cable tube. This arrangement allows the LED assembly and the LED electronics to be received in individual and independent casing members and are associated with respective individual heat dissipation fins or heat radiators, so as to realize high efficiency of heat dissipation, stabilized operation, and extended lifespan.

Abstract: A light projection apparatus that projects light onto an arbitrary space and an object set in the space, comprising: projection light data generating means for generating projection light data for specifying the projection light; projection range setting means for setting a projection range onto which the light is projected and a non-projection range onto which the light is not projected in accordance with an operation of a user; projection data correcting means for correcting the projection light data so as to project the light onto the projection range set by the projection range setting means; projection light correction data drawing means for performing drawing processing for projection light correction data obtained by correcting the projection light data by the projection data correcting means; and light projecting means for projecting the light by using projection light drawing data generated by the projection light data drawing means.

Abstract: The lighting assembly (20) includes a light guide (22) formed of a resin material propagating light through internal reflection. A housing (28) surrounds the light guide (22) and maintains the light guide (22) in a predetermined position. A light transmissive coating (24), such as a vacuum metalized coating, is disposed on the light guide (22) and faces outwardly of the housing (28). The light transmissive coating (24) disguises the resin light guide (22) so that the light guide (22) appears to be a metallic trim. A non-light transmissive coating (26), such as a paint, appearing to be the same material as the light transmissive coating (24), may be disposed on the light guide (22) adjacent the light transmissive coating (24).

Abstract: The invention relates to a motor vehicle lighting fixture which comprises at least: a light source comprising at least one LED; a light-transmitting part that is arranged such that it receives light from the light source; and a reflector that is arranged such that it reflects that portion of the light from the light source that passes through the light-transmitting part and couples it out to the front of the lighting fixture, a reflection portion and a refraction portion being provided within the light-transmitting part, wherein said reflection portion deflects the light issuing from the light source through total reflection in one direction that is substantially perpendicular to the optical axis of the reflector, whereas the refraction portion couples out the light in the direction of the reflector.

Abstract: A light source apparatus for vehicle lamps and particularly vehicle headlights can include a plurality of LED elements can be mounted in a cavity located on a base surface or on a base. Each of the LED elements can be arranged in such a manner as to form an emission shape and a brightness distribution that is suited for a light distribution pattern, and especially a light distribution pattern for a vehicle headlight.

Abstract: A light emitting module includes: a semiconductor light emitting element; a plate-shaped light wavelength conversion ceramic that is provided so as to face the light emitting surface of the semiconductor light emitting element and that is configured to convert the wavelength of the light, which has been emitted by the semiconductor light emitting element; and a reflective film that is formed on the surface of the light wavelength conversion ceramic and that is configured to shield part of the light, which has been transmitted through the light wavelength conversion ceramic. The light wavelength conversion ceramic is composed on an inorganic material.

Abstract: A heat dissipation device of a vehicle lamp and an interposing element thereof are provided. The heat dissipation device is installed in a lamp room which is divided by the interposing element into a front partition and a rear partition. A heat sink is installed in the interposing elements. An air feeding fan is disposed in an air feeding channel of the interposing element, for drawing air in the front partition to the rear partition through the air feeding channel. Further, a back flow fan is disposed in the rear partition, for drawing air in the rear partition to the front partition through a back flow channel. Whereby, the air in the front partition is cooled down through an external air flow passing through the lamp cover. Then, the heat sink dissipates heat of the air flow with the relatively low temperature in the front partition to the rear partition.

Abstract: A tip for a mobility device which is capable of providing light and/or sound to aid in the safety of the user of the mobility device.

Abstract: The invention relates to an illumination system (10, 20, 30) for illuminating a display device (40) and to a display device (40). The illumination system comprises a light-mixing chamber (50) which comprises a light-exit window (52), a rear wall (54) which is situated opposite the light-exit window (52), and edge walls (56, 58) which extend between the light-exit window (52) and the rear wall (54). A surface (55) of the rear wall (54) is substantially specularly reflective for specularly reflecting light impinging on the surface of the rear wall and having a relatively large angle of incidence with respect to an axis perpendicular to the rear wall. The illumination system further comprises a light source (60, 62) and a plurality of light out-coupling elements (70). The light source emits light into the light-mixing chamber in a direction substantially parallel to the light-exit window. The illumination system further comprises an angularly reflective filter (80) applied at the light-exit window.

Abstract: The present invention introduces a new class of thin doubly collimating light distributing engines for use in a variety of general lighting applications, especially those benefiting from thinness. Output illumination from these slim-profile illumination systems whether square, rectangular or circular in physical aperture shape is directional, square, rectangular or circular in beam cross-section, and spatially uniform and sharply cutoff outside the system's adjustable far-field angular cone. Field coverage extends from +/?5- to +/?60-degrees and more in each meridian, including all asymmetric combinations in between, both by internal design, by addition of angle spreading film sheets, and angular tilts. Engine brightness is held to safe levels by expanding the size of the engine's output-aperture without sacrifice in the directionality of illumination. One form of the present invention has a single input light emitter, a square output aperture and the capacity to supply hundreds of lumens per engine.

Abstract: A light emitting diode package may be provided that includes a light emitting diode chip and a heat sink. Heat generated from the light emitting diode chip may be radiated to the outside using the heat sink.

Abstract: An LED includes a light-emitting chip, a metal member, and a housing. The light-emitting chip generates light. The light-emitting chip is arranged on the metal member. The housing is combined with the metal member to fix the metal member. The housing has an opening portion exposing at least a portion of the light-emitting chip and the metal member. The metal member includes a base metal layer, a light-reflecting layer arranged on the base metal layer, and a protection layer arranged on the light-reflecting layer and including a metal.

Abstract: A brightness enhancing reflector to accurately control the light exiting the guide achieves accurate control of the reflected light by extracting light from a limited area of the light guide. The configuration of the reflectors used for the selective extraction determines the nature of the output light. The reflectors are preferably located on a side of the light guide opposite to an output side of the light guide and in conjunction with an electronic display.

Abstract: A method for operating a switching power supply is provided. A switching element is switched on and off by a switching signal with a variable switching frequency. A frequency bandwidth is predefined for determining average levels of a frequency spectrum of the switching signal. The switching frequency is modulated by a modulation frequency greater than a frequency bandwidth.

Abstract: In one embodiment, a method of operating a switched-mode power supply that has a switch coupled to a drive signal is disclosed. The method includes deactivating the drive signal at a first instance of time, and comparing a power supply signal to a threshold after deactivating the drive signal. The method further includes activating the drive signal a variable period of time after the power supply signal crosses the threshold.

Abstract: An energy recovery snubber circuit for use in switching power converters. The power converters may include a switch network coupled to a primary winding of an isolation transformer, and rectification circuitry coupled to a secondary winding of the isolation transformer. The energy recovery snubber circuit may include clamping circuitry that is operative to clamp voltage spikes and/or ringing at the rectification circuitry. The clamped voltages may be captured by an energy capture module, such as a capacitor. Further, the energy recovery snubber circuitry may include control circuitry operative to return the energy captured by the energy capture module to the input of the power converter. To maintain electrical isolation between a primary side and a secondary side of the isolation transformer, a second isolation transformer may be provided to return the captured energy back to the input of the power converter.

Abstract: One embodiment of the invention relates to a power apparatus. The power apparatus includes a power converter configured to convert an input voltage to an output voltage for providing power at an output thereof to which a load is connectable. The converter can include an isolation barrier configured to electrically isolate the output and the load from an input source that provides the input voltage. The system also includes a control loop that includes indirect sense circuitry configured to indirectly derive an indication of at least one of output current and output power of the converter. The control loop is configured to control output current or output power based on the indirectly derived indication of output current or output power, respectively.

Abstract: A switching power supply apparatus includes: a turn-on control circuit which generates a turn-on signal; a feedback control circuit which generates a reference voltage VEAO indicating a limitation level for a current ID flowing into a switching element, by referring to a feedback signal IFB indicating an output current voltage VOUT, the limitation level which decreases as the output direct current voltage becomes greater; an overcurrent protection level setting circuit which generates a reference voltage VLR indicating an overcurrent protection level; a current detecting terminal; an offset current generating circuit which provides an offset current IIS from the current detecting terminal, the offset current IIS which is greater as the output current voltage VOUT is greater; and a turn-off control circuit which generates a turn-off signal by comparing a voltage applied to the current detecting terminal with each of the reference voltage VEAO, and the reference voltage VLR.

Abstract: A drive circuit of first and second switches includes a first series circuit having a capacitor and a primary winding of a transformer and connected to both ends of a pulse signal generator, a first secondary winding of the transformer to apply a voltage to a control terminal of the first semiconductor switch based on the pulse signal, the first secondary winding being wound in a direction opposite to the primary winding, a second secondary winding of the transformer to apply a voltage to a control terminal of the second semiconductor switch based on the pulse signal, the second secondary winding being wound in the same direction to the primary winding, and a third semiconductor switch that turns on when the pulse signal is stopped, to shorten an ON period of the first semiconductor switch.

Abstract: Disclosed are methods of detection for output short circuit of a flyback power supply, which detect the current sense signal provided by a current sense resistor serially connected to a power switch of the flyback power supply, and thus quickly identify whether or not the flyback power supply suffers output short circuit.

Abstract: A method of operating a DC-DC converter according to the current mode control is provided. A current measuring signal for determining a turn-off time of a converter switching element is supplied to a PWM controller and a voltage that is proportional to the current measuring signal is compared by a comparator to a reference voltage. When the reference voltage is exceeded, the converter switching element is turned off.

Abstract: A power source circuit includes a DC voltage generating section which rectifies and smoothes an input AC voltage to generate a DC voltage; a switching regulator which converts the DC voltage into an AC voltage; a transformer which lowers the AC voltage; a first switch connected between a secondary winding of the transformer, and a load; and a control section which controls on/off of the switch. The control section controls the first switch to turn off the first switch at a time of a waiting mode.

Abstract: A switching power supply includes an energy-storing device, a power switch, a driving circuit and a thermal sensing device. The energy-storing device is coupled to an input power source and controlled by the power switch to increase or decrease the power therein. The power switch has a control terminal connected to the driving circuit for switching. The thermal sensing device is connected to the control terminal of the power switch and powered by the driving circuit. When sensing an operation temperature exceeding a predetermined range, the thermal sensing device disables the driving circuit.

Abstract: Provided herein are circuits, systems and methods that monitor for a fault within a multi-phase DC-DC converter. This can include monitoring the channels of the DC-DC converter for way out of balance (WOB) conditions, and monitoring for a component fault in dependence on detected WOB conditions. A fault can be detected if, during a predetermined period of time, one of the WOB conditions occurs at least a specified amount of times more than another one of the WOB conditions. The DC-DC converter and/or another circuit can be shut-down in response to a fault being detected. Additionally, or alternatively, a component fault detection signal can be output in response to a fault being detected.

Abstract: A time domain voltage step down capacitor based circuit has an oscillating circuit for generating a clock signal. The circuit also has a capacitor based charge pump circuit for receiving the clock signal and an input voltage signal having an input current and generates an output voltage signal, less than the input voltage signal and an output current greater than the input current. The circuit further comprises a comparator circuit for receiving the output voltage signal, as a first input signal thereto, and a reference voltage signal as a second input signal thereto and compares the first input signal to the second input signal and generates a control signal in response thereto.

Abstract: Systems and methods for operating an uninterruptable power supply are provided. The uninterruptable power supply may include a rectifier that has a transistor and an inductor. The uninterruptable power supply may also include a controller. A current sensor can be configured to detect inductor current and to provide a detected inductor current value to the controller to generate a current error value based and to generate a pulse width modulation control signal based in part on the current error value. The controller can apply the pulse width modulation control signal to the transistor to adjust a switching frequency of the transistor.

Abstract: A power inverter is provided for converting DC power into AC power. The inverter may be operable to couple to two or more transformer modules each operable to convert at least a portion of the DC power to at least a portion of the AC power. In one embodiment, two or more transformer modules are removably coupled to the inverter. In an alternative embodiment, the inverter is capable of electrically coupling to an externally-housed transformer module. In an alternative embodiment, the inverter may include two or more transformer modules hard-wired into the device. The inverter may include an AC safety plug for releasably connecting to an AC power network and outputting AC power. The inverter may include one or more sensors configured to detect one or more properties of the AC power network for the purposes of determining whether a connection to the power network should be established.

Abstract: A circuit arrangement (S) for supplying a load (P), whose essential electric property is capacitance, from a DC voltage source (U0) has a switch element (S1), which in the operational state is alternately switched between the conductive and non-conductive state, and at least one component (L1, L2) whose essential property is inductance, the load (P) being coupled into the circuit arrangement (S) in parallel to the component (L1, L2) so that the load (P) and the component (L1, L2) form a parallel resonant circuit, the switch element (S1) is connected between the parallel resonant circuit and a base voltage (GND) and the DC voltage source is to be applied in parallel (U0) to the load. The circuit arrangement (S) according to the invention can be used to drive the capacitive load (P) in a bipolar manner, the supply of the load in the non-conductive phase of the switch element (S1) being achieved by the component (L1, L2).

Abstract: A storage device including a memory and a reading circuit is disclosed. The memory includes a plurality of word lines, a first bit line, a second bit line, a third bit line, and a plurality of cells. The word lines are sequentially disposed in parallel. The first, the second, and the third bit lines are sequentially disposed in parallel and vertical with the word lines. Each cell corresponds to one word line and one bit line. The word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line. The read circuit is coupled to the memory for reading the data stored in the memory.

Abstract: In a semiconductor integrated circuit including a memory macro, such as a DRAM, an SRAM, a ROM, a flash memory, or the like, and a logic circuit, memory macro test-dedicated pads are provided on the memory macro, whereby an increase in the number of normal pads is reduced or prevented to reduce or prevent an increase in the chip area. Moreover, by fixing arrangement (positions) of the pads provided on the memory macro between memory macros of a plurality of memory macro-including semiconductor integrated circuits, a single common probe card for a single chip can be used for the memory macro-including semiconductor integrated circuits, thereby providing low-cost testing.

Abstract: A domain wall motion type MRAM has: a magnetic recording layer 10 having perpendicular magnetic anisotropy; and a pair of terminals 51 and 52 used for supplying a current to the magnetic recording layer 10. The magnetic recording layer 10 has: a first magnetization region 11 connected to one of the pair of terminals; a second magnetization region 12 connected to the other of the pair of terminals; and a magnetization switching region 13 connecting between the first magnetization region 11 and the second magnetization region 12 and having reversible magnetization. A first pinning site PS1, by which the domain wall is trapped, is formed at a boundary between the first magnetization region 11 and the magnetization switching region 13. A second pinning site PS2, by which the domain wall is trapped, is formed at a boundary between the second magnetization region 12 and the magnetization switching region 13.

Abstract: Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.

Abstract: In an embodiment, a read-only memory array includes a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of memory cells configured to represent data values. Each memory cell can include a transistor having a control terminal coupled to one of the plurality of word lines, a drain terminal, and a source terminal. Connections associated with the drain and source terminals of a particular memory cell can determine a data value represented by the memory cell. The memory cells of the plurality of memory cells that are coupled to less than two bit-lines are configured to represent one values.

Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.

Abstract: Disclosed is a memory architecture comprising at least one memory bit cell and at least one read bit line whose voltage is controlled and changed by a current from a current controller. Each memory bit cell has a storage mechanism, a controlled current source, and a read switch. The controlled current source in each memory bit cell is electrically connected to the read bit line through the read switch. The current from the current controller that controls and changes the read bit line voltage flows through the controlled current source in the memory bit cell. The value of this current is determined by a function of a difference between the voltage on the storage mechanism in the memory bit cell and a reference voltage from a reference voltage input to the current controller. In some versions an indicator is provided for indicating when to stop the current in the controlled current source that controls a voltage change on one of the read bit lines.

Abstract: An integrated circuit structure includes a first static random access memory (SRAM) cell including a first read-port and a first write-port; and a second SRAM cell including a second read-port and a second write-port. The first SRAM cell and the second SRAM cell are in a same row and arranged along a row direction. A first word-line is coupled to the first SRAM cell. A second word-line is coupled to the second SRAM cell. A read bit-line is coupled to the first SRAM cell and the second SRAM cell, wherein the read bit-line extends in a column direction perpendicular to the row direction. A write bit-line is coupled to the first SRAM cell and the second SRAM cell.

Abstract: An integrated circuit has a matrix of rows and columns of cells (10, 18, 19), each cell (10, 18, 19) comprising a first inverter (100) and a second inverter (102). First columns have a bit-line (12a,b), the first inverter (100) and the second inverter (102) in each cell of the first columns being cross-coupled to each other and coupled to bit-line (12a,b) of the associated first column. A further column is provided in the matrix with bit line fragments (16) that are mutually disconnected. Delays are monitored by coupling at least the first inverters (100) of cells in respective pairs of rows in series via the bit-line fragments and measuring a delay during signal propagation through the series connection, for example by in corporating the series of inverters in a ring oscillator.

Abstract: In an SRAM cell including a first to a fourth semiconductor thin plates which stand on a substrate and are arranged in parallel to each other, on each of the four semiconductor thin plates being formed a first four-terminal double-gate FET with a first conductivity type; a second and a third four-terminal double-gate FETs which are connected in series with each other and have a second conductivity type; a fourth and a fifth four-terminal double-gate FETs which are connected in series with each other and have the second conductivity type; a sixth four-terminal double-gate FET with the first conductivity type, wherein the third and the fourth four-terminal double-gate FETs form select transistors, and the first, the second, the fifth and the sixth four-terminal double-gate FETs form a CMOS inverter, logic signal input gates of the first and the sixth four-terminal double-gate FETs are arranged on the side facing the second and the third semiconductor thin plates, respectively, while threshold voltage control ga

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer.

Abstract: A magnetoresistive element includes: a magnetization free layer having a first plane and a second plane located on the opposite side from the first plane, and having a variable magnetization direction; a magnetization pinned layer provided on the first plane side of the magnetization free layer, and having a pinned magnetization direction; a first tunnel barrier layer provided between the magnetization free layer and the magnetization pinned layer; a second tunnel barrier layer provided on the second plane of the magnetization free layer; and a non-magnetic layer provided on a plane on the opposite side of the second tunnel barrier layer from the magnetization free layer. The magnetization direction of the magnetization free layer is variable by applying current between the magnetization pinned layer and the non-magnetic layer, and a resistance ratio between the first tunnel barrier layer and the second tunnel barrier layer is in a range of 1:0.25 to 1:4.

Abstract: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.

Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

Abstract: A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result.

Abstract: A structure of a storage device which can operate memory elements utilizing silicide reaction using the same voltage value for writing and for reading, and a method for driving the same are proposed. The present invention relates to a storage device including a memory element and a circuit which changes a polarity of applying voltage to the memory element for writing (or reading) into a different polarity of that for reading (or writing). The memory element includes at least a first conductive layer, a film including silicon formed over the first conductive layer, and a second conductive layer formed over the silicon film. The first conductive layer and the second conductive layer of the memory element are formed using different materials.

Abstract: The invention discloses a method to store digital information through use of spin torque transfer in a device that has a very low critical current. This is achieved by adding a spin filtering layer whose direction of magnetization is fixed to be parallel to the device's pinned layer.

Abstract: A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor.

Abstract: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.