Patents Issued in December 30, 2010
  • Publication number: 20100330716
    Abstract: An electroluminescent device including a transparent substrate, a securing layer, a light scattering layer, an electroluminescent unit including a transparent electrode layer, a light emitting element including at least one light emitting layer, and a reflecting electrode layer in that order, wherein the light scattering layer includes one monolayer of inorganic particles having an index of refraction larger than that of the light emitting layer and wherein the securing layer holds the inorganic particles in the light scattering layer.
    Type: Application
    Filed: September 2, 2010
    Publication date: December 30, 2010
    Applicant: GLOBAL OLED TECHNOLOGY
    Inventors: Yuan-Sheng Tyan, Jin-Shan Wang, Raymond A. Kesel, Giuseppe Farruggia, Thomas R. Cushman
  • Publication number: 20100330717
    Abstract: A high-efficiency semiconductor light emitting diode and a method for manufacturing the same are provided. The semiconductor LED has high internal quantum efficiency and can reduce the bad effect caused by the crystal defect. In the semiconductor light emitting diode, a conductive substrate has a three-dimensional top surface, and a light-emitting stack structure has a three-dimensional structure and includes an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer, which are sequentially formed on the conductive substrate. A p-electrode is formed on the p-type nitride semiconductor layer, and an n-electrode is formed on a bottom surface of the conductive substrate.
    Type: Application
    Filed: September 14, 2010
    Publication date: December 30, 2010
    Applicant: SAMSUNG LED CO., LTD.
    Inventors: Pun Jae CHOI, Sang Yeob Song, Suk Youn Hong
  • Publication number: 20100330718
    Abstract: A method of manufacturing an LCD device is disclosed.
    Type: Application
    Filed: December 23, 2009
    Publication date: December 30, 2010
    Inventors: Seok Woo Lee, Seung Chan Choi
  • Publication number: 20100330719
    Abstract: A method of forming a transflective LCD panel is provided. The transflective LCD includes a substrate, a first polycrystalline silicon pattern disposed in a reflection region, a second polycrystalline silicon pattern disposed in a peripheral region, an insulating layer disposed on the first and second polycrystalline silicon pattern and the substrate, a gate electrode disposed in the reflection region, a common electrode disposed in the peripheral region, a first inter-layer dielectric disposed on the insulating layer, the gate electrode and the common electrode, a reflection electrode disposed on the first inter-layer dielectric, a second inter-layer dielectric disposed on the first inter-layer dielectric and the reflection electrode, and a transmission electrode disposed on the second inter-layer dielectric and electrically connected to the reflection electrode through an opening of the second inter-layer dielectric.
    Type: Application
    Filed: September 10, 2010
    Publication date: December 30, 2010
    Inventors: Yu-Cheng Chen, Tun-Chun Yang
  • Publication number: 20100330720
    Abstract: A laser diode comprising a first separate confinement heterostructure and an active region on the first separate confinement heterostructure. A second separate confinement heterostructure is on the active region and one or more epitaxial layers is on the second separate confinement heterostructure. A ridge is formed in the epitaxial layers with a first mesa around the ridge. The first mesa is 0.1 to 0.2 microns above the second confinement heterostructure.
    Type: Application
    Filed: September 13, 2010
    Publication date: December 30, 2010
    Inventors: STEVEN DENBAARS, Shuji Nakamura, Monica Hansen
  • Publication number: 20100330721
    Abstract: A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.
    Type: Application
    Filed: September 1, 2010
    Publication date: December 30, 2010
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: GABRIELE BARLOCCHI, PIETRO CORONA, DINO FARALLI, FLAVIO FRANCESCO VILLA
  • Publication number: 20100330722
    Abstract: A method for fabricating the MEMS device includes providing a substrate. Then, a structural dielectric layer is formed over the substrate at a first side, wherein a diaphragm is embedded in the structural dielectric layer. The substrate is patterned from a second side to form a cavity in corresponding to the diaphragm and a plurality of venting holes in the substrate. An isotropic etching process is performed from the first side and the second side of the substrate via vent holes to remove a dielectric portion of the structural dielectric layer for exposing a central portion of the diaphragm while an end portion is held by a residue portion of the structural dielectric layer.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 30, 2010
    Applicant: SOLID STATE SYSTEM CO., LTD.
    Inventors: Tsung-Min Hsieh, Chien-Hsing Lee
  • Publication number: 20100330723
    Abstract: In a method of manufacturing a photoelectric conversion device having a pixel region and a peripheral circuit region, a semiconductor compound layer is formed by causing a surface of a diffusion layer or gate electrode of a MOS transistor in the peripheral circuit region to react with a high melting point metal, then an insulating layer is formed in the pixel region and the peripheral circuit region after the step of forming a semiconductor compound layer. A contact hole is formed in the insulating layer to expose a diffusion layer in the pixel region, and a contact hole is formed in the insulating layer to expose the semiconductor compound layer formed in the peripheral circuit region. These holes are formed at different timings. Prior to forming the hole which is formed later, a contact plug is formed in the contact hole which is formed earlier.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 30, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Takehito Okabe, Hiroaki Naruse, Ryuichi Mishima, Kouhei Hashimoto
  • Publication number: 20100330724
    Abstract: A solid-state imaging device including an imaging region having a plurality of pixels arranged in a two-dimensional matrix and a peripheral circuit detecting output signals from the pixels. An impurity concentration in a transistor of each pixel is lower than an impurity concentration in a transistor of the peripheral circuit. Further, the impurity concentration of a semiconductor well region under a floating diffusion portion in the pixel is set to be lower than the impurity concentration of a semiconductor well region under a transistor portion at the subsequent stage of the floating diffusion portion.
    Type: Application
    Filed: August 11, 2010
    Publication date: December 30, 2010
    Applicant: SONY CORPORATION
    Inventors: MAKI SATO, SUSUMU OOKI
  • Publication number: 20100330725
    Abstract: In a semiconductor device which has through holes in an end face, in which a semiconductor element is fixedly mounted on a face of a substrate which has a wiring pattern, which is conductive to the wiring portion formed in the through hole, in at least one face, in which electrodes of the semiconductor element are electrically connected to the wiring pattern, and in which the face of the substrate which has the semiconductor element is coated with a resin, the through hole has a through hole land with a width of 0.02 mm or more, which is conductive to the wiring portion, in a substrate face, and the wiring portion and the through hole land are exposed.
    Type: Application
    Filed: September 14, 2010
    Publication date: December 30, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Tetsuo Yoshizawa, Shin-ichi Urakawa, Takashi Miyake
  • Publication number: 20100330726
    Abstract: A photovoltaic module comprises electrically interconnected and mutually spaced photovoltaic cells that are encapsulated by a light-transmitting encapsulant between a light-transparent front cover and a back cover, with the back cover sheet being an ionomer/nylon alloy embossed with V-shaped grooves running in at least two directions and coated with a light reflecting medium so as to provide light-reflecting facets that are aligned with the spaces between adjacent cells and oriented so as to reflect light falling in those spaces back toward said transparent front cover for further internal reflection onto the solar cells, whereby substantially all of the reflected light will be internally reflected from said cover sheet back to the photovoltaic cells, thereby increasing the current output of the module. The internal reflector improves power output by as much as 67%.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Inventors: Ronald C. Gonsiorawski, Steven Gonsiorawski
  • Publication number: 20100330727
    Abstract: A method for fabricating butt-coupled electro-absorptive modulators is disclosed. A butt-coupled electro-absorptive modulator with minimal dislocations in the electro-absorptive material is produced by adding a dielectric spacer for lining the coupling region before epitaxially growing the SiGe or other electro-absorptive material. It has been determined that during the SiGe growth, the current process has exposed single crystal silicon at the bottom of the hole and exposed amorphous silicon on the sides. SiGe growth on the amorphous silicon is expected to have more dislocations than single crystal silicon. There should also be dislocations or fissures where the SiGe growth from the each nucleation source finally join. Thus, a dielectric sidewall can protect an exposed waveguide face from any etching from an aggressive surface preparation prior to epi growth.
    Type: Application
    Filed: August 29, 2008
    Publication date: December 30, 2010
    Inventors: Craig M. Hill, Andrew T.S. Pomerene
  • Publication number: 20100330728
    Abstract: A back-illuminated image sensor includes a sensor layer disposed between a circuit layer adjacent to a frontside of the sensor layer and a layer disposed on a backside of the sensor layer. One or more first alignment marks are formed in a layer in the circuit layer. A masking layer is aligned to the one or more first alignment marks. The masking layer includes openings that define locations for one or more second alignment marks. The one or more second alignment marks are then formed in or through the layer disposed on a backside of a sensor layer. One or more elements are formed in or on the backside of the sensor layer. The one or more elements are aligned to one or more second alignment marks.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventors: John P. McCarten, Cristian A. Tivarus, Joseph R. Summa
  • Publication number: 20100330729
    Abstract: The present invention provides a photoelectric conversion device in which a leakage current is suppressed. A photoelectric conversion device of the present invention comprises: a first electrode over a substrate; a photoelectric conversion layer including a first conductive layer having one conductivity, a second semiconductor layer, and a third semiconductor layer having a conductivity opposite to the one conductivity of the second semiconductor layer over the first electrode, wherein an end portion of the first electrode is covered with the first semiconductor layer; an insulating film, and a second electrode electrically connected to the third semiconductor film with the insulating film therebetween, over the insulating film, are formed over the third semiconductor film, and wherein a part of the second semiconductor layer and a part of the third semiconductor layer is removed in a region of the photoelectric conversion layer, which is not covered with the insulating film.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 30, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuusuke Sugawara, Kazuo Nishi, Tatsuya Arao, Daiki Yamada, Hidekazu Takahashi, Naoto Kusumoto
  • Publication number: 20100330730
    Abstract: The present invention discloses a method of manufacturing a solar cell by forming two electrode layers on the same side of a wafer, and avoiding sunlight incident to another side from being blocked by the electrode layers to enhance the photoelectric conversion efficiency, and each electrode layer is formed by using a mask layer to perform a vapor deposition process, without requiring any mask lithography or etching process. Of course, the issue of a high-temperature process that deteriorates the quality of the wafer no longer exists.
    Type: Application
    Filed: June 28, 2009
    Publication date: December 30, 2010
    Inventors: Lu-Sheng HONG, Wen-Ching Hsu, Szu-Hua Ho
  • Publication number: 20100330731
    Abstract: A semiconductor donor body such as a wafer is implanted with ions to form a cleave plane. The donor wafer is affixed to a polyimide receiver element, for example by applying polyimide in liquid form to the donor wafer, then curing, or by affixing the donor wafer to a preformed polyimide sheet. Annealing causes a lamina to cleave from the donor wafer at the cleave plane. The resulting adhered lamina and polyimide body are not adhered to another rigid substrate and can be jointly flexed.
    Type: Application
    Filed: June 27, 2009
    Publication date: December 30, 2010
    Applicant: TWIN CREEKS TECHNOLOGIES, INC.
    Inventors: Aditya Agarwal, Kathy J. Jackson
  • Publication number: 20100330732
    Abstract: A method for manufacturing a thin film photoelectric conversion module includes the steps of forming a plurality of photoelectric conversion elements connected in series on a substrate, and carrying out reverse bias processing simultaneously on a group of photoelectric conversion elements including a plurality of the photoelectric conversion elements positioned with one or a plurality of the photoelectric conversion elements interposed between each of them, by applying a plurality of voltages electrically isolated from one another to the group of photoelectric conversion elements.
    Type: Application
    Filed: January 28, 2009
    Publication date: December 30, 2010
    Inventor: Shinsuke Tachibana
  • Publication number: 20100330733
    Abstract: A method of manufacturing partially light transparent thin film solar cells generally includes forming a solar cell structure stack and forming multiple openings through the solar cell structure stack. The solar cell structure stack includes a flexible foil substrate, a contact layer formed over the flexible foil substrate, a Group IBIIIAVIA absorber layer formed over the contact layer and a transparent conductive layer formed over the Group IBIIIAVIA absorber layer. A terminal structure including at least one busbar and a plurality of conductive finger patterns is deposited onto a top surface of the transparent conductive layer forming a semi-transparent solar cell.
    Type: Application
    Filed: September 13, 2010
    Publication date: December 30, 2010
    Applicant: SoloPower, Inc.
    Inventor: Bulent M. Basol
  • Publication number: 20100330734
    Abstract: In a manufacturing process of a solar cell comprising an amorphous silicon unit in which a p-type layer, an i-type layer, and an n-type layer are layered, in a step of forming the p-type layer, a doping concentration of a p-type dopant included in the p-type layer is increased as a distance from the i-type layer is increased, and in particular, a high-absorption amorphous silicon carbide layer and a low-absorption amorphous silicon carbide layer are consecutively formed while a state of plasma generation is maintained.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Mitsuhiro Matsumoto, Makoto Nakagawa
  • Publication number: 20100330735
    Abstract: A method of forming an optical sensor includes the following steps. A substrate is provided, and a read-out device is formed on the substrate. a first electrode electrically connected to the read-out device is formed on the substrate. a photosensitive silicon-rich dielectric layer is formed on the first electrode, wherein the photosensitive silicon-rich dielectric layer comprises a plurality of nanocrystalline silicon crystals. A second electrode is formed on the photosensitive silicon-rich dielectric layer.
    Type: Application
    Filed: September 1, 2010
    Publication date: December 30, 2010
    Inventors: An-Thung Cho, Chia-Tien Peng, Kun-Chih Lin
  • Publication number: 20100330736
    Abstract: When a layered structure of a transparent electrode layer and a metal layer is formed as a back side electrode layer over a surface on a side opposite to a side of incidence of light of a thin film solar battery, a time when formation of the transparent electrode layer is completed and a time when formation of the metal layer is started are made to coincide for one substrate.
    Type: Application
    Filed: March 30, 2010
    Publication date: December 30, 2010
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventor: Kazushige Kaneko
  • Publication number: 20100330737
    Abstract: A method includes the steps of forming a contiguous semiconducting region and heating the region. The semiconducting region includes polyaromatic molecules. The heating raises the semiconducting region to a temperature above room temperature. The heating is performed in the presence of a dopant gas and the absence of light to form a doped organic semiconducting region.
    Type: Application
    Filed: September 3, 2010
    Publication date: December 30, 2010
    Applicants: Lucent Technologies Inc., The Trustees of Columbia University
    Inventors: Christian Leo Kloc, Arthur Penn Ramirez, Woo-Young So
  • Publication number: 20100330738
    Abstract: An oxide semiconductor target of a ZTO (zinc tin complex oxide) type oxide semiconductor material of an appropriate (Zn/(Zn+Sn)) composition having high mobility and threshold potential stability and with less restriction in view of the cost and the resource and with less restriction in view of the process, and an oxide semiconductor device using the same, in which a sintered Zn tin complex oxide with a (Zn/(Zn+Sn)) composition of 0.6 to 0.8 is used as a target, the resistivity of the target itself is at a high resistance of 1 ?cm or higher and, further, the total concentration of impurities is controlled to 100 ppm or less.
    Type: Application
    Filed: April 9, 2010
    Publication date: December 30, 2010
    Inventors: Hiroyuki Uchiyama, Hironori Wakana, Tetsufumi Kawamura, Fumi Kurita, Hideko Fukushima
  • Publication number: 20100330739
    Abstract: Materials, devices, and methods for enhancing performance of electronic devices such as solar cells, fuels cells, LEDs, thermoelectric conversion devices, and other electronic devices are disclosed and described. A diamond-like carbon electronic device can include a conductive diamond-like carbon cathode having specified carbon, hydrogen and sp2 bonded carbon contents. In some cases, the sp2 bonded carbon content may be sufficient to provide the conductive diamond-like carbon material with a visible light transmissivity of greater than about 0.70. A charge carrier separation layer can be coupled adjacent and between the diamond-like carbon cathode and an anode. The conductive diamond-like carbon material of the present invention can be useful for any other application which can benefit from the use of conductive and transparent electrodes which are also chemically inert, radiation damage resistance, and are simple to manufacture.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Inventor: Chien-Min Sung
  • Publication number: 20100330740
    Abstract: A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.
    Type: Application
    Filed: September 10, 2010
    Publication date: December 30, 2010
    Inventor: David Pratt
  • Publication number: 20100330741
    Abstract: A fabrication method for a system-on-chip (SoC) module is provided. The fabrication method includes the steps of providing at least two SoC sub-modules and connecting the SoC sub-modules. The SoC sub-modules are electrically connected with each other by connection interfaces of the SoC sub-modules so as to form the SoC module. As the SoC sub-modules have been verified in advance, the time required for verifying the resulting SoC module can be significantly reduced. As for application-specific SoC modules, they are fabricated by connecting with application-specific SoC sub-modules via the appropriate connection interfaces. Thus, the time and costs for developing SoC modules can both be minimized.
    Type: Application
    Filed: September 30, 2009
    Publication date: December 30, 2010
    Applicant: National Chip Implementation Center National Applied Research Laboratories.
    Inventors: Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chin-Long Wey, Chi-Shi Chen, Chi-Sheng Lin
  • Publication number: 20100330742
    Abstract: A first conductive member made of metal is provided over a first wiring substrate, which is a mounting substrate in the lower tier, a through hole is provided in a second wiring substrate, which is a mounting substrate in the upper tier, at a position corresponding to the first conductive member in a plan view, and a wiring is exposed at the sidewall of the through hole. The first conductive member is inserted into the through hole on the corresponding first wiring substrate side and the first wiring substrate and the second wiring substrate are electrically coupled by filling the through hole with a second conductive member. an electrode pad that is electrically coupled to the second conductive member and over which a semiconductor member in the upper tier is mounted is formed on the main surface side of the second wiring substrate.
    Type: Application
    Filed: June 4, 2010
    Publication date: December 30, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Michiaki Sugiyama, Takashi Miwa, Toshikazu Ishikawa, Tatsuya Hirai
  • Publication number: 20100330743
    Abstract: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.
    Type: Application
    Filed: September 9, 2010
    Publication date: December 30, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu, Hung-Jung Tu, Ku-Feng Yang
  • Publication number: 20100330744
    Abstract: The invention relates to an ultrathin semiconductor circuit having contact bumps and to a corresponding production method. The semiconductor circuit includes a bump supporting layer having a supporting layer thickness and having a supporting layer opening for uncovering a contact layer element being formed on the surface of a semiconductor circuit. An electrode layer is situated on the surface of the contact layer element within the opening of the bump supporting layer, on which electrode layer is formed a bump metallization for realizing the contact bump. On account of the bump supporting layer, a thickness of the semiconductor circuit can be thinned to well below 300 micrometers, with the wafer reliably being prevented from breaking. Furthermore, the moisture barrier properties of the semiconductor circuit are thereby improved.
    Type: Application
    Filed: September 8, 2010
    Publication date: December 30, 2010
    Inventors: Dirk Muller, Manfred Schneegans, Sokratis Sgouridis
  • Publication number: 20100330745
    Abstract: The process for producing a semiconductor device of the invention is a process for producing a semiconductor device, comprising: a temporarily bonding step of bonding a semiconductor element temporarily on an adherend through an adhesive sheet, a semi-curing step of heating the adhesive sheet under predetermined conditions, thereby turning the sheet into a semi-cured state that the shearing adhering strength of the sheet to the adherend is 0.5 MPa or more, and a wire bonding step of causing the semiconductor element to undergo wire bonding in the state that the adhesive sheet is semi-cured.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventors: Masami Oikawa, Takeshi Matsumura, Sadahito Misumi
  • Publication number: 20100330746
    Abstract: A method of manufacturing a semiconductor package, including at least a step A that forms a first transforming portion by irradiating a laser beam on at least a portion of a first substrate; a step B that joins together the first substrate and a second substrate in which a functional element is disposed; a step C that removes the first transforming portion that is disposed on the first substrate by etching; and a step D that forms a conductive portion in the first substrate by filling a conductive material in a portion where the first transforming portion has been removed.
    Type: Application
    Filed: September 1, 2010
    Publication date: December 30, 2010
    Applicant: Fujikura Ltd.
    Inventor: Shogo Mitani
  • Publication number: 20100330747
    Abstract: A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board.
    Type: Application
    Filed: August 31, 2010
    Publication date: December 30, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Joon-Sik Shin, Nobuyuki Ikeguchi, Keungjin Sohn, Joung-Gul Ryu, Sang-Youp Lee, Jung-Hwan Park, Ho-Sik Park
  • Publication number: 20100330748
    Abstract: Methods of encapsulating an environmentally sensitive device. The methods involve temporarily laminating a flexible substrate to a rigid support using a reversible adhesive for processing, reversing the reversible adhesive, and removing the device from the rigid support.
    Type: Application
    Filed: January 26, 2007
    Publication date: December 30, 2010
    Inventors: Xi Chu, Steve Shi Lin, Gordon L. Graff
  • Publication number: 20100330749
    Abstract: Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.
    Type: Application
    Filed: September 3, 2010
    Publication date: December 30, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Boon Suan Jeung, Chia Yong Poo, Eng Meow Koon
  • Publication number: 20100330750
    Abstract: A thin film transistor (TFT) including a nanowire semiconductor layer having nanowires aligned in one direction in a channel region is disclosed. The nanowire semiconductor layer is selectively formed in the channel region. A method for fabricating the TFT, a liquid crystal display (LCD) device using the TFT, and a method for manufacturing the LCD device are also disclosed. The TFT fabricating method includes forming alignment electrodes on the insulating film such that the alignment electrodes face each other, to define a channel region, forming an organic film, to expose the channel region, coating a nanowire-dispersed solution on an entire surface of a substrate including the organic film, forming a nanowire semiconductor layer in the channel region by generating an electric field between the alignment electrodes such that nanowires of the nanowire semiconductor layer are aligned in a direction, and removing the organic film.
    Type: Application
    Filed: August 31, 2010
    Publication date: December 30, 2010
    Applicant: LG Display Co., Ltd.
    Inventors: Bo Hyun Lee, Tae Hyoung Moon, Jae Hyun Kim
  • Publication number: 20100330751
    Abstract: The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor operating at room temperature and a method of manufacturing the same, which are capable of minimizing influence of the gate voltage on tunneling barriers and effectively controlling the electric potential of a quantum dot (QD), by forming the quantum dot using a trenched nano-wire structure and forming the gate to wrap most of the way around the quantum dot.
    Type: Application
    Filed: September 1, 2010
    Publication date: December 30, 2010
    Applicant: Chungbuk National University Industry-Academic Cooperation Foundation
    Inventors: Jung Bum Choi, Seung Jun Shin
  • Publication number: 20100330752
    Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.
    Type: Application
    Filed: July 23, 2010
    Publication date: December 30, 2010
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Publication number: 20100330753
    Abstract: Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.
    Type: Application
    Filed: September 10, 2010
    Publication date: December 30, 2010
    Inventors: Pil-Kyu Kang, Yong-Hoon Son, Si-Young Choi, Jong-Wook Lee, Byeong-Chan Lee, InSoo Jung
  • Publication number: 20100330754
    Abstract: Various embodiments of the disclosure include the formation of enhancement-mode (e-mode) gate injection high electron mobility transistors (HEMT). Embodiments can include GaN, AlGaN, and InAlN based HEMTs. Embodiments also can include self-aligned P-type gate and field plate structures. The gates can be self-aligned to the source and drain, which can allow for precise control over the gate-source and gate-drain spacing. Additional embodiments include the addition of a GaN cap structure, an AlGaN buffer layer, AlN, recess etching, and/or using a thin oxidized AlN layer. In manufacturing the HEMTs according to present teachings, selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) can both be utilized to form gates.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 30, 2010
    Inventor: Francois Hebert
  • Publication number: 20100330755
    Abstract: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.
    Type: Application
    Filed: September 1, 2010
    Publication date: December 30, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Ru-Shang Hsiao, Min Cao, Chung-Te Lin, Ta-Ming Kuan, Cheng-Tung Hsu
  • Publication number: 20100330756
    Abstract: A method of manufacturing an integrated circuit structure implants a first-type of channel implant in a first area of a substrate and implants a second-type of channel implant in a second area of the substrate. The method forms at least one first gate conductor above the first area of the substrate and forms at least one second gate conductor above the second area of the substrate. The method forms a hard mask over the first gate conductor, the second gate conductor, and the substrate. The hard mask comprises an oxide or a nitride and patterns an organic photoresist over the hard mask, to leave the organic photoresist on areas of the hard mask that are above the first area of the substrate. The method removes portions of the hard mask not protected by the organic photoresist to leave the hard mask on the first area of the substrate and not on the second area of the substrate.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Toshiharu Furukawa, Steven J. Holmes
  • Publication number: 20100330757
    Abstract: When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 30, 2010
    Inventors: Markus Lenski, Kerstin Ruttloff, Martin Mazur, Frank Seliger, Ralf Otterbach
  • Publication number: 20100330758
    Abstract: A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buri
    Type: Application
    Filed: January 19, 2010
    Publication date: December 30, 2010
    Inventors: Jin-bum Kim, Wook-je Kim, Kwan-heum Lee, Yu-gyun Shin, Sun-ghil Lee
  • Publication number: 20100330759
    Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
    Type: Application
    Filed: August 26, 2008
    Publication date: December 30, 2010
    Inventor: Leonard Forbes
  • Publication number: 20100330760
    Abstract: A fabrication method of trenched metal-oxide-semiconductor device is provided. A pattern layer with a plurality of openings is formed on a semiconductor base, and then a spacer is formed on the sidewall of the opening to define the gate trench. After the gate electrode formed in the gate trench, a dielectric structure is formed on the gate electrode by filling dielectric material into the opening. Then, the pattern layer and the spacer are removed and a dielectric layer is formed on the dielectric structure. The portion of the dielectric layer on the sidewall of the dielectric structure defines the source regions. After the source regions are formed in the well, another dielectric layer is formed on the dielectric layer to define the heavily doped regions adjacent to the source regions.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Inventors: Kao-Way Tu, Yen-Chih Huang
  • Publication number: 20100330761
    Abstract: Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.
    Type: Application
    Filed: September 10, 2010
    Publication date: December 30, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Woo Oh, Sung-Hwan Kim, Dong-Gun Park
  • Publication number: 20100330762
    Abstract: A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width.
    Type: Application
    Filed: September 13, 2010
    Publication date: December 30, 2010
    Applicant: SPANSION LLC
    Inventors: Weidong Qian, Mark T. Ramsbey, Tazrien Kamal
  • Publication number: 20100330763
    Abstract: The present invention provides a method of forming asymmetric field-effect-transistors.
    Type: Application
    Filed: June 29, 2009
    Publication date: December 30, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory G. Freeman, Shreesh Narasimha, Ning Su, Hasan M. Nayfeh, Nivo Rovedo, Werner A. Rausch, Jian Yu
  • Publication number: 20100330764
    Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode, a source region and a drain region, forming a first metal layer, forming silicide layers by first annealing, removing a remainder of the first metal layer after the first annealing, performing a second annealing, forming a second metal layer, performing a third annealing, and removing a remainder of the second metal layer.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinichi Akiyama, Kazuya Okubo, Yusuke Morisaki, Youichi Momiyama
  • Publication number: 20100330765
    Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.
    Type: Application
    Filed: September 9, 2010
    Publication date: December 30, 2010
    Applicant: Infineon Technologies AG
    Inventors: Karlheinz Muller, Klaus Roschlau