Abstract: A flexible electronic assembly including a flexible circuit board and at least one electronic component is provided. The flexible circuit board includes at least one dielectric film layer and at least one patterned conductive layer disposed on the dielectric film layer. The electronic component is disposed on the flexible circuit board and electrically connected to the flexible circuit board. The flexible angle of the flexible electronic assembly is greater than 5 degrees.

Abstract: A system component of a control device, especially for a transmission or engine controller of a motor vehicle, is provided as a closed system component for a control device which can be transported, thereby allowing decentralized manufacturing of the system component. The system component has a hybrid circuit, equipped with electronic components, which is embedded in a printed circuit board, recessed in the center, in such a manner that the hybrid circuit is completely enclosed by the printed circuit board. The hybrid circuit and the printed circuit board are mounted on a base element and connected to each other via contact elements. A cover element is positioned on top of the hybrid circuit and the contact elements in such a manner that the hybrid circuit is fully encapsulated by the base element, the cover element and the printed circuit board from environmental influences.

Abstract: A component incorporating module includes an insulation resin layer, a plurality of lands arranged to mount components and wiring patterns connected to the plurality of lands, which are arranged along a first main surface of the resin layer, and circuit components connected to the lands to mount components. The circuit components are embedded in the resin layer. The plurality of lands have thicknesses that are greater than those of the wiring patterns adjacent to the corresponding lands.

Abstract: A communication cabinet and methods for installing active component into a communication cabinet, the method includes: removing at least one passive communication connector being connected by at least one wire to at least one customer connector within the communication cabinet; installing at least one printed circuit board that are connected to at least one active communication component and to at least one slim edge connector; wherein the printed circuit boards are shaped such as to be completely positioned within the communication cabinet; and connecting the at least one wire to the at least one slim edge connector.

Abstract: A circuit board assembly which includes an electrically insulating layer, a conductive printed wiring layer formed on the surface of the electrically insulating layer and includes a plurality of conductive paths, a conductive trace on the electrically insulating layer and apparatus for dissipating a transient in addition to a surface mount resistor fixed in relation to the trace. In some forms of the invention the surface mount resistor has opposed generally planar lips. The trace may also be generally planar. In some cases the lower lips and the trace are generally parallel. The generally planar lips of the surface mount resistor may be closer to the trace than the thickness of the surface mount resistor. A single geometric plane may extend through substantially all of the lips and all of the trace. In some cases the lower surface of the lips and the lower surface of the trace are substantially coplanar.

Abstract: A control circuit for soft switching and synchronous rectifying is provided for power converter. A switching-signal circuit is used for generating drive signals and a pulse signal in response to a leading edge and a trailing edge of a switching signal. The switching signal is developed for regulating the power converter. Drive signals are coupled to switch the power transformer. A propagation delay is developed between drive signals to achieve soft switching of the power converter. An isolation device is coupled to transfer the pulse signal from a primary side of a power transformer to a secondary side of the power transformer. A controller of the integrated synchronous rectifier is coupled to the secondary side of the power transformer for the rectifying operation. The controller is operated to receive the pulse signal for switching on/off the power transistor. The pulse signal is to set or reset a latch circuit of the controller for controlling the power transistor.

Abstract: A control unit controls cascaded PFC and LLC converters, the LLC converter having an input coupled to an output, of the PFC converter and providing an output voltage that decreases with increasing switching frequency. The control unit produces a sawtooth waveform with a linear ramp for controlling the LLC converter switching frequency, and hence its output voltage, in dependence upon a feedback signal. It also produces for the PFC converter a PWM signal with a frequency that is the same as or an integer fraction of the LLC converter switching frequency, by comparing two thresholds with the linear ramp in respective different cycles of the sawtooth waveform to turn on and off a switch of the PFC converter during these different cycles. Logic circuits prevent PFC converter switch transitions from occurring simultaneously with switching transitions of the LLC converter.

Abstract: The present invention relates to a forward converter with self-driven synchronous rectifiers, which utilizes a secondary driving winding and a secondary driving circuit to drive the synchronous rectifiers in the secondary power loop. The secondary driving circuit, which is composed of a level shifter and a signal distributor, can shift the voltage waveform across the secondary driving winding by a predetermined level and distribute proper driving signals to the synchronous rectifiers to reduce the rectifier conduction loss. Specially, the channel of the freewheeling synchronous rectifier still can be turned on during the dead interval to further reduce the body diode conduction loss.

Abstract: A modularized active power filter includes a control module and at least one power module. The control module automatically identifies the number of parallel connected power modules and generates one set of PWM signals to correspondingly control the parallel connected power modules, so as to provide a final compensation current by a single power module or by plural power modules. Thereby, the compensation demand of a load is met. Consequently, the modularized active power filter is able to improve flexibility of compensation capacity, to shorten the time for service, to be suitable for mass production, and to lower the manufacturing cost.

Abstract: A method is provided for controlling a converter of the multiphase interleaving type. According to the method, there is detected when a change of the load applied to an output terminal of the converter occurs. All the phases of the converter are simultaneously turned on, and a driving interleaving phase shift is recovered to restart a normal operation of the converter. A controller for carrying out such a method is also provided.

Abstract: A power conversion system comprises: a source of multiphase high frequency alternating current (AC) electrical input power; a high frequency controlled magnetics transformer for each phase of the multiphase high frequency AC input power, with each transformer having a primary winding coupled to its respective phase of the multiphase high frequency AC input power, at least one secondary winding that produces high frequency AC output power and at least one control winding responsive to a direct current (DC) control signal that changes the high frequency output power in proportion to the amplitude of the DC control signal; a power converter that receives the multiphase high frequency AC output power from each high frequency transformer secondary and converts it to system output power without the high frequency AC content; and a system controller responsive to the system output power that produces a DC control signal for each control winding that changes in amplitude in response to changes in a measured parameter

Abstract: Aspects of the disclosure provide a CAM module that can be used independent of a defective entry line. The CAM module can include at least a CAM array having at least X CAM entry lines, and an additional CAM entry line. Each CAM entry line may include a selection line for enabling the CAM entry line for writing and/or reading and an entry output for indicating matching to a search key. Further, the CAM module can include a decoder unit that can decode an address to enable one out of X word-lines, and an encoder unit that can encode X matching outputs to a matching address according to a predetermined priority sequence. Additionally, the CAM module can include a switching unit coupling the CAM array with the decoder unit and the encoder unit.

Abstract: A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements. In one aspect a circuit that has one or more clock inputs is run for a predetermined number of clock cycles. The circuit generates an amount of charge over the predetermined number of clock cycles. At most the amount of charge is provided to non-volatile storage element to program the non-volatile storage element. It is determined whether the non-volatile storage element is programmed to a desired state as a result of providing at most the amount of charge to the non-volatile storage element. Techniques disclosed herein can be applied to program memory cells other than memory cells with reversible resistance-switching elements.

Abstract: A semiconductor storage device includes: a bit line; a first word line; a second word line; a first inverter in which one terminal of a first load transistor is connected to a first driver transistor and their junction point forms a first node; a second inverter in which one terminal of a second load transistor is connected to a second driver transistor and their junction point forms a second node; a first write transistor one terminal of which is connected to the first load transistor and the other terminal of which is connected to a power supply voltage; a second write transistor one terminal of which is connected to the first driver transistor and the other terminal is connected to a reference potential; and an access transistor one terminal of which is connected to the first node and the other terminal of which is connected to the bit line.

Abstract: A method testing an SRAM having a plurality of memory cells is disclosed. In a first step, a bit value is written into a cell under test (CUT). Subsequently, the first and second enabling transistors are disabled and the bit lines are discharged to a low potential. Next, the word line (WL) coupled to the memory cell under test is activated for a predetermined period. During a first part of this period, one of the bit lines (BLB) is kept at the low potential to force the associated pull up transistor in the CUT into a conductive state, after which this bit line (BLB) is charged to a high potential. Upon completion of this period, the bit value of the first cell is determined. The method facilitates the detection of weak or faulty SRAM cells without requiring the inclusion of dedicated hardware for this purpose.

Abstract: The incidence of half-select errors during MRAM programming has been significantly reduced by giving the free layer a shape that approximates an X so that, when the free layer switches, the magnetization in the arms of the X guides the magnetization in the central section (the X's intersection area) causing it to rotate towards the hard axis in two opposing directions. This raises the free layer's switching energy barrier, thereby reducing half-select errors.

Abstract: A magnetic random access memory of the present invention includes: a plurality of first wirings and a plurality of second wirings extending in a first direction; a plurality of third wirings and a plurality of fourth wirings extending in a second direction; and a plurality of memory cells provided at intersections of the plurality of first wirings and the plurality of third wirings, respectively. Each of the plurality of memory cells includes: a first transistor and a second transistor connected in series between one of the plurality of first wirings and one of the plurality of second wirings and controlled in response to a signal on one of the plurality of third wirings, a first magnetic resistance element having one end connected to a write wiring through which the first transistor and the second transistor are connected, and the other end grounded; and a second magnetic resistance element having one end connected to the write wiring, and the other end connected to the fourth wiring.

Abstract: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.

Abstract: In accordance with various embodiments, a column of non-volatile memory cells is connected between opposing first and second control lines. A fixed reference voltage is applied to the second control line. The memory cells are simultaneously programmed to a first resistive state by applying a first voltage to the first control line that is greater than the fixed reference voltage. Less than all of the memory cells are subsequently simultaneously programmed to a different, second resistive state by applying a second voltage to the first control line that is less than the fixed reference voltage, so that at the conclusion of the respective programming steps a first portion of the memory cells along said column are at the first resistive state and a second portion of the memory cells along said column are at the second resistive state.

Abstract: In one aspect, a non-volatile semiconductor memory device includes a phase phase-change memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of phase-change memory cells, where each the phase-change memory cells includes a phase-change resistive element and a diode connected in series between a word line and a bit line among the plurality of word lines and bit lines of the phase-change memory cell array. The memory device of this aspect further includes a sense node which is selectively connected to a bit line of the phase-change memory cell array, a boosting circuit which generates a boosted voltage which is greater than an internal power supply voltage, a pre-charge and biasing circuit which is driven by the boosted voltage to pre-charge and bias the sense node, and a sense amplifier connected to the sense node.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: A phase change random access memory (PRAM) includes a cell array divided into an active region and a dummy active region. A bitline is formed across the active region and the dummy active region and a global wordline is formed in the active region so as to intersect with the bitline. The cell array includes a phase change memory cell formed at an intersection point of the bitline and the global wordline that is electrically connected with the bitline and the global wordline. The cell array further includes a phase change dummy cell formed below the bitline in the dummy active region that is electrically isolated from the bitline. The dummy cell maintains a turn-off state as the dummy cell and the bitline are electrically isolated from each other.

Abstract: According to a method for multilevel reading of a phase change memory cell a bit line (9) and a PCM cell (2) are first selected and a first bias voltage (VBL, V00) is applied to the selected bit line (9). A first read current (IRD00), that flows through the selected bit line (9) in response to the first bias voltage (VBL, V00), is compared with a first reference current (I00). The first reference current (I00) is such that the first read current (IRD00) is lower than the first reference current (I00), when the selected PCM cell (2) is in a reset state, and is otherwise greater. It is then determined whether the selected PCM cell (2) is in the reset state, based on comparing the first read current (IRD00) with the first reference current (I00). A second bias voltage (VBL, V01), greater than the first bias voltage (VBL, V00), is applied to the selected bit line (9) if the selected PCM cell (2) is not in the reset state.

Abstract: In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.

Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.

Abstract: An information storage device includes a magnetic layer configured to store information, a first and second conductive layer. The first conductive layer contacts a first end of the magnetic layer. The second conductive layer contacts a second end of the magnetic layer. The magnetic layer includes first and second pinning regions at which magnetic domain walls are pinned. The widths of the magnetic layer at the first and second pinning regions are different.

Abstract: Magnetic tunnel junction cell including multiple vertical domains. In an embodiment, a magnetic tunnel junction (MTJ) structure is disclosed. The MTJ structure includes an MTJ cell. The MTJ cell includes multiple vertical side walls. Each of the multiple vertical side walls defines a unique vertical magnetic domain. Each of the unique vertical magnetic domains is adapted to store a digital value.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate including a first channel, and a source region and a drain region provided on both sides of the first channel; a first insulating film provided on the first channel; a charge retention layer provided on the first insulating film; a second insulating film provided on the charge retention layer; and a semiconductor layer including a second channel provided on the second insulating film, and a source region and a drain region provided on both sides of the second channel.

Abstract: A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed by setting the threshold voltage to a second voltage level based on a value of the second bit. The second voltage level is the same as the first voltage level if the second bit is a first value and the second voltage level is within a second of the plurality of threshold voltage distributions if the second bit is a second value. A third bit of the multi-bit data is programmed by setting the threshold voltage to a third voltage level based on a value of the third bit.

Abstract: A memory programming method may include identifying at least one of a plurality of memory cells with a threshold voltage to be changed based on a pattern of data to be programmed in the at least one of the plurality of memory cells, applying a program condition voltage to the at least one identified memory cell until the threshold voltage of the at least one identified memory cell is included in a first threshold voltage interval, to thereby adjust the threshold voltage of the at least one identified memory cell, and programming the data in the at least one identified memory cell with the adjusted threshold voltage.

Abstract: Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed.

Abstract: Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a CMOS-compatible non-volatile storage element having a node coupled to the storage node and configured to hold a charge corresponding to a binary value, and an access transistor coupled to the storage node. The access transistor includes a word line gate, a first node, and a second node, the word line gate being coupled to the one of the plurality of row lines, the first node being coupled to the one of the plurality of column lines, the second node being coupled to the storage node and to said node of the CMOS-compatible non-volatile storage element.

Abstract: A flash memory device includes a cell array and a decision unit. The cell array includes multiple regions corresponding to multiple input/output lines. Initialization data are repeatedly stored in each of the regions. The decision unit determines whether the stored data are valid based on values of bits of the stored data read from each region.

Abstract: Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip.

Abstract: A flash memory device and method of controlling a program operation thereof, includes page buffers divided into a predetermined number of groups and a program operation is performed on a group basis.

Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.

Abstract: A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.

Abstract: A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.

Abstract: Disclosed is a method for programming a nonvolatile memory device including one time programmable unit cells. The method for programming a nonvolatile memory device including one time programmable (OTP) unit cells, the method comprising applying a pulse type program voltage having a plurality of cycles. The present invention relates to a method for programming a nonvolatile memory device, which can prevent malfunctions by enhancing a data sensing margin in a read operation through the normal dielectric breakdown of an antifuse during a program operation, and thus improve the reliability in the read operation of an OTP unit cell.

Abstract: Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The reference voltage generating circuit is configured to generate at least one reference voltage to be supplied to the high voltage generating circuit. The reference voltage generating circuit includes a first reference voltage generator configured to generate a first reference voltage in response to a supply voltage, and a second reference voltage generator configured to generate a second reference voltage in response to the first reference voltage. The at least one reference voltage supplied to the high voltage generating circuit includes the second reference voltage.

Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).

Abstract: A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line.

Abstract: A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to one selected in the word lines; and a bit line driver circuit configured to drive multiple bit lines in such a manner that a set mode and a reset mode are set simultaneously for multiple memory cells selected by the selected word line, the set mode being for changing a selected memory cell from a first resistance state into a second resistance state while the reset mode is for changing a selected memory cell from the second resistance state into the first resistance state.

Abstract: A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.

Abstract: An integrated circuit for storing data, and for application in a memory card that operates in cooperation with at least one of an external acquisition system and an external processing system includes input/output terminals for receiving the data to be stored, and an electrically programmable non-volatile memory for storing the data in digital format. The memory includes a first terminal for receiving a programming signal for enabling storage of the data, and a second terminal for receiving a reading signal for enabling output of the stored data via the input/output terminals. A memory control circuit is connected to the first and second terminals of the electrically programmable non-volatile memory, and to the input/output terminals for generating programming and reading signals based upon the command signal. The electrically programmable non-volatile memory is erasable by electromagnetic radiation for permitting a non-electrical erasure of the stored data.

Abstract: A precharge circuit steps up a voltage of a bit line connected to a memory cell to a power supply voltage. A plurality of step-down circuits step down the voltage of the bit line to a voltage level lower than the power supply voltage before data is read from the memory cell. The plurality of step-down circuits are connected to the bit line, and the plurality of step-down circuits are controlled by step-down control signals different to each other.

Abstract: A semiconductor memory device comprises a logic circuit supplied with a first supply voltage; a cell array supplied with a second supply voltage higher than the first supply voltage and including plural mutually intersecting word lines and bit lines and plural memory cells connected at intersections thereof; and a word line driver operative to drive the word lines. The word line driver includes plural pull-up circuits connected between the supply terminal of the first supply voltage and the drive terminal of the word line and between the supply terminal of the second supply voltage and the drive terminal of the word line, and a pull-down circuit connected between the drive terminal of the word line and the ground terminal, and drives the word line with an intermediate voltage between the first and second supply voltages in accordance with a driving force ratio between the plural pull-up circuits at the time of driving the word line.

Abstract: An apparatus for controlling an activation of semiconductor integrated circuit includes: an active control unit configured to generate active control signal for determining activation of banks; and a plurality of active signal generating units configured to input the active control signal commonly, and generate active signals for activating the banks to according to the active control signal. According to this structure, it is possible to reduce current consumption to a minimum in a refresh mode, to easily arrange signal lines, and thus to effectively use extra space.

Abstract: A semiconductor memory device includes a reference strobe signal generator configured to generate a reference strobe signal having a reference pulse width in response to a bank information signal and a column command signal, and a main strobe signal generator configured to generate a main strobe signal by controlling the reference pulse width in response to the reference strobe signal and a bank grouping signal that is activated in a bank grouping mode where columns are continuously accessed in a plurality of logically grouped banks.

Abstract: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.