Abstract: An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal, a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential, a first fuse device coupling the second source/drain terminal to a node, a second fuse device coupling the node to the first pad, a third pad operable to receive a signal to be applied to at least one die, and a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node.

Abstract: A system includes a supporting substrate and at least one semiconductor substrate. The semiconductor component includes a semiconductor substrate having a circuit side with integrated circuits and substrate contacts and a back side, a plurality of through interconnects in the substrate, and redistribution conductors on the back side of the substrate. Each through interconnect includes a via aligned with a substrate contact, and a conductive layer at least partially lining the via in physical and electrical contact with the substrate contact. Each redistribution conductor is formed by a portion of the conductive layer.

Abstract: A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die.

Abstract: A light receiving element 1 has a semiconductor substrate 101; a first mesa 11 provided over the semiconductor substrate 101, and having an active region and a first electrode (p-side electrode 111) provided over the active region; a second mesa 12 provided over the semiconductor substrate 101, and having a semiconductor layer and a second electrode (n-side electrode 121) provided over the semiconductor layer; and a third mesa 13 provided over the semiconductor substrate 101, and having a semiconductor layer, wherein the third mesa 13 is arranged so as to surround the first mesa 11.

Abstract: A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.

Abstract: A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.

Abstract: Provided are a lead frame and a semiconductor package including the same. The lead frame includes a first lead frame portion including a plurality of first leads; an adhesive member disposed such that the first leads are adhered to one surface of the adhesive member; and a second lead frame portion including a plurality of second leads disposed such that the second leads are adhered to the other surface of the adhesive member, wherein the second leads are arranged so as not to overlap with the first leads. The lead frame may optionally include a die pad on which a semiconductor chip is installed.

Abstract: A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent.

Abstract: A resin-sealed semiconductor device with built-in heat sink prevents internal bulging and cracking caused by exfoliation of a semiconductor element from the heat sink when the vapor pressure of moisture absorbed into a gap between the semiconductor element and the heat sink rises during mounting of the semiconductor device to a printed circuit board using lead-free solder. By providing a plurality of separated die pads (502) in a mounting area for a semiconductor element (301) and adhering the semiconductor element (301) to the heat sink (105) via the die pads (502), space is opened up between the semiconductor element (301) and the heat sink (105) for sealing resin (304) to run into.

Abstract: According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of alignment features disposed thereon, the monolithic frame having a mounting surface disposed thereon for the integrated circuit, the monolithic frame also having a thermal interface area disposed thereon for the integrated circuit. The device also includes an electrical interface capable of providing an electrical connection for the integrated circuit, the plurality of alignment features being substantially independent of the electrical interface, and an adhesive layer disposed between the monolithic frame and the electrical interface.

Abstract: A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate.

Abstract: An integrated circuit having an MCM structure, an interface circuit used in the integrated circuit, and an apparatus incorporating the integrated circuit are disclosed. The integrated circuit includes at least two semiconductor devices formed on a common substrate. The semiconductor devices are interconnected via an interface circuit, capable of converting a single-ended signal received from one semiconductor device to a differential signal, and providing the differential signal to another semiconductor device. The interface circuit includes a pair of bonders, which physically connect the semiconductor devices.

Abstract: An interposer has an opening in the central portion. A plurality of first electrode terminals are formed on the front surface near the opening of the interposer, a plurality of second electrode terminals are formed on the front surface of the peripheral portion thereof and corresponding ones of the plurality of first and second electrode terminals are electrically connected to one another via a plurality of wirings. A plurality of bump electrodes is formed on the front surface of a child chip. A plurality of bump electrodes containing a plurality of bump electrodes for connection with the exterior are formed on the front surface of a parent chip. The front surfaces of the parent chip and child chip are set to face each other with the interposer disposed therebetween and the bump electrodes are electrically connected to one another in the opening of the interposer.

Abstract: A semiconductor package comprises a first package; a second package that is provided on the first package; and a first interconnect that comprises a bump to couple to the first package and a base material layer to cover the bump, wherein the second package is supported on the base material layer that is coupled to the bump.

Abstract: A element group includes a plurality of semiconductor elements stacked in a step-like shape on a wiring board. The semiconductor elements are electrically connect to connection pads of the wiring board through metal wires. Among the plural semiconductor elements stacked in a step-like shape, the uppermost semiconductor element has a thickness larger than that of the semiconductor element immediately below it.

Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Abstract: A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.

Abstract: A semiconductor package includes a bare chip which has a plurality of external electrodes, a land grid array substrate having an edge, a first surface and a second surface. The first surface includes a first portion apart from the edge and a second portion adjacent to the edge. The first portion of the first surface mounts the bare chip and is covered with a resin to seal the bare chip with the resin. The first portion of the first surface and the second surface includes a non-sealed region which is not covered with the resin. A plurality of first electrodes are arranged on the non-sealed region and connected to the external electrodes and a plurality of second electrodes are arranged on the second surface and connected to the external electrodes.

Abstract: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.

Abstract: A module is described having a semiconductor chip which has at least one contact pad. A first dielectric layer, which contains a fluorocarbon compound, as well as a first wiring layer are applied to the semiconductor chip.

Abstract: An embodiment of the present invention provides a method of manufacturing hermetic packaging for devices on a substrate wafer, comprising forming a plurality of adhesive rings on a cap wafer or the substrate wafer, bonding the cap wafer to the substrate wafer with an adhesive layer, forming trenches in the cap wafer and the adhesive rings along outer rim of the adhesive rings, and covering sidewall of the trenches by at least one deposited film to provide a diffusion barrier to moisture or gas.

Abstract: A method and apparatus for fabrication of microelectronic devices are shown. In an embodiment of the invention, a microelectronic device comprises a die, the die comprising a first side, a second side, and an edge; a first plate, the first plate coupled with the die; and a package, the die being coupled with the package.

Abstract: A semiconductor device of the present invention includes a wiring substrate, a plurality of semiconductor chips mounted on the wiring substrate, and a radiation plate arranged over a plurality of semiconductor chips, and having a cooling passage to flow water in a horizontal direction to the wiring substrate. A plurality of semiconductor chips are arranged along the cooling passage, and out of the plurality of semiconductor chips, the semiconductor chip arranged on an inflow side of the cooling passage, has a smaller amount of heat generation than the semiconductor chip arranged on an outflow side of the cooling passage. For example, a memory chip is arranged on the inflow side of the cooling passage, and a logic chip is arranged on the outflow side of the cooling passage.

Abstract: A melting temperature adjustable metal thermal interface material (TIM) and a packaged semiconductor including thereof are provided. The metal TIM includes about 20-98 wt % of In, about 0.03-4 wt % of Ga, and at least one element of Bi, Sn, Ag and Zn. The metal TIM has an initial melting temperature between about 60-144° C.

Abstract: In one embodiment, the present invention is a method and apparatus for chip cooling. One embodiment of an inventive method for bonding a liquid metal to an interface surface (e.g., a surface of an integrated circuit chip or an opposing surface of a heat sink) includes applying an adhesive to the interface surface. A metal film is then bonded to the adhesive, thereby easily adapting the interface surface for bonding to the liquid metal.

Abstract: A voltage regulation module and system for an integrated circuit die. The voltage regulation module includes an interposer situated in a stack between a substrate and the integrated circuit die. The interposer includes a hybrid array of voltage regulation elements for receiving voltage from the power supply and for down-converting the voltage from the power supply into a regulated voltage supplied to the integrated circuit die. The hybrid array of voltage regulation elements includes both high-bandwidth linear regulation elements for providing voltage regulation to areas on the integrated circuit die that intermittently demand relatively high current levels, and low-bandwidth switching regulator elements that are highly power efficient.

Abstract: A microelectronic assembly that includes a first microelectronic element having a first rear surface. The assembly further includes a second microelectronic element having a second rear surface. The second microelectronic element is attached to the first microelectronic element so as to form a stacked package. A bridging element electrically connects the first microelectronic element and the second microelectronic element. The first rear surface of the first microelectronic element faces toward the second rear surface of the second microelectronic element.

Abstract: An interconnect assembly for use in high frequency applications includes an interconnect structure, a plurality of electronic die disposed on the interconnect structure, and an encapsulant at least partially surrounding the plurality of electronic die. The interconnect structure includes a plurality of layers. The interconnect assembly further includes a thermal management layer disposed within a portion of the encapsulant and proximate to the plurality of electronic die and a controlled impedance interconnect connected to the interconnect structure and extending to a peripheral surface of the interconnect assembly.

Abstract: The invention discloses an electrical component with a carrier substrate, on which at least one semiconductor chip is mounted. Terminal areas are arranged on the underside of the carrier substrate and contact areas designed for the assembly with semiconductor chips are arranged on the upper side. The carrier substrate has a functional area that is divided into sections, wherein each section is assigned at least one function such as, e.g., as a filter, a frequency-separating filter, a balun, etc. A separate area of the carrier substrate is assigned to each section. The following applies to at least one of the sections: the contact area and/or the terminal area that is conductively connected to the section lies outside the base of this section. The connecting line that conductively connects the input or output of the respective section to the contact area and/or the terminal area is preferably shielded from the section by a ground area.

Abstract: A BGA package primarily includes a leadless leadframe with a plurality of leads, a chip disposed on the leads, a die-attaching layer adhering to an active surface of the chip and the top surfaces of the leads, a plurality of bonding wires electrically connecting the chip to the leads, an encapsulant, and a plurality of solder balls. Each lead has a bottom surface including a wire-bonding area and a ball-placement area, moreover, a plurality of lips project from the bottom surfaces of the leads around the ball-placement areas. The encapsulant encapsulates the chip, the bonding wires, the die-attaching layer, and the top surfaces, the bottom surfaces except the ball-placement areas. The solder balls are disposed on the ball-placement areas.

Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.

Abstract: A semiconductor device including a chip including an integrated circuit, a conductive layer, a copolymer layer and metal elements. The conductive layer is disposed over the chip and electrically coupled to the integrated circuit. The copolymer is disposed on the conductive layer. The metal elements are electrically coupled to the conductive layer via through-connects in the copolymer layer.

Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract: Methods of forming microelectronic device structures are described. Those methods may include forming a passivation layer on a substrate, wherein the substrate comprises an array of conductive structures, forming a first via in the passivation layer, forming a second via in the passivation layer that exposes at least one of the conductive structures in the array, and wherein the second via is formed within the first via space to form a step via, and forming a conductive material in the step via, wherein a round dimple is formed in the conductive material.

Abstract: An exemplary semiconductor die package is disclosed having one or more semiconductor dice disposed on a first substrate, one or more packaged electrical components disposed on a second substrate that is electrical coupled to the first substrate, and an electrically insulating material disposed over portions of the substrates. The first substrate may hold power-handling devices and may be specially constructed to dissipation heat and to facilitate fast and inexpensive manufacturing. The second substrate may hold packaged components of control circuitry for the power-handling devices, and may be specially constructed to enable fast and inexpensive wiring design and fast and inexpensive component assembly. The first substrate may be used with different designs of the second substrate.

Abstract: A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips.

Abstract: The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.

Abstract: Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.

Abstract: A substrate on which an IC element is fixed includes: a plurality of metal posts arranged in a plurality of columns in a lengthwise direction and in a plurality of rows in a crosswise direction when viewed in a plan view, the plurality of metal posts having first faces and second faces that face an opposite side to a side that the first faces face; first marks each of the first marks being disposed on extending lines of the plurality of columns; and second marks, each of the second marks being disposed on extending lines of the plurality of rows.

Abstract: An integrated circuit package system includes an integrated circuit die, a first controlled bump over the integrated circuit die, a second controlled bump over the integrated circuit die, and a connector between the first controlled bump and the second controlled bump.

Abstract: There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump formed at the other side of the multilayer thin film structure. The multilayer thin film structure functions as the substrate for the semiconductor package and realizes the light, thin, short and small BGA package without any additional substrate. A plurality of the packages can be simultaneously formed at wafer level or carrier level, to simplify the process and to be favorable for mass production.

Abstract: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.

Abstract: Applications of smart polymer composites to integrated circuit packaging.

Abstract: An overlay mark arrangement for reducing the asymmetric profile and an overlay shift during an integrated circuit manufacturing process is disclosed. In one embodiment, the overlay mark arrangement may comprise a first mark, a second mark and a stress releasing means. The first mark is used to indicate the position of a lower layer, the second mark is used to indicate the position of an upper layer; and the stress releasing means is used to release the film stress induced by the upper layer. Unlike the conventional overlay mark arrangements, which will have a severe overlay mark shift due to the film stress, the asymmetric overlay mark profile can be improved by using multiple trenches around the overlay marks according to certain embodiments of the invention disclosed herein.

Abstract: A wind power generation system temporarily stops a power converter when a system disturbance occurs, and reactivates the power converter after detecting a solution of the problem of an influence (overcurrent of a stator, direct current component of a stator, overcurrent of a rotor, etc.) of a fault occurring in a doubly-fed generator during a system fault. During a system fault, a reactive current can be safely output from a doubly-fed generator to an electric power system without destroying equipment of the wind power generation system.

Abstract: To provide a wind turbine generator, a wind turbine generator system, and a power-generation control method of a wind turbine generator that are capable of improving the power-generation capability and reducing the fatigue load on the windmill.

Abstract: A wind turbine generator system can regulate the rotational velocity of the wind turbine within an operation range even when the wind velocity suddenly changes and can perform continuous operation of the wind turbine. The wind turbine generator system includes a generator connected to the shaft of the wind turbine and a converter connected to the generator. When the rotational velocity of the wind turbine is within a predetermined range, power outputted from the generator is controlled so as to follow the instruction concerning the generator output given from the wind turbine to the converter. When the rotational velocity of the wind turbine is out of the predetermined range, the power outputted from the generator is controlled without following the instruction concerning generator output given from the wind turbine to the converter.

Abstract: The invention relates to a wind turbine comprising a rotor including one or more pitchable blades, registration means for registering an idling power producing situation of the wind turbine in relation to a utility grid, detection means for detecting edgewise oscillations in one or more of the blades, and control means for controlling the pitch angle of one or more of the blades. The control means is adapted for changing the pitch angle of one or more of the blades when the registration means registers that the wind turbine is operating in an idling power producing situation and the detection means detects edgewise oscillations in one or more of the blades, hereby damping or eliminating the edgewise oscillations. The invention further relates to a method for controlling a wind turbine and use hereof.

Abstract: A system for generating electricity includes a pump operable to convert wave motion from a body of water into mechanical energy. The pump includes an input port through which an operating fluid can enter the pump and an output port through which the operating fluid can exit the pump. A first outlet line and a second outlet line are fluidly coupled to the output port of the pump. A first reservoir is fluidly connected to the first outlet line, and a second reservoir is fluidly connected to the second outlet line, both reservoirs being selectively capable of receiving operating fluid driven through the output port.