Abstract: The present invention relates to a high-voltage light-emitting device suitable for light-emitting diode chip array module. The device comprises a set of light emitting diode chips, about 18-25 chips, deposited on a substrate by using a non-matrix arrangement. Through the adjustments, the high-voltage light-emitting device of the present invention has optimized luminous efficiency.

Abstract: Disclosed herein is a resist stripping composition, which has an excellent ability of stripping a residual resist remaining after dry or wet etching at the tune of forming patterns in a process of manufacturing a flat panel display substrate.

Abstract: In a light emitting module, a semiconductor light emitting element is mounted on a mounting board. A plated layer is provided on the surface of the mounting board so as to be electrically connected to the semiconductor light emitting element mounted on the mounting board. The plated layer has a power feeding portion and an element connection portion. The power feeding portion extends, of the surfaces of the mounting board, from the upper surface on which the semiconductor light emitting element is to be mounted to a stepped surface located below the upper surface, so that power can be fed, on the stepped surface, to the semiconductor light emitting element. The element connection portions are provided on the upper surface such that a plurality of the semiconductor light emitting elements mounted on the upper surface are connected together in series.

Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes a substrate, a plurality of pixels arranged in a matrix on the substrate where each pixel includes a switching element, a plurality of gate lines that are connected to the switching elements and extend in a row direction, and a gate driver that is connected to the gate lines and is formed on the substrate as an integrated circuit. In the liquid crystal display, the gate driver includes a first region and a second region that is not aligned with the first region.

Abstract: A LED light source has a red, blue and green LED triad for generating a full spectrum of colored light that appears to be emanating from a point source. The LED triad is mounted in a CPC that is surrounded by a cylindrical reflector.

Abstract: Solid state light sources based on LEDs mounted on or within thermally conductive luminescent elements provide both convective and radiative cooling. Low cost self-cooling solid state light sources can integrate the electrical interconnect of the LEDs and other semiconductor devices. The thermally conductive luminescent element can completely or partially eliminate the need for any additional heatsinking means by efficiently transferring and spreading out the heat generated in LED and luminescent element itself over an area sufficiently large enough such that convective and radiative means can be used to cool the device.

Abstract: Disclosed is a light emitting device. The light emitting device includes a light emitting structure comprising a first area comprising a first semiconductor layer doped with a first dopant, a second semiconductor layer doped with a second dopant and a first active layer, and a second area comprising a third semiconductor layer doped with the first dopant and comprising an exposed region, a fourth semiconductor layer arranged on the third semiconductor layer except for the exposed region and doped with the second dopant and a second active layer, and provided with first and second trenche formed from the fourth semiconductor layer to the first semiconductor layer and separated from each other, a first electrode comprising first and second electrode pad, a second electrode, and a third electrode arranged on the fourth semiconductor layer and comprising a third electrode pad, a fourth electrode pad and a fifth electrode pad.

Abstract: A radiation-emitting semiconductor device includes a chip connection region, a radiation-emitting semiconductor chip, and a light-absorbing material, wherein the radiation-emitting semiconductor chip is fixed to the chip connection region, the chip connection region is covered with the light-absorbing material at selected locations at which said chip connection region is not covered by the radiation-emitting semiconductor chip, and the radiation-emitting semiconductor chip is free of the light-absorbing material in locations.

Abstract: A light emitting device (LED) package and a manufacturing method thereof are provided. The LED package may include a package body including a cavity, a first lead frame and a second lead frame that are disposed in the cavity of the package body, and an LED mounted on a bottom surface of the cavity of the package body, the LED including a transparent substrate, a first semiconductor layer, an active layer, and a second semiconductor layer that are laminated sequentially in one of a first direction that is parallel to the bottom surface of the cavity and a second direction that is inclined with respect to the bottom surface of the cavity.

Abstract: This invention discloses a wafer-scaled light-emitting structure comprising a supportive substrate; an anti-deforming layer; a bonding layer; and a light-emitting stacked layer, wherein the anti-deforming layer reduces or removes the deformation like warp caused by thinning of the substrate.

Abstract: An electronic assembly includes a first substrate and a second substrate, a hole through the first substrate, the second substrate having a trace with an indentation, an electronic device mounted over the indentation in the trace, and the first substrate is attached to the second substrate such that the electronic device is positioned within the hole through the first substrate.

Abstract: A lead frame for an optical semiconductor device, having a reflection layer at least on one side or each side of the outermost surface of a substrate, partially or entirely, in which the reflection layer has, on the outermost surface at least in a region where light emitted by an optical semiconductor element is reflected, a microstructure with at least the surface thereof having been mechanically deformed, which is converted from a plating microstructure formed of a metal or an alloy thereof; a method of producing the same, and an optical semiconductor device having the same.

Abstract: A light-emitting device is provided that can extract light in all directions and that has wide directivity. This light-emitting device includes: an elongated bar-shaped package extending sideways, the package being formed such that a plurality of leads are formed integrally with a first resin with part of the leads exposed; a light-emitting element that is fixed onto at least one of the leads and that is electrically connected to at least one of the leads; and a second resin sealing the light-emitting element. In the light-emitting device, the first resin and the second resin are formed of optically transparent resin, and the leads have outer lead portions used for external connection and protruding sideways from both left and right ends of the package.

Abstract: An optoelectronic semiconductor chip includes a semiconductor body, having an n-conducting region and a p-conducting region, and a single n-type contact element, via which the n-conducting region can be electrically contact-connected through the p-conducting region.

Abstract: A wiring substrate includes a substrate, a first insulating layer formed on the substrate, wiring patterns formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer. The second insulating layer covers the wiring patterns and includes a first opening that partially exposes adjacent wiring patterns as a pad. A projection is formed in an outer portion of the substrate located outward from where the first opening is arranged. The projection rises in a thickness direction of the substrate.

Abstract: A heat radiation structure of a light emitting element has leads, each lead having a plurality of leg sections, and a light emitting chip mounted on any one of the leads. The present invention can provide a high-efficiency light emitting element, in which a thermal load is reduced by widening a connecting section through which a lead and a chip seating section of the light emitting element are connected, and the heat generated from a heat source can be more rapidly radiated to the outside. Further, the present invention can also provide a high-efficiency light emitting element, in which heat radiation fins are formed between a stopper and a molding portion of a lead of the light emitting element so that natural convection can occur between the heat radiation fins, and an area in which heat radiation can occur is widened to maximize a heat radiation effect.

Abstract: LED packages and their fabrication techniques are disclosed to provide LED package with improved thermal dissipation based on one or more thermally conductive channels or studs. In one implementation, a LED package includes a plastic body structured to have a hole that penetrates through the plastic body; a metal contact formed on the plastic body at one side of the hole to cover the hole; a LED mounted to the metal contact at a location that spatially overlaps with the hole; and a stud formed in the hole in contact with the metal contact at a first end of the stud and extending to an opening of the hole at a second end of the stud, the stud being formed of a thermally conductive material to transfer heat from the LED through the metal contact and the stud to dissipate the heat at the opening of the hole via the second end of the stud.

Abstract: An object of the invention is to provide an LED light source device and a manufacturing method for the same that can maintain high reflectance over an extended period of time notwithstanding the interaction between light and heat. More specifically, the invention provides an LED light source device that includes a substrate, an electrode formed on the substrate, a white inorganic resist layer deposited over the substrate so as to cover a surface thereof everywhere except where the electrode is formed, and an LED element connected to the electrode, wherein the white inorganic resist layer contains fine white inorganic particles dispersed or mixed into an inorganic binder, and a method for manufacturing such an LED light source device.

Abstract: A method of selective dry etching of N-face (Al,In,Ga)N heterostructures through the incorporation of an etch-stop layer into the structure, and a controlled, highly selective, etch process. Specifically, the method includes: (1) the incorporation of an easily formed, compatible etch-stop layer in the growth of the device structure, (2) the use of a laser-lift off or similar process to decouple the active layer from the original growth substrate, and (3) the achievement of etch selectivity higher than 14:1 on N-face (Al,In,Ga)N.

Abstract: An SCR apparatus includes an SCR structure and a first N injection region. The SCR structure includes a P+ injection region, a P well, an N well and a first N+ injection region, the first N injection region is located under an anode terminal of the P+ injection region of the SCR structure. A method for adjusting a sustaining voltage therefor is provided as well.

Abstract: An exemplary power semiconductor device with a wafer having an emitter electrode on an emitter side and a collector electrode on a collector side, an (n-) doped drift layer, an n-doped first region, a p-doped base layer, an n-doped source region, and a gate electrode, all of which being formed between the emitter and collector electrodes. The emitter electrode contacts the base layer and the source region within a contact area. An active semiconductor cell is formed within the wafer, and includes layers that lie in orthogonal projection with respect to the emitter side of the contact area of the emitter electrode. The device also includes a p-doped well, which is arranged in the same plane as the base layer, but outside the active cell. The well is electrically connected to the emitter electrode at least one of directly or via the base layer.

Abstract: An overvoltage protection devices operable to provide protection against overvoltage events of positive and negative polarity, comprising: an N P N semiconductor structure defining: a first N-type region; a first P-type region; and a second N-type region; wherein one of the first or second N-type regions is connected to a terminal, conductor or node that is to be protected against an overvoltage event, and the other one of the first or second N-type regions is connected to a reference, and wherein a field plate is in electrical contact with the first P-type region, and the field plate overlaps with but is isolated from portions of the first and second N type regions.

Abstract: Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first dielectric layer disposed over the substrate. The semiconductor device further includes a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer. The semiconductor device further includes an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer. The semiconductor device also includes a second dielectric layer disposed over the first dielectric layer and the insulator layer. Further, the semiconductor device includes a fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer.

Abstract: A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device such as, for example, a high electron mobility transistor (HEMT) or metal-insulator-semiconductor field-effect transistor (MISFET), or combinations thereof. The IC device includes a buffer layer formed on a substrate, a barrier layer formed on the buffer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) and gallium (Ga), a cap layer formed on the barrier layer, the cap layer including nitrogen (N) and at least one of indium (In) and gallium (Ga), and a gate formed on the cap layer, the gate being directly coupled with the cap layer. Other embodiments may also be described and/or claimed.

Abstract: According to example embodiments a transistor includes a channel layer on a substrate, a first channel supply layer on the channel, a depletion layer, a second channel supply layer, source and drain electrodes on the first channel supply layer, and a gate electrode on the depletion layer. The channel includes a 2DEG channel configured to generate a two-dimensional electron gas and a depletion area. The first channel supply layer corresponds to the 2DEG channel and defines an opening that exposes the depletion area. The depletion layer is on the depletion area of the channel layer. The second channel supply layer is between the depletion layer and the depletion area.

Abstract: A first GaN layer, a first AlGaN layer, a second GaN layer and a third GaN layer are formed in layers on a substrate. A second AlGaN layer is formed on the sidewall of an opening formed in the multilayer structure. A gate electrode is formed to fill an electrode trench in an insulating film. A portion of the insulating film between the gate electrode and the second AlGaN layer functions as a gate insulating film. A source electrode is formed above the gate electrode and a drain electrode is formed below the gate electrode. This configuration enables implementation of a miniatuarizable, reliable vertical HEMT that has a sufficiently high withstand voltage and high output power and is capable of a normally-off operation without problems that could otherwise result from the use of a p-type compound semiconductor.

Abstract: Embodiments of semiconductor structure are disclosed along with methods of forming the semiconductor structure. In one embodiment, the semiconductor structure includes a semiconductor substrate, a collector layer formed over the semiconductor substrate, a base layer formed over the semiconductor substrate, and an emitter layer formed over the semiconductor substrate. The semiconductor substrate is formed from Gallium Arsenide (GaAs), while the base layer is formed from a Gallium Indium Nitride Arsenide Antimonide (GaInNAsSb) compound. The base layer formed from the GaInNAsSb compound has a low bandgap, but a lattice that substantially matches a lattice constant of the underlying semiconductor substrate formed from GaAs. In this manner, semiconductor devices with lower base resistances, turn-on voltages, and/or offset voltages can be formed using the semiconductor structure.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, in which a shallow trench is formed of a first shallow trench and a second shallow trench vertically joined together in the active region, the second shallow trench being located directly under the first shallow trench and having a width less than that of the first shallow trench; a pseudo buried layer is formed surrounding the bottom and side walls of the second shallow trench and is in contact with the collector region to serve as a connection layer of a collector; a deep hole contact is formed in the shallow trench and is in contact with the pseudo buried layer to pick up the collector. A SiGe HBT manufacturing method is also disclosed. The present invention is capable of improving the cut-off frequency of a SiGe HBT.

Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Abstract: Disclosed is a method for manufacturing a semiconductor device that can improve the performance of a photodiode that is formed on a same substrate as a thin film transistor without greatly deteriorating the productivity of the semiconductor device. On a glass substrate 30, a base layer 31 having a recess 33b on the surface is formed, and on the base layer 31, an amorphous silicon thin film 42 is formed. The amorphous silicon thin film 42 is melted to form a crystalline silicon thin film 43, while moving the molten silicon into the recess 33b. Of the silicon thin film 43, a silicon film 11 that constitutes a portion of a thin film transistor 10 is formed of the silicon thin film 43 in a part other than the recess 33b, while a silicon film 21 that constitutes a portion of a photodiode 20 is formed of the silicon thin film 43 in the recess 33b.

Abstract: A solid-state imaging device includes a first and second pixel regions. In the first pixel region, a photoelectric conversion unit, a floating diffusion region (FD), and a transferring transistor are provided. In the second pixel region, an amplifying transistor, and a resetting transistor are provided. A first element isolation portion is provided in the first pixel region, while a second element isolation portion is provided in the second pixel region. An amount of protrusion of an insulating film into a semiconductor substrate in the first element isolation portion is smaller, than that in the second element isolation portion.

Abstract: A semiconductor substrate of a semiconductor device has a sensor region and an integrated circuit region, and a cavity is formed immediately under a surface layer portion of the sensor region. A capacitive acceleration sensor is formed on the sensor region by working a surface layer portion of the semiconductor substrate opposed to the cavity. The capacitive acceleration sensor includes an interdigital fixed electrode and an interdigital movable electrode. A CMIS transistor is formed on the integrated circuit region. The CMIS transistor includes a P-type well region and an N-type well region formed on the surface layer portion of the semiconductor substrate. A gate electrode is opposed to the respective ones of the P-type well region and the N-type well region through a gate insulating film formed on a surface of the semiconductor substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first doped region and a semiconductor region. The first doped region has a first type conductivity. The semiconductor region is in the first doped region. A source electrode and a drain electrode are respectively electrically connected to parts of the first doped region on opposite sides of the semiconductor region.

Abstract: A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes forming a first dislocation plane adjacent to a gate electrode of the MOSFET, and forming a second dislocation plane adjacent to the gate electrode of the MOSFET. The first and the second dislocation planes are on a same side of the gate electrode, and extend into source/drain regions of the MOSFET.

Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.

Abstract: A device includes a transistor including a source and a drain disposed in a substrate and a gate disposed above the substrate. The gate includes a first longitudinal member disposed above the source and the drain and running substantially parallel to a channel of the transistor. The first longitudinal member is disposed over a first junction isolation area. The gate also includes a second longitudinal member disposed above the source and the drain and running substantially parallel to the channel of the transistor. The second longitudinal member is disposed over a second junction isolation region. The gate also includes a cross member running substantially perpendicular to the channel of the transistor and connecting the first longitudinal member to the second longitudinal member. The cross member is disposed above and between the source and the drain.

Abstract: An electrostatic discharge protection device electrically connected between a pad and an internal circuit is provided and includes a capacitor, a first resistor, a voltage-drop element and an NMOS transistor. A first end of the capacitor is electrically connected to the pad. A first end of the first resistor is electrically connected to a second end of the capacitor, and a second end of the first resistor is electrically connected to ground. The NMOS transistor and the voltage-drop element are connected in series between the pad and the ground, a gate of the NMOS transistor is electrically connected to the second end of the capacitor, and a bulk of the NMOS transistor is electrically connected to the ground.

Abstract: A semiconductor device comprises a buried gate formed in a mat and in an adjacent dummy region. A space larger than is conventional is formed in a dummy region of a mat edge where the buried gate is to be created. This larger space inhibits shortening of an end of a buried gate and reduction in pattern size attributable to lithographic distortion arising between patterned (mat) and unpatterned (dummy) regions. Device reliability is thereby improved by avoiding gap-fill defects of a gate material.

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of times of writing operations. A semiconductor device includes a source-bit line, a first signal line, a second signal line, a word line, and a memory cell connected between the source-bit lines. The memory cell includes a first transistor, a second transistor, and a capacitor. The second transistor is formed including an oxide semiconductor material. A gate electrode of the first transistor, one of a source and drain electrodes, and one of electrodes of the capacitor are electrically connected to one another. The source-bit line and a source electrode of the first transistor are electrically connected to each other. Another source-bit line adjacent to the above source-bit line and a drain electrode of the first transistor are electrically connected to each other.

Abstract: The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an I-shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.

Abstract: A nonvolatile memory device and a method of manufacturing thereof are provided. The method includes forming a floating gate on a substrate, forming a dielectric layer to conform to a shape of the floating gate, forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer, forming a photoresist pattern on one side of the conductive layer, forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate including performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed, and forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad including removing the photoresist pattern.

Abstract: A semiconductor memory device according to embodiment of the present invention includes a tunnel insulating layer formed over a semiconductor substrate, a floating gate formed over the tunnel insulating layer, a dielectric layer formed over the floating gate, and a control gate including a third silicon layer formed over the dielectric layer, a fourth silicon layer formed over the third silicon layer, and a conductive layer formed over the fourth silicon layer, wherein the fourth silicon layer has a greater width than the third silicon layer.

Abstract: A memory and a manufacturing method thereof are provided. A plurality of stacked structures extending along a first direction is formed on a substrate. Each of the stacked structures includes a plurality of first insulating layers and a plurality of second insulating layers. The first insulating layers are stacked on the substrate and the second insulating layers are respectively disposed between the adjacent first insulating layers. A plurality of trenches extending along the first direction is formed in each of the stacked structures. The trenches are respectively located at two opposite sides of each of the second insulating layers. A first conductive layer is filled in the trenches. A plurality of charge storage structures extending along a second direction is formed on the stacked structures and a second conductive layer is formed on each of the charge storage structures.

Abstract: The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.

Abstract: Semiconductor devices having vertical channel transistors are provided. The semiconductor device includes an insulation layer on a substrate and a buried bit line on the insulation layer. The buried bit line extends in a first direction. An active pillar is disposed on the buried bit line. The active pillar includes a lower dopant region, a channel region having a first sidewall and an upper dopant region vertically stacked on the buried bit line. A contact gate electrode is disposed to be adjacent to the first sidewall of the channel region. A word line is electrically connected to the contact gate electrode. The word line extends in a second direction intersecting the first direction. A string body connector is electrically connected to the channel region. Related methods are also provided.

Abstract: A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.

Abstract: A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer in the first gate trench, forming a second work function metal layer in the first gate trench and the second gate trench, forming a first patterned mask layer exposing portions of the second work function metal layer in the first gate trench and the second gate trench, and performing an etching process to remove the exposed second work function metal layer.

Abstract: According to an embodiment, a method of forming a semiconductor device includes: providing a wafer having a semiconductor substrate with a first side a second side opposite the first side, and a dielectric region arranged on the first side; mounting the wafer with the first side on a carrier system; etching a deep vertical trench from the second side through the semiconductor substrate to the dielectric region, thereby insulating a mesa region from the remaining semiconductor substrate; and filling the deep vertical trench with a dielectric material.