Abstract: An apparatus for making directional resistivity measurements of a subterranean formation includes a resistivity tool body with a longitudinal axis and an outer surface, a first antenna with two open ends deployed below the outer surface, a second antenna deployed below the outer surface and spaced at an axial distance from the first antenna, and at least one slot formed on the outer surface. A corresponding method for making directional resistivity measurements includes rotating a resistivity tool in a borehole, utilizing a transmitter-receiver antenna group formed in the resistivity tool to process an electromagnetic wave, and computing a resistivity-related measurement from the electromagnetic wave received on the receiver antenna.

Abstract: Procedures are described for monitoring dynamics along a drill string during the drilling process using only surface instrumentation or using a combination of surface and downhole instrumentation. Events such as drill collar whirl may be identified from signatures found in signals generated by an electromagnetic sensor such as a magnetometer and/or from a mechanical sensor such as accelerometer. Additional embodiments are described.

Abstract: There is provided a storage battery deterioration diagnosis system, including: a cell-list creator configured to select diagnosis target cells from among a plurality of cells in a storage battery system, and create a list of the diagnosis target cells; a cell deterioration diagnoser configured to obtain degradation degrees of the diagnosis target cells; a temperature distribution estimator configured to estimate degradation degrees of non-target cells other than the diagnosis target cells, based on a distance between the non-target cell and the diagnosis target cells, and obtain temperature distribution of a whole of the plurality of cells based on degradation degrees of the diagnosis target cells and the degradation degrees of the non-target cells; and a cell-list updater configured to update the list of the diagnosis target cells based on the temperature distribution.

Abstract: A protective semiconductor apparatus for protecting an assembled battery including N secondary cells connected in series includes a disconnection detecting circuit including, for each of the N secondary cells, a voltage-sensing resistor dividing a voltage of a corresponding one of the secondary cells, a reference voltage, and a first comparator comparing a voltage obtained by the voltage-sensing resistor with the reference voltage. The protection semiconductor apparatus also includes a circuit connecting an internal resistor having a resistance value smaller than a resistance value of a corresponding one of the voltage-sensing resistors in parallel to the corresponding voltage-sensing resistors successively and selectively at predetermined time intervals.

Abstract: The present invention relates to a chuck mechanism of a charge-discharge test device for a thin secondary battery, and aims to provide a chuck mechanism having excellent action controllability. The chuck mechanism includes: a chuck drive part which is movable in a direction toward a battery container housing a thin secondary battery; and a chuck activation part which is located away from the chuck drive part in the direction toward the battery container and whose movement in the same direction is restricted. In the chuck mechanism, when the chuck unit is moved in the direction toward the battery container, the chuck drive part activates a chuck member of the chuck activation part whose movement in the same direction is restricted.

Abstract: Fail-safe systems and design methodologies for large capacity battery systems are disclosed. The disclosed systems and methodologies serve to locate a faulty cell in a large capacity battery, such as a cell having an internal short circuit, determine whether the fault is evolving, and electrically isolate the faulty cell from the rest of the battery, preventing further electrical energy from feeding into the fault.

Abstract: Testing integrity of electrical connections between cardiac resuscitation devices and electrodes connected thereto while the electrodes remain stored within a sealed package. Each electrode comprises a skin-contacting gel layer, a current-spreading layer, and an adhesive layer for adhering the electrode to the patient. An electrical lead for delivering a therapy pulse extends from the current-spreading layer of each electrode to the exterior of the package. A jumper element located within the package and connected to the current-spreading layer of each electrode provides a self-test electrical connection between the first and second electrical leads while the electrodes are adhered to a substrate within the package to permit testing the integrity of the electrical connection between the electrodes and cardiac resuscitation device prior to use of the electrodes. The jumper is configured so that the self-test electrical connection is broken when the user removes the electrodes from the substrate.

Abstract: A fault position analysis method and a fault position analysis device for a semiconductor device, through which a fault position of a SiC semiconductor device can be analyzed and specified by an OBI RCH method, are disclosed. The fault position analysis method for the semiconductor device scans and irradiates a device and a circuit on a front surface of a substrate with a laser beam from a rear surface side of the substrate of the semiconductor device to heat the device and the circuit. It causes a current to flow to the device and the circuit while being heated, detects a change in a resistance value caused by a change in a current, and analyzes the fault position. The semiconductor device is a semiconductor device which uses an N-doped SiC substrate. Laser beams having wavelengths of 650 to 810 nm are used.

Abstract: A test device with uninterruptible power supply supplies external power to a product under test (PUT) and performing electric power tests thereon. The PUT has a processing unit, a power input end, a battery connection end, and a charging and discharging circuit. The device includes a first test port, a second test port, and a power-storing unit. The PUT is electrically connected to the first and second test ports to receive the external power through the first test port and be switchable to the second test port to selectively receive power from the power-storing unit, thereby preventing interruption of operation of the PUT. A charging voltage from the charging and discharging circuit is applied to the power-storing unit via the second test port to charge the power-storing unit. An operation-required power level of the PUT can be maintained, even if the test device receives no power.

Abstract: A method and apparatus for determining planar impedance tomography of a sample comprising a measurement head unit comprising an impedance sensor; a three-axis actuator assembly, coupled to the measurement head unit, for positioning the impedance sensor relative to a sample; a controller, coupled to the three-axis actuator assembly, for controlling the three-axis actuator assembly to position the impedance sensor at a plurality of locations relative to the sample; and an impedance analyzer, coupled to the impedance sensor, for determining an impedance value at each location in the plurality of locations.

Abstract: A fill-level measuring device for ascertaining and monitoring fill level of a medium located in the process space of a container by means of a microwave travel time measuring method. The device comprises a measurement transmitter and an antenna unit, which is constructed at least of a hollow conductor and a radiating element A microwave transmissive, process isolating element is inserted for process isolation into the hollow conductor between the measurement transmitter and the horn shaped radiating element contacting the process space.

Abstract: A distance measuring apparatus for detecting the position of a reflection body in a line structure is provided that includes a sensor device, which has at least one antenna for feeding a transmission signal as an electromagnetic wave into the line structure and for receiving the electromagnetic wave reflected on the reflection body. The sensor device also includes evaluation electronics which are configured to determine the position of the reflection body from the phase difference between the transmitted and the received wave.

Abstract: In one embodiment, an apparatus includes a touch sensor with one or more meshes of conductive material. Each of the meshes includes multiple mesh cells defined by multiple mesh segments. Each of the mesh cells includes a centroid and multiple vertices. The mesh segments are made of the conductive material, and the centroids or vertices of the mesh cells have a substantially random distribution within an area of the touch sensor. The apparatus also includes one or more computer-readable non-transitory storage media coupled to the touch sensor that embody logic that is configured when executed to control the touch sensor.

Abstract: The invention relates to a method and device for measuring the location of a particle beam (10) present in packets in a linear accelerator comprising a hollow chamber structure (4) in which an electromagnetic wave oscillating at a base frequency (f0) is generated in order to accelerate the particles, wherein an electrical measurement signal (M) generated by the particle beam (10) by means of electromagnetic interaction with the measurement recorder (16) is recorded by at least one measurement recorder (16) disposed in the hollow chamber structure (4), said signal being a function of the distance between the measurement recorder (16) and the particle beam (10). According to the invention, the measurement signal (M) is analyzed in a frequency range different from the base frequency (f0) and higher natural frequencies of the hollow chamber structure (4), comprising a whole multiple of the base frequency (f0).

Abstract: A vehicle door handle apparatus is provided with a handle main body formed by coupling a first cover and a second cover and a capacitance sensor accommodated in a hollow space in the handle main body. One of the first cover and the second cover is formed with an accommodation recess defined by partition walls. The capacitance sensor is accommodated in the accommodation recess and fixed by a potting agent.

Abstract: Present invention concerns generally to a sensor or a sensor system for detecting spilling of aqueous liquids, for instance in confined spaces were such is critical such in an airplane. The system of present invention is an early warning system or sentinel for the prevention of corrosion by corrosive liquids. Corrosion caused by corrosive liquids can rapidly change the surface properties of components in engineering structures, and that will finally endanger the functionality of structural parts. However, if monitoring technologies are in place providing continuous information on the presence of corrosive liquids, corrosion treatment and even corrosion prevention can start at a very early stage. Present invention provides such by early detection of corrosive liquids by extended sensors based on the collapse of percolation conductivity (COPC).

Abstract: A system for sensing human activity by monitoring impedance includes a signal generator for generating an alternating current (AC) signal, the AC signal applied to an object, a reactance altering element coupled to the AC signal, an envelope generator for converting a returned AC signal to a time-varying direct current (DC) signal, and an analog-to-digital converter for determining a defined impedance parameter of the time-varying DC signal, where the defined impedance parameter defines an electromagnetic resonant attribute of the object.

Abstract: The present invention relates to voltage measurement apparatus. The voltage measurement apparatus comprises a potential attenuator configured to be electrically connected between first and second conductors, which are electrically coupled to a source. The potential attenuator comprises a first impedance and a reference impedance arrangement in series with each other. The reference impedance arrangement has an electrical characteristic which is changed in a known fashion. The voltage measurement apparatus further comprises a processing arrangement configured: to acquire at least one signal from the reference impedance arrangement, the at least one signal reflecting change of the electrical characteristic in the known fashion; and to determine a voltage between the first and second conductors in dependence on the fashion in which the electrical characteristic is changed being known and the at least one signal.

Abstract: Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal.

Abstract: A temperature control system for IC tester, comprising: a test socket; a compressing device including a heat exchanger and a thermoelectric cooler (TEC); and a test head having a temperature sensor. The test head is configured at the front end of the compressing device such that, upon placing at least one device under test (DUT) onto the test socket, the test head coerces tightly one of the DUTs through downward pressure from the compressing device thereby allowing the temperature sensor to detect the surface temperature of the DUT to obtain a temperature signal, and then feed such a temperature signal back to a control processing unit for operations to generate a linear control signal thus that, through the control of the linear control signal, the heat absorption and heat discharge functions of the TEC are enabled to further control the temperature of the DUT within a determined range.

Abstract: An apparatus for providing modulation mapping is disclosed. The apparatus includes a laser source, a motion mechanism providing relative motion between the laser beam and the DUT, signal collection mechanism, which include a photodetector and appropriate electronics for collecting modulated laser light reflected from the DUT, and a display mechanism for displaying a spatial modulation map which consists of the collected modulated laser light over a selected time period and a selected area of the IC.

Abstract: A DC-AC probe card for testing a DUT includes: a plurality of probe needles, each probe needle having a distal end for contacting said DUT; and a plurality of connection pathways operable to connect test instrumentation to the probe needles, wherein each connection pathway provides both a desired characteristic impedance for AC measurements and a guarded pathway for DC measurements between respective test instrument connections and probe needles.

Abstract: The present invention provides a probe block, which comprises 1) a conductive base on which a first groove is formed, 2) a pair of signal transmitting probes which have dielectric covers and are placed parallel to each other in the first groove, and 3) a ground probe which is in contact with the conductive base, wherein front portions of the signal transmitting probes and the ground probe protrude from the conductive base to form signal transmitting probe needles and a ground probe needle, respectively. The probe block of the present invention has excellent high frequency responses characteristics and is easy for maintenance.

Abstract: A semiconductor package testing apparatus and testing a semiconductor package, the apparatus including a test circuit substrate that electrically tests a semiconductor package having connection terminals; a socket electrically connecting the test circuit substrate with the semiconductor package; a socket guide having an open region delimiting the socket; an insert that fixes the semiconductor package and positions the semiconductor package in the open region of the socket guide; a pusher that presses the semiconductor package to make contact between the socket and the semiconductor package; and an alignment part that aligns the semiconductor package with the open region, wherein the alignment part is configured to selectively apply a magnetic force to align keys of the semiconductor package, the align keys being formed of a magnetic material.

Abstract: A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

Abstract: An impedance control circuit includes a first impedance unit configured to terminate an impedance node using an impedance value that is determined by an impedance control code, a second impedance unit configured to terminate the impedance node using an impedance value that is determined by an impedance control voltage, a comparison circuit configured to compare a voltage level of the impedance node and a voltage level of a reference voltage, generate an up/down signal indicating whether the voltage at the impedance node is greater than the reference voltage, and generate the impedance control voltage that has a voltage level corresponding to a difference between the voltage at the impedance node and the reference voltage, and a counter unit configured to increase or decrease a value of the impedance control code in response to the up/down signal.

Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

Abstract: An impedance control circuit includes a pull-up code generator configured to generate pull-up impedance control codes using a voltage of a first node, a pull-up impedance unit configured to pull-up-drive the first node in response to the pull-up impedance control codes, a plurality of dummy impedance units enabled in response to respective select signals and each configured to pull-up-drive a second node in response to the pull-up impedance control codes, a pull-down code generator configured to generate pull-down impedance control codes using a voltage of the second node, and a plurality of pull-down impedance units enabled in response to the respective select signals and each configured to pull-down-drive the second node in response to the pull-down impedance control codes.

Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.

Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.

Abstract: A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively.

Abstract: A semiconductor device includes: a main driving unit configured to receive an output data and to drive the received data to a data output pad; a pre-emphasis data generation unit configured to compare a delayed data obtained by delaying the output data by one data period with the output data, to delay the comparison result by one data period, and to output the delayed data as pre-emphasis data; and a pre-emphasis driving unit configured to receive the pre-emphasis data and to drive the received data to the data output pad.

Abstract: Pre-Charge Static Logic (PCSL), is an asynchronous-logic Quasi-Delay-Insensitive architecture based on Static-Logic, featuring fully-range Dynamic Voltage Scaling including robust operation in the sub-threshold voltage regime, with simultaneous low hardware overheads, high-speed and yet low power dissipation. The invented PCSL logic circuit achieves this by integration of the Request sub-circuit into the Static-Logic cell. During the initial phase, the output of Static-Logic cell (within the PCSL logic circuit) is pre-charged. During the evaluate phase, the Static-Logic cell computes the input and the PCSL logic circuit outputs the computation.

Abstract: A semiconductor device includes a main driving unit configured to serialize first and second data applied in parallel and output the serialized data to a data output pad, and an auxiliary driving unit configured to drive the data output pad in a period when the first and second data have different logic levels.

Abstract: An output buffer includes a pullup driver, a pulldown driver, and an output stage. The pullup driver has a drive control input, and an output for providing a pullup drive signal in a push-pull mode in response to receiving a first drive control signal on the drive control input, and in a current limited mode in response to receiving a second drive control signal on said drive control input. The pulldown driver has a drive control input, and an output for providing a pulldown drive signal in the push-pull mode in response to receiving a third drive control signal on the drive control input, and in the current limited mode in response to receiving a fourth drive control signal on the drive control input. The output stage provides a voltage on an output terminal in response to the pullup and pulldown drive signals.

Abstract: A semiconductor device includes a first internal terminal, a first transistor, a second transistor, an oscillator including an output terminal to output a clock signal, and a comparator coupled to a first internal terminal, and that compares a potential of the first internal terminal when the first internal terminal is coupled to the first reference potential with a potential of the first internal terminal when the first internal terminal is coupled to a second reference potential, an external terminal being connectable to the first internal terminal, and a second internal terminal being coupled to the external terminal, and that receives an input signal through the external terminal. Each of the first control terminal and the second control terminal is coupled to the output terminal to commonly receive the clock signal. The first transistor and the second transistor exclusively operate according to the clock signal.

Abstract: A control signal generation circuit which generates a control signal for controlling a gate of an MOS transistor, comprises a first switching part connected to a current source and the gate and controlled based on an input signal; and a second switching part connected to the current source and the gate and controlled based on an input signal and control signal, wherein a voltage value of the control signal changes based on the input signal, and a slant of the voltage value with respect to time is switched to become smaller after the voltage value exceeds a threshold voltage of the MOS transistor compared with when the voltage value equals to or less than the threshold voltage of the MOS transistor.

Abstract: This invention relates to a clock circuit for providing an electronic device with a clock signal having an adjustable clock frequency. The clock circuit is adapted to receive information regarding a context level of the electronic device and to dynamically control the clock frequency of the clock signal according to the context level. The dynamical control of the clock circuit output frequency based on the context level enables automated power-to-performance control of the electronic device. The invention also relates to an electronic device comprising a context setting unit adapted to set a context level in which the electronic device is operated and a clock circuit. Furthermore, it relates to a method of providing an electronic device with a clock signal having an adjustable clock frequency, wherein a clock circuit receives information regarding a context level of the electronic device; and wherein the clock circuit dynamically controls the clock frequency of the clock signal according to the context level.

Abstract: The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancelation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancelation technique to reduce phase noise introduced by the MMD.

Abstract: A signal generator for coupling to a concealed conductor including a first oscillator configured to generate a first waveform having a first frequency, a first terminal coupled to the first oscillator through a first band pass filter configured to pass signals of the first frequency, a second oscillator configured to generate a second waveform having a second frequency, and a second terminal coupled to the second oscillator through a second band pass filter configured to pass signals of the second frequency.

Abstract: A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator.

Abstract: An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available.

Abstract: A power control device is provided. The power control device includes a power supply unit, a reset unit, and a power control unit. The power supply unit determines whether a supplied voltage from an external voltage supply source is being provided to the power supply unit to generate a determination signal. The power supply unit further generates an operation voltage and a standby voltage according to the supplied voltage. The reset unit receives the determination signal and the standby voltage and generates a reset signal according to the determination signal and the standby voltage to activate a reset operation. The power control unit receives the reset signal and generates a power enabling signal according to the reset signal. The power supply unit outputs the operation voltage or does not according to the power enabling signal.

Abstract: A temperature compensated frequency reference comprising first MEMS oscillator (MEMS1) used as frequency reference oscillator (REF) for phase locked loop, and means for temperature compensation of phase locked loop output frequency (Fout), wherein the phase locked loop comprises a second MEMS oscillator (MEMS2) used as electronically controlled oscillator (VCO) of phase locked loop.

Abstract: A clock data recovery circuit which has a high degree of jitter tolerance and can alleviate increase in the phase number of a multi-phase clock, power consumption, and a semiconductor chip area is provided. Each circuit of plural edge detection circuits comprises a first edge detection circuit and a second edge detection circuit. The first detection circuit detects that a data edge leads in phase more than ?1 phase from an edge detection phase, the second detection circuit detects that the data edge laggs in phase more than +1 phase from the edge detection phase. In response to the first output signal or the second output signal, the edge detection phase is changed by the amount of ?1 phase or +1 phase. When the data edge is detected in the range of ±1 phase, a next edge detection phase is maintained in the current state.

Abstract: A communications device is disclosed that adjusts a target signal to allow a reference phase locked loop (PLL) to lock onto a reference signal that is related to a desired operating frequency in a first mode of operation. The reference PLL locks onto the reference signal when the target signal is calibrated to be proportional to the reference signal. As the communications device transitions between the first mode of operation and a second mode of operation, the communications device performs a shorten calibration cycle on the reference PLL. The reference phase locked loop (PLL) locks onto the reference signal in response to the shorten calibration cycle in the second mode of operation.

Abstract: The present disclosure is directed to a fractional-N digital phase locked loop (DPLL) that replaces the conventionally used time-to-digital converter (TDC) based phase detector with a bang-bang phase detector (BBPD). Compared to the TDC based phase detector, the BBPD has an often superior resolution for the same or similar amount of power and/or area consumption. Therefore, replacing the TDC based phase detector with a BBPD can reduce, or even eliminate, the common problem of spurs being added to the output signal generated by the DPLL because of the limited resolution of the TDC based phase detector. This can allow the DPLL to be used for the most demanding applications, such as in generating local oscillator signals for down-converting and demodulating weak signals received by a communication device, such as a cellular phone.

Abstract: A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.

Abstract: A device and a method for eliminating transitions in discrete signals. The working of the device and method is based on allowing the charge of a capacitor with one state when the state opposite the state to which it has been assigned is produced and allowing their discharge through a corresponding capacitor when their state is active. The signal is advantageously consolidated without needing processors or programmes, is very simple, there is increased reliability, and the device can very easily be integrated in any sensor, such as those used in aircraft.

Abstract: A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output.