Abstract: An automated EL CID inspection technique for the stator core of an electrical machine is provided. The inspection device includes a rail, a pickup coil and a coil support assembly. The coil support assembly includes a first part movable along the rail, and a second part where the pickup coil is actually installed. The second part is movable jointly with the first part along the rail, while also being movable relative to the first part in a direction towards or away from the stator core. A motor actuates a motion of the coil support assembly. During inspection, the motor is activated, upon which the coil support assembly moves along the rail while a specified distance is maintained between the stator core and the pickup coil by the relative motion between the first and second parts. The technique is particularly applicable in a step-iron portion of the stator core.

Abstract: A hysteresis-based logic element design for improved soft error rate with low area/performance overhead. In one embodiment, a hysteresis inverter block including one or more pairs of inverters can be coupled to a logic element to adjust a switching threshold of the logic element.

Abstract: Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.

Abstract: An impedance calibration device includes: a variable impedance, an operational unit, an analog-digital converter, and a controller. The operational unit receives a first analog signal and a second analog signal, and performs a difference operation to generate an output voltage. The analog-digital converter generates an adjustment code according to the output voltage. The controller is coupled to the analog-digital converter and the variable impedance, and adjusts a resistance value of the variable impedance according to the adjustment code.

Abstract: A hybrid IO cell for use with controlled collapse chip connection, wirebond core limited, wirebond IO limited, and wirebond inline chip designs is provided. A method of designing the hybrid IO cell includes designating a technology, determining a minimum pad width of the technology, and determining a minimum pad spacing of the technology. The method also includes determining a width of the hybrid IO cell based on the minimum pad width and the minimum pad spacing, setting a length of the hybrid IO cell equal to the determined width, and storing a definition of the IO cell in a library stored on a computer useable storage medium.

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included.

Abstract: The asynchronous circuit includes a fork having at least two branches, each branch being connected to a logic gate so that the logic gate receives as input a branch-ending signal. It further includes a circuit for branching the branch-ending signal at the level of each logic gate to form a branched signal, and a blocking circuit comprising a Muller gate and receiving as input at least one branched signal, the blocking circuit being configured to prevent the propagation of an output signal when the branch-ending signals are in different logic states.

Abstract: A clock-delayed domino logic circuit includes a first pre-charge circuit configured to pre-charge a first dynamic node with a pre-charge voltage in response to a first clock signal received via a first control terminal during a pre-charge operation; a first logic network configured to determine a logic level of the first dynamic node in response to first input data signals during an evaluation operation; and a first storage circuit which is connected between the first control terminal and the first dynamic node.

Abstract: An output buffer including a P-type transistor, an N-type transistor, a first comparison unit and a second comparison unit is provided. The P-type transistor has a first source, a first gate and a first drain. The first source receives a system voltage, and the first drain outputs an output voltage. The N-type transistor has a second drain, a second gate and a second source. The second drain is coupled to the first drain, and the second source receives a ground voltage. The first comparison unit and the second comparison unit respectively output a high voltage or a low voltage to the first gate and the second gate according to a comparison result of an input voltage and the output voltage, and respectively regulate a first tail current flowing into the first comparison unit and a second tail current flowing from the second comparison unit accordingly.

Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.

Abstract: A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.

Abstract: Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.

Abstract: A phase synchronization circuit for AC voltage includes an optical phase detection unit that outputs a phase detection signal by detecting an externally provided first AC voltage; a power failure detection unit that outputs a power failure signal by detecting the power failure condition of the first AC voltage; a control unit that selectively activates a selection signal according to the control of the power failure detection signal and outputs a phase control signal according to the control of the phase detection signal; a second AC voltage generation unit that generates a second AC voltage to have the same phase of the first AC voltage when outputting a second AC voltage according to the control of the phase control signal; and a selection unit that outputs either the first AC voltage or the second AC voltage according to the control of the selection signal.

Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.

Abstract: An input receiver includes a first input receiving unit, a second input receiving unit, a delay unit, and a first logic unit. The first input receiving unit receives an inverse wake-up signal, an external clock enable signal, a first voltage, and a reference signal, and then generates a first enable signal according to the external clock enable signal and the reference signal. The second input receiving unit receives the external clock enable signal, the first voltage, and an inverse enable voltage, and then generates a second enable signal as its output according to the external clock enable signal. The delay unit generates a wake-up signal according to the second enable signal. The first logic unit receives the wake-up signal and the first enable signal, and then generates an internal clock enable signal according to the wake-up signal and the first enable signal.

Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

Abstract: A boosting circuit is provided which performs an appropriate boosting operation in accordance with load capacitance. In the boosting circuit, a slope control circuit is provided between a limiter circuit, which limits a high voltage obtained by a charge pump circuit to a desired boosted voltage VPP, and a discharge circuit, which makes the boosted voltage VPP drop quickly to a power supply voltage VCC after the completion of writing, to enable a boosting operation in an appropriate boosted-voltage reach time, by increasing the time taken to reach the boosted voltage VPP in the case where the load capacitance is low, while keeping the time taken to reach the boosted voltage VPP unchanged, irrespective of the presence/absence of the slope control circuit, in the case where the load capacitance is high as in the case of selecting the memory cells collectively.

Abstract: A PWM duty cycle converter includes a PWM signal generator, a timing signal generator, a limit signal generator, and a duty cycle limiter. The PWM signal generator generates a first PWM signal by comparing a triangular carrier wave with a duty command from a signal source. The timing signal generator generates a timing signal synchronously with at least one of a maximum value and a minimum value of the amplitude of the carrier wave. The limit signal generator generates a limit signal in response to the timing signal. The limit signal sets at least one of an upper limit and a lower limit on a duty cycle of the first PWM signal. The duty cycle limiter combines the first PWM signal and the limit signal to output a second PWM signal having a limited duty cycle.

Abstract: A delay measuring circuit includes a first trigger-signal generating unit that, when a value of a signal input to a circuit under test, changes, generates a first trigger signal. The delay measuring circuit includes a second trigger-signal generating unit that, when a value of a signal output from the circuit under test changes, generates a second trigger signal. The delay measuring circuit includes a delay unit that includes a plurality of delay elements connected in series. The delay measuring circuit includes a delay information retaining unit that individually captures and retains the first trigger signal output from each of the delay elements included in the delay unit between when the first trigger signal is generated by the first trigger-signal generating unit and when the second trigger signal is generated by the second trigger-signal generating unit.

Abstract: A physical unclonable function is provided 100, comprising a plurality of bus-keepers 110, each bus-keeper of the plurality of bus-keepers 110 being configured to settle into one of at least two different stable states upon power-up, the particular stable state into which a particular bus-keeper of the plurality of bus-keepers settles being dependent at least in part upon the at least partially random physical characteristics of the particular bus-keeper, and a reading circuit 120 for reading the plurality of stable states into which the plurality of bus-keepers settled after a power-up, the plurality of bus-keepers being read-only.

Abstract: A circuit that supplies a clock signal to a load having a clock input section capable of suppressing power consumption is disclosed. A clock generating section generates a clock signal having an amplitude corresponding to an absolute value of an electric potential difference between a lower limit of a high-level input voltage VIH and an upper limit of a low-level input voltage VIL in a load having a clock input section; a level shift section shifts an electric potential while maintaining the amplitude of the clock signal so that a high-level electric potential of the clock signal is not less than the lower limit of the high-level input voltage VIH and a low-level electric potential of the clock signal does not exceed the upper limit of the low-level input voltage VIL, and a clock signal whose electric potential is shifted is supplied to the clock input section.

Abstract: An implementation relates to compensating DC offset in a signal path. The signal path may have a plurality of stages, where for each stage a fine DC compensation is performed by introducing a fine DC compensation signal into the signal path of the stage by way of a compensation analog to digital converter.

Abstract: This document discusses, among other things, methods for controlling a Rail-to-Rail enabling signal, including providing a first signal of an input signal of a control circuit to a level switching circuit, performing, by the level switching circuit, enabling control according to a high level and a low level of the first signal, and outputting, by the level switching circuit, a disabling signal in case of a failure of a power supply coupled to the level switching circuit. The document also discusses a circuit for controlling a Rail-to-Rail enabling signal and a level switching circuit configured to output a disabling signal properly to provide an accurate enabling control signal for equipment operated under control of an enabling control in case of the failure of the power supply.

Abstract: A circuit for providing a DC output equal to the RMS value of a time-varying input signal, the circuit including: (i) an RMS-to-DC converter for producing the DC output and (ii) a high-order low-pass filter comprising at least first and second low-pass filters connected in series to cooperatively reduce at least one of ripple in the DC output, ripple in an denominator feedback loop, or DC error in the DC output.

Abstract: A circuit includes first to third nodes, resistors with different resistance, capacitors with different capacitance, first switches corresponding to the same number of resistors, second switches corresponding to the same number of capacitors, and a third switch. A first terminal of each resistor is connected to the first node. A second terminal of each resistor is connected to a first terminal of a corresponding one first switch, a second terminal of each first switch is connected to the second node. A first terminal of the third switch is connected to the second terminal of each first switch. A second terminal of the third switch is connected to a first terminal of each capacitor. A second terminal of each capacitor is connected to a first terminal of a corresponding one second switch. A second terminal of each second switch is connected to the third node.

Abstract: Each of a plurality of redundantly formed semiconductor circuits integrally has a monitor transistor and is energized by being supplied with an enable signal. A monitor circuit associated with each semiconductor circuit detects a collector current of the monitor transistor and, when the collector current is less than a predetermined threshold value, outputs an alarm signal. A variation predicting circuit calculates the rate of change per unit time with respect to the collector current. An order determining circuit stores the identification numbers of the semiconductor circuits into an order determination register in descending order of the rate of change. The order determination register initially outputs the front identification number, and thereafter outputs the respective following identification number each time a respective one of the monitor circuits outputs an alarm signal.

Abstract: A switching-element drive circuit that is configured to be applied to a power converter includes: a switching element; and a control unit that controls an operation of the switching element. The control unit includes a drive-voltage control unit that is configured to be capable of changing a switching speed of the switching element based on a power supply current.

Abstract: A solid state relay and method for enabling and disabling power to a load are disclosed. A fast turn-on circuit and fast turn-off circuit receive control signals in an isolated manner. The control signals allow only one of the fast turn-on circuit and fast turn-off circuit to be enabled at a time. A power switching circuit that enables power to be supplied to a load when the fast turn-on circuit is enabled and the fast turn-off circuit is disabled state, and disables the power from being supplied to the load when the fast turn-on circuit is disabled and the fast turn-off circuit is enabled. A power supply circuit provides isolated power used by the fast turn-on and fast turn-off circuits to drive or discharge a gate in the power switching circuit.

Abstract: For thermal compensation for an intrinsic element in a system, a circuit and method are proposed to predict the temperature variation caused by power loss of the intrinsic element, in addition to sense the external environment temperature variation of the intrinsic element, and thus sense the operational temperature of the intrinsic element more precisely.

Abstract: A voltage reference is produced from PTAT, CTAT, and nonlinear current components generated in isolation from each other and combined to create the voltage reference.

Abstract: A sensor arrangement for detection of proximity and/or touching including least one sensor supporting surface having a first flat face and a second flat face, a proximity and/or touching sensor which is connected to the first flat face and/or to the second flat face of the sensor supporting surface, a decoration supporting medium with a first support flat face and a second support flat face, a decoration layer which is connected to the first support flat face and/or to the second support flat face of the decoration supporting medium, and/or is an integral component of the decoration supporting medium. In this case, the sensor supporting surface and the decoration supporting medium are connected to one another such that a connection along their mutually facing flat face and support flat face is not formed, or is partially formed.

Abstract: Motor drives, signal conditioning systems and configurable circuit boards are presented in which diode blocking circuits are provided for contemporaneous opening of programming fuses in multiple programmable impedance circuits using a single configuration input signal during manufacturing and for mitigating interference between impedance circuits during system operation.

Abstract: A pixel of an image sensor includes only two signal lines per pixel, a pinned photodiode for sensing light, a floating base bipolar transistor, and no reset and address transistors. The floating base bipolar transistor provides the pixel with a gain, which can increase pixel sensitivity and reduce noise. The pixel also incorporates a vertical blooming control structure for an efficient blooming suppression. The output terminals of the pixel are coupled to a common column output line terminated by a special current sensing correlated double sampling circuit, which is used for subtraction of emitter leakage current. Based on this structure, the pixel has high sensitivity, high response uniformity, low noise, reduced size, and efficient layout.

Abstract: An embodiment apparatus comprises a switched capacitor network coupled between an input voltage and an output capacitor and a feedforward controller. The switched capacitor network comprises a plurality of flying capacitors and a switching circuit. The feedforward controller comprises a sensor configured to detect the input voltage and a mode selector configured to generate a plurality of gate drive signals for the switched capacitor network. The gate drive signals configure the switched capacitor network to form a charge pump with a non-integer multiplication factor.

Abstract: A charge pump comprises, a plurality of branches each having serially-connected T-circuit cells, wherein each of the branches has a first end for receiving an input voltage and a second end for outputting a charge pump voltage, wherein each of the T-circuit cells comprises a first transistor, a second transistor, and a capacitor, wherein the first transistor and the second transistor of each of the T-circuit cells have a common drain, and wherein the gate of the first transistor of a certain one of the T-circuit cells of a certain branch is connected to a first branch and the gate of the second transistor of the certain one of the T-circuit cells of the certain branch is connected to a second branch.

Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

Abstract: A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding, reference source without any substantial affect upon its full scale output.

Abstract: A semiconductor integrated circuit apparatus includes: a plurality of column select signal lines extended in parallel to each other with a predetermined distance provided therebetween; a local I/O line arranged in a selected space among spaces formed between the respective column select signal lines; and an upper segment I/O line arranged to overlap the local I/O line and a local I/O line bar.

Abstract: A control circuit for a power converter is disclosed, having a shared pin, a driving circuit, a current source, a sampling circuit, and a signal processing circuit. The shared pin is used for coupling with an output end of the power converter through a resistor. The driving circuit is used for conducting a switch of the power converter. The current source provides a current to the resistor through the shared pin. The sampling circuit samples the signal on the shared pin for generating a first sampling value and a second sampling value. When the difference between the first sampling value and the second sampling value is less than a predetermined value, the signal processing circuit configures the driving circuit to adjust at least one of the conduction time and the conduction frequency of the switch according to an output signal of the power converter received from the shared pin.

Abstract: An equivalent circuit includes: a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; a second transistor having a second gate electrode, a second drain electrode, and a second source electrode electrically connected to the first drain electrode; and a charging and discharging circuit which includes a first capacitor having a terminal electrically connected to the second gate electrode and another terminal electrically connected to the second source electrode, and charges and discharges the first capacitor with predetermined time constants.

Abstract: According to one embodiment, a time difference amplifier circuit includes the first amplifier including first positive and negative inputs and first positive and negative outputs, the second amplifier including second positive and negative inputs and second positive and negative outputs, first to fourth wirings, a selection circuit including the first selection element connecting the first or fourth wirings to the second positive input, and the second selection element connecting the second or third wirings to the second negative input, and a control circuit connecting the amplifiers by the first and second wirings or by the third and fourth wirings.

Abstract: An envelope tracking power supply and transmitter control circuitry are disclosed. The transmitter control circuitry receives a first envelope power supply control signal and a second envelope power supply control signal. The envelope tracking power supply operates in one of a group of operating modes, which includes a first operating mode and a second operating mode. During both the first operating mode and the second operating mode, a first envelope power supply signal is provided to a driver stage based on the first envelope power supply control signal. During the first operating mode, a second envelope power supply signal is provided to a final stage based on the first envelope power supply control signal. However, during the second operating mode, the second envelope power supply signal is provided to the final stage based on the second envelope power supply control signal.

Abstract: A microwave semiconductor amplifier includes a semiconductor amplifier element, an input matching circuit and an output matching circuit. The semiconductor amplifying element includes an input electrode and an output electrode and has a capacitive output impedance. The input matching circuit is connected to the input electrode. The output matching circuit includes a bonding wire and a first transmission line. The bonding wire includes first and second end portions. The first end portion is connected to the output electrode. The second end portion is connected to one end portion of the first transmission line. A fundamental impedance and a second harmonic impedance seen toward the external load change toward the one end portion. The second harmonic impedance at the one end portion has an inductive reactance. The output matching circuit matches the capacitive output impedance of the semiconductor amplifying element to the fundamental impedance of the external load.

Abstract: A method is provided. A first enable signal is asserted so as to enable a first driver, where the first driver has a first output and a first parasitic capacitance. A second enable signal is asserted so as to enable a second driver, where the second driver has a second output and a second parasitic capacitance. The first and second outputs are coupled together by a switching network when the second driver is enabled. Pulses from complementary first and second radio frequency (RF) signals are applied to the first driver, where there is a first set of free-fly intervals between consecutive pulses from the first and second RF signals, and pulses from complementary third and fourth RF signals are applied to the second driver, wherein there is a second set of free-fly interval between consecutive pulses from the third and fourth RF signals.

Abstract: The current-mode CMOS logarithmic function circuit provides an ultra-low power circuit that produces an output current proportional to the logarithm of the input current. An OTA (operational transconductance amplifier) constructed from CMOS transistors, in combination with two PMOS transistors configured in weak inversion mode for providing a reference voltage input and a voltage input from the input current to the OTA, provides the circuit with a high dynamic range, controllable amplitude, high accuracy, and insensitivity to temperature variation.

Abstract: An amplifying circuit for use in, for example, broadband transceivers is described. A bias filter is connected between an amplifying transistor and a power supply to block a wide range of frequencies associated with amplified RF input signals from reaching the power supply, while permitting DC power to reach the transistor.

Abstract: An amplifier includes a transformer including a primary coil whose one end is connected to an input port and whose other end is connected to reference potential and a secondary coil magnetically-coupled with the primary coil, and a transistor including a source connected to one end of the secondary coil and a gate connected to other end of the secondary coil and a drain connected to an output port side.

Abstract: A receiver is described. The receiver includes a first amplifier on an integrated circuit. The receiver also includes a second amplifier on the integrated circuit. The receiver further includes a first inductor coupled to the first amplifier. The receiver also includes a second inductor coupled to the second amplifier. The receiver further includes a first capacitor coupled to the first inductor, the second inductor, and to ground. The first capacitor is shared between a first matching network for the first amplifier and a second matching network for the second amplifier.

Abstract: A calibration device arranged for calibrating an oscillating frequency of an oscillator includes: a phase locking device arranged to track a first reference clock generated by the oscillator until a feedback clock is phase-aligned with the first reference clock, and then arranged to track a second reference clock generated by the oscillator until a phase difference between the second reference clock and the feedback clock is a static phase difference, wherein the feedback clock is generated by dividing an output oscillating signal of the phase locking device by a divisor; an adjusting circuit arranged to adjust the divisor into an updated divisor to reduce the static phase difference between the second reference clock and the feedback clock; and a calibrating circuit arranged to calibrate the oscillating frequency of the oscillator according to the updated divisor, wherein the second reference clock is generated by varying a control signal of the oscillator.

Abstract: An oscillator circuit includes a signal generator having a compensation frequency output node that provides a compensation frequency signal at the compensation frequency output node. A pulse generator having a pulsed signal output node and a pulse generator input node is coupled to the compensation frequency output node and converts the compensation frequency signal into a series of compensation binary pulses having a constant pulse duration regardless of variations in the duty cycle of the compensation binary pulses. An oscillator module having at least two capacitors, an oscillator output node and a pulsed signal input node is coupled to the pulsed signal output node, and provides an output signal that is at a frequency dependent on charging rates of the capacitors. Drift variations in the capacitors are offset by variations in a duty cycle of the compensation binary pulses supplied in order to maintain constant charging rates of the capacitors.