Patents Issued in September 17, 2013
  • Patent number: 8536042
    Abstract: A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John T. Andrews, Hamza Yilmaz, Bruce Marchant, Ihsiu Ho
  • Patent number: 8536043
    Abstract: Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jeehwan Kim, Jin-Hong Park, Devendra Sadana, Kuen-Ting Shiu
  • Patent number: 8536044
    Abstract: A method for opening a bond pad on a semiconductor device is provided. The method comprises removing a first layer to expose a first portion of the bond pad and forming a protective layer over the exposed first portion of the bond pad. The method further comprises performing subsequent processing of the semiconductor device and removing the protective layer to expose a second portion of the bond pad.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: September 17, 2013
    Assignee: Intersil Americas Inc.
    Inventors: Helen Hongwei Li, Joy Ellen Jones, Phillip J. Benzel, Jeanne M. McNamara, John T. Gasner
  • Patent number: 8536045
    Abstract: A reflow method of a solder ball provided to a treatment object may include providing a coil, applying a current to the coil, and moving the treatment object through an internal space surrounded by the coil.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: September 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minill Kim, Kwang Yong Lee, Jonggi Lee, Ji-Seok Hong
  • Patent number: 8536046
    Abstract: Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: September 17, 2013
    Assignee: Micron Technology
    Inventor: Teck Kheng Lee
  • Patent number: 8536047
    Abstract: A device and a method for realizing reliable electrical contacts at low temperature and low pressure between conducting materials on, for example, different substrates are disclosed. In one aspect, a rough and brittle intermetallic layer is formed on a conducting material on a first substrate. A soft solder material layer on the other substrate is used for contacting the brittle and rough intermetallic layer that will break. As the solder material is relatively soft, contact between the broken intermetallic layer and the solder material can be realized over a large portion of the surface area. At that stage, a second intermetallic layer is formed between the solder material and the first intermetallic layer realizing electrical contact.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: September 17, 2013
    Assignee: IMEC
    Inventors: Wenqi Zhang, Eric Beyne
  • Patent number: 8536048
    Abstract: According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nansei
  • Patent number: 8536049
    Abstract: Methods of forming metal contacts with metal inks in the manufacture of photovoltaic devices are disclosed. The metal inks are selectively deposited on semiconductor coatings by inkjet and aerosol apparatus. The composite is heated to selective temperatures where the metal inks burn through the coating to form an electrical contact with the semiconductor. Metal layers are then deposited on the electrical contacts by light induced or light assisted plating.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: September 17, 2013
    Assignees: Rohm and Haas Electronic Materials LLC, Alliance for Sustainable Energy, LLC
    Inventors: Erik Reddington, Thomas C. Sutter, Lujia Bu, Alexandra Cannon, Susan E. Habas, Calvin J. Curtis, Alexander Miedaner, David S. Ginley, Marinus Franciscus Antonius Maria Van Hest
  • Patent number: 8536050
    Abstract: In sophisticated semiconductor devices, the contact elements connecting to active semiconductor regions having formed thereabove closely spaced gate electrode structures may be provided on the basis of a liner material so as to reduce the lateral width of the contact opening, while, on the other hand, non-critical contact elements may be formed on the basis of non-reduced lateral dimensions. To this end, at least a first portion of the critical contact element is formed and provided with a liner material prior to forming the non-critical contact element.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: September 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kai Frohberg, Ralf Richter, Torsten Huisinga, Katrin Reiche
  • Patent number: 8536051
    Abstract: A semiconductor device manufacture method includes: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; executing a plasma process for a side wall of the patterned first mask film to transform the side wall into a transformed layer; after the plasma process, forming a second mask film covering the first mask film; etching the second mask film to remove the second mask film above the first mask film and leave the second mask film formed on the side wall; after the etching the second mask film, removing the transformed layer; and after the removing the transformed layer, etching the first film by using the first mask film and the second mask film as mask.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: September 17, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hikaru Ohira, Tomoyuki Kirimura
  • Patent number: 8536052
    Abstract: When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: September 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Kai Frohberg, Katrin Reiche
  • Patent number: 8536053
    Abstract: A method for restricting lateral encroachment of the metal silicide into the channel region, comprising: providing a semiconductor substrate, a gate stack being formed on the semiconductor substrate, a source region being formed in the semiconductor on one side of the gate stack, and a drain region being formed in the semiconductor substrate on the other side of the gate stack; forming a sacrificial spacer around the gate stack and on the semiconductor substrate; depositing a metal layer for covering the semiconductor substrate, the gate stack and the sacrificial spacer; performing a thermal treatment on the semiconductor substrate, thereby causing the metal layer to react with the sacrificial spacer and the semiconductor substrate in the source region and the drain region; removing the sacrificial spacer, reaction products of the sacrificial spacer and the metal layer, and a part of the metal layer which does not react with the sacrificial spacer.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: September 17, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Jun Luo, Chao Zhao, Huicai Zhong
  • Patent number: 8536054
    Abstract: Provided herein are methods of polishing and texturing surfaces thin-film photovoltaic cell substrates. The methods involve laser irradiation of a surface having a high frequency roughness in an area of 5-200 microns to form a shallow and rapidly expanding melt pool, followed by rapid cooling of the material surface. The minimization of surface tension causes the surface to re-solidify in a locally smooth surface. the high frequency roughness drops over the surface with a lower frequency bump or texture pattern remaining from the re-solidification.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: September 17, 2013
    Assignee: MIASOLE
    Inventors: Dallas W. Meyer, Jason Stephen Corneille, Steven Thomas Croft, Mulugeta Zerfu Wudu, William James McColl
  • Patent number: 8536056
    Abstract: A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: September 17, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Kuo-Hui Su, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8536057
    Abstract: A thin film deposition apparatus and a method of manufacturing an organic light emitting device (OLED) using the thin film deposition apparatus.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: September 17, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Choong-Ho Lee, Yoon-Chan Oh, Jung-Min Lee
  • Patent number: 8536058
    Abstract: A method for forming a conductive thin film includes depositing a metal oxide thin film on a substrate by an atomic layer deposition (ALD) process. The method further includes at least partially reducing the metal oxide thin film by exposing the metal oxide thin film to a reducing agent, thereby forming a seed layer. In one arrangement, the reducing agent comprises one or more organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO, and —COOH. In another arrangement, the reducing agent comprises an electric current.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: September 17, 2013
    Assignee: ASM International N.V.
    Inventors: Juhana Kostamo, Pekka J. Soininen, Kai-Erik Elers, Suvi Haukka
  • Patent number: 8536059
    Abstract: Etching equipment and methods are disclosed herein for more efficient etching of sacrificial material from between permanent MEMS structures. An etching head includes an elongate etchant inlet structure, which may be slot-shaped or an elongate distribution of inlet holes. A substrate is supported in proximity to the etching head in a manner that defines a flow path substantially parallel to the substrate face, and permits relative motion for the etching head to scan across the substrate.
    Type: Grant
    Filed: February 18, 2008
    Date of Patent: September 17, 2013
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Khurshid Syed Alam, Evgeni Gousev, Marc Maurice Mignard, David Heald, Ana R. Londergan, Philip Don Floyd
  • Patent number: 8536060
    Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: September 17, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yen-Chu Chen, Teng-Chun Tsai, Chien-Chung Huang, Keng-Jen Liu
  • Patent number: 8536061
    Abstract: According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisataka Hayashi, Yusuke Kasahara, Tsubasa Imamura
  • Patent number: 8536062
    Abstract: Methods are provided for removing an oxide layer from a metal pad on an integrated circuit in order to reduce contact resistance. In one embodiment, aluminum oxide, on the surface of a bond pad substantially comprised of aluminum, is reacted with a first chemical agent to form an inorganic salt, and the inorganic salt is then reacted with a second chemical agent leaving a substantially bare, that is, unoxidized, aluminum surface.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: September 17, 2013
    Assignee: Advanced Inquiry Systems, Inc.
    Inventor: Jens Ruffler
  • Patent number: 8536063
    Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: September 17, 2013
    Assignee: Avalanche Technology Inc.
    Inventors: Kimihiro Satoh, Yiming Huai, Jing Zhang, Rajiv Yadav Ranjan, Parviz Keshtbod, Roger K. Malmhall
  • Patent number: 8536064
    Abstract: A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chih-Hao Chen, Keng-Chu Lin
  • Patent number: 8536065
    Abstract: Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron containing amorphous carbon layer on a semiconductor substrate. In one embodiment, a method of processing a substrate in a processing chamber is provided. The method comprises providing a substrate in a processing volume, flowing a hydrocarbon containing gas mixture into the processing volume, generating a plasma of the hydrocarbon containing gas mixture by applying power from an RF source, flowing a boron containing gas mixture into the processing volume, and depositing a boron containing amorphous carbon film on the substrate in the presence of the plasma, wherein the boron containing amorphous carbon film contains from about 30 to about 60 atomic percentage of boron.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 17, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Martin Jay Seamons, Sudha Rathi, Kwangduk Douglas Lee, Deenesh Padhi, Bok Hoen Kim, Chiu Chan
  • Patent number: 8536066
    Abstract: Methods of forming an oxide layer on silicon carbide include thermally growing an oxide layer on a layer of silicon carbide, and annealing the oxide layer in an environment containing NO at a temperature greater than 1175° C. The oxide layer may be annealed in NO in a silicon carbide tube that may be coated with silicon carbide. To form the oxide layer, a preliminary oxide layer may be thermally grown on a silicon carbide layer in dry O2, and the preliminary oxide layer may be re-oxidized in wet O2.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: September 17, 2013
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Brett Hull, Sumi Krishnaswami
  • Patent number: 8536067
    Abstract: A memory element is formed by providing an organic compound between a pair of upper and lower electrodes. However, when the electrode is formed over a layer containing an organic compound, a temperature is limited because the layer containing the organic compound can be influenced depending on a temperature for forming the electrode. A forming method for the electrode is limited due to this limitation of a temperature. Therefore, there are problems that an expected electrode cannot be formed, and miniaturization of an element is inhibited. A semiconductor device includes a memory element and a switching element which are provided over a substrate having an insulating surface. The memory element includes first and second electrodes, and a layer containing an organic compound, which are provided on the same plane. A current flows from the first electrode to the second electrode. The first electrode is electrically connected to the switching element.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: September 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Takehisa Sato
  • Patent number: 8536068
    Abstract: Methods for forming photoresists sensitive to radiation on substrate are provided. Atomic layer deposition methods of forming films (e.g., silicon-containing films) photoresists are described. The process can be repeated multiple times to deposit a plurality of silicon photoresist layers. Process of depositing photoresist and forming patterns in photoresist are also disclosed which utilize carbon containing underlayers such as amorphous carbon layers.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: September 17, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Timothy W. Weidman, Timothy Michaelson, Paul Deaton
  • Patent number: 8536069
    Abstract: The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 17, 2013
    Assignees: International Business Machines Corporation, Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Stephan A. Cohen, Alfred Grill, Thomas J. Haigh, Jr., Son V. Nguyen, Li-Qun Xia
  • Patent number: 8536070
    Abstract: This invention relates to materials and processes for thin film deposition on solid substrates. Silica/alumina nanolaminates were deposited on heated substrates by the reaction of an aluminum-containing compound with a silanol. The nanolaminates have very uniform thickness and excellent step coverage in holes with aspect ratios over 40:1. The films are transparent and good electrical insulators. This invention also relates to materials and processes for producing improved porous dielectric materials used in the insulation of electrical conductors in microelectronic devices, particularly through materials and processes for producing semi-porous dielectric materials wherein surface porosity is significantly reduced or removed while internal porosity is preserved to maintain a desired low-k value for the overall dielectric material.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: September 17, 2013
    Assignee: President and Fellows of Harvard College
    Inventors: Roy Gerald Gordon, Jill S. Becker, Dennis Hausmann
  • Patent number: 8536071
    Abstract: An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A thermally and electrically conductive gasket with projections thereon is compressed between the showerhead electrode and the backing plate at a location three to four inches from the center of the showerhead electrode. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release locking pins extending from the upper face of the electrode.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: September 17, 2013
    Assignee: Lam Research Corporation
    Inventors: Gregory R. Bettencourt, Gautam Bhattacharyya, Simon Gosselin, Sandy Chao
  • Patent number: 8536072
    Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: September 17, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li
  • Patent number: 8536073
    Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: September 17, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwanathan Rangarajan, George Andrew Antonelli, Ananda Banerji, Bart Van Schravendijk
  • Patent number: 8536074
    Abstract: Disclosed are cleaning sheets having substantial macroscopic three-dimensionality. Optionally, the macroscopically three-dimensional cleaning sheets can comprise a contractable material (e.g., a scrim material), which when heated and then cooled contracts so as to provide a macroscopic, three-dimensional structure. Macroscopic three-dimensionality is described in terms of “average peak-to-peak distance” and “surface topography index”, as well in terms of “average height differential”. Also disclosed are cleaning implements comprising a handle and the described cleaning sheets. Processes for the sheets, benefits of the processes, and articles of manufacture are also disclosed.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: September 17, 2013
    Assignee: The Procter & Gamble Company
    Inventors: Saeed Fereshtehkhou, Paul Joseph Russo, Wilbur Cecil Strickland, Jr., Nicola John Policicchio
  • Patent number: 8536075
    Abstract: A textile thread or fiber has a plurality of elements, such as electronic elements, embedded or encapsulated therein. The textile thread or fiber could also be part of a fabric article. The textile thread or fiber, for example, has the plurality of elements interconnected, or otherwise intercommunicating, with one another to form a signal processing system. This signal processing system may include, for example, a personal computer system, a personal telecommunications transmitter/receiver system or a personal television and/or radio system.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: September 17, 2013
    Inventor: Philip Noel Leonard
  • Patent number: 8536076
    Abstract: A textile fleece fabric having a resistance to thermal energy from exposure to momentary electric arcs or flame so as to be suitable for use in safety apparel is made of three integrated layers including inner and outer layers on opposite sides of an intervening middle layer. The inner and outer layers are comprised predominately of textile fibers which have inherent or additive flame resistant properties, and the middle layer is comprised substantially entirely of textile fibers without inherent or additive flame resistant properties. The textile fibers of one of the inner or outer layers have a raised nap forming a fleece surface.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: September 17, 2013
    Assignee: Innovative Textiles, Inc.
    Inventor: Michael N. Byles
  • Patent number: 8536077
    Abstract: Disclosed herein is a flooring underlayment membrane, and associated methods of manufacturing and installing such a membrane, comprising upper and lower nonwoven fiber layers. In one embodiment, the flooring underlayment membrane constructed as disclosed herein may comprise a first nonwoven fiber material, and a second nonwoven fiber material and at least one layer of extrudable thermoplastic resin disposed between and bonding the first and second nonwoven fiber materials.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: September 17, 2013
    Assignee: Building Materials Investment Corporation
    Inventors: Daniel LaVietes, David Gladden, Song-Ping Dai
  • Patent number: 8536078
    Abstract: Lithium silicate glass ceramics and glasses containing at least 6.1 wt.-% ZrO2 are provided which can advantageously be applied to zirconium oxide ceramics in particular by pressing-on in the viscous state and forming a solid bond with the zirconium oxide ceramics.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: September 17, 2013
    Assignee: Ivoclar Vivadent AG
    Inventors: Christian Ritzberger, Ricardo Dellagiacomo, Marcel Schweiger, Harald Burke, Wolfram Holand, Volker Rheinberger
  • Patent number: 8536079
    Abstract: An unbonded loosefill insulation material formed from a glass batch is provided. The glass batch comprises, in weight percent: 62.0-69.0% of SiO2, 0.0-4.0% of Al2O3, 7.0-12.0% of CaO, 0.0-5.0% of MgO, 3.0-14.0% of B2O3, 13.0-18.0% of Na2O and 0.0-3.0% of K2O. The unbonded loosefill insulation material is configured for distribution in a blowing insulation machine.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: September 17, 2013
    Assignee: Owens Corning Intellectual Capital, LLC
    Inventors: Michael E. Evans, Patrick M. Gavin, Scott E. Colangelo
  • Patent number: 8536080
    Abstract: A metal carbide ceramic fiber having improved mechanical properties and characteristics and improved processes and chemical routes for manufacturing metal carbide ceramic fiber. Metal carbide ceramic fibers may be formed via reaction bonding of a metal-based material (e.g. boron) with the inherent carbon of a carrier medium. One embodiment includes a method of making a metal carbide ceramic fiber using VSSP to produce high yield boron carbide fiber. Embodiments of the improved method allow high volume production of high density boron carbide fiber. The chemical routes may include a direct production of boron carbide fiber from boron carbide powder (B4C) and precursor (e.g. rayon fiber) having a carbon component to form a B4C/rayon fiber that may be processed at high temperature to form boron carbide fiber, and that may be subsequently undergo a hot isostatic pressing to improve fiber purity. Another route may include a carbothermal method comprising combining boron powder (B) with a precursor (e.g.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: September 17, 2013
    Assignee: Advanced Cetametrics, Inc.
    Inventors: Farhad Mohammadi, Richard B. Cass
  • Patent number: 8536081
    Abstract: Supported catalyst system for the polymerization of olefins, having at least two different monocyclopentadienyl transition metal compounds, one or more activators including an ionic compound having (i) a cation and (ii) an anion having up to 100 non-hydrogen atoms and the anion containing at least one substituent comprising a moiety having an active hydrogen, and one or more support materials. The supported “mixed or dual site” catalyst systems having different monocyclopentadienyl catalysts when activated by specific ionic activators lead to catalyst systems showing an improved balance of properties which may be used to prepare LLDPE polymers having broad melt flow ratios.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: September 17, 2013
    Assignee: Ineos Europe Limited
    Inventors: Grant Berent Jacobsen, Dusan Jeremic, Sergio Mastroianni, Ian Douglas McKay
  • Patent number: 8536082
    Abstract: The invention relates to a method of preparing a dehydrogenation catalyst comprising a group VIII metal, a group IVA metal and a refractory oxide support. The method comprises stages of preparing the dry impregnation aqueous solution containing said group VIII metal, ammonia, either in solution or in gas form, and a complexing agent. It then comprises stages of aging the aqueous solution, of dry impregnation of the support, of maturing the impregnated support, of drying the impregnated support and of calcining the dried support.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: September 17, 2013
    Assignee: IFP Energies Nouvelles
    Inventors: Alexandre Chambard, Yohan Oudart
  • Patent number: 8536083
    Abstract: A process is provided for preparing a carrier which process comprises incorporating into the carrier at any stage of the carrier preparation a strength-enhancing additive. Also provided is the resultant carrier having incorporated therein a strength-enhancing additive and a catalyst comprising the carrier. Also provided is a process for the epoxidation of an olefin employing the catalyst. Also provided is a method of using the olefin oxide so produced for making a 1,2-diol, a 1,2-diol ether or an alkanolamine.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: September 17, 2013
    Assignee: Shell Oil Company
    Inventors: Randall Clayton Yeates, John Robert Lockemeyer, Marek Matusz
  • Patent number: 8536084
    Abstract: The present invention provides a tungsten trioxide microparticle carrying on its surface divalent copper salt. The divalent copper salt is utilized to perform a multi-electron reduction of oxygen. The tungsten trioxide exhibits a high oxidative decomposition activity when exposed to visible light.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: September 17, 2013
    Assignees: The University of Tokyo, Panasonic Corporation
    Inventors: Kazuhito Hashimoto, Hiroshi Irie, Syuhei Miura, Kazuhide Kamiya, Shinichiro Miki, Koichi Takahama, Mitsuo Yaguchi
  • Patent number: 8536085
    Abstract: A method is provided for preparing a supported cobalt-containing catalyst having substantially homogeneously dispersed, small cobalt crystallites. The method comprises depositing cobalt nitrate on a support and then subjecting the support to a two-step decomposition protocol. In the first step, the support is heated in an oxygen-containing, substantially water-free atmosphere to about 160° C. to form an intermediate decomposition product. This intermediate product is then or hydrolyzed and reduced, or hydrolyzed, calcined and reduced.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: September 17, 2013
    Assignee: ExxonMobil Research and Engineering Company
    Inventors: Stuart L. Soled, Joseph E. Baumgartner, Christine E. Kliewer, El-Mekki El-Malki, Patricia A. Bielenberg
  • Patent number: 8536086
    Abstract: A thermosensitive recording medium including a support; a layer containing a photothermal conversion material, formed over a surface of the support; and an oxygen blocking layer formed over a surface of the layer opposite to a surface thereof over which the support is formed, wherein the layer further contains a resin, which is in a cross-linked state, and the photothermal conversion material absorbs a light having a specific wavelength and converts the light into heat, and wherein the oxygen blocking layer has an oxygen permeability of 0.5 mL/(m2·24 hr·atm) or less at 25° C. and 80% RH.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: September 17, 2013
    Assignee: Ricoh Company, Ltd.
    Inventors: Shinya Kawahara, Tomomi Ishimi, Toshiaki Asai, Yoshihiko Hotta
  • Patent number: 8536087
    Abstract: A thermographic substrate assembly comprised of a colorant and a flexible substrate. This assembly also contains a thermosensitive layer, and the thermosensitive layer contains a binder, a multiplicity of hollow sphere organic pigments, and a thermal solvent.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: September 17, 2013
    Assignee: International Imaging Materials, Inc.
    Inventors: Daniel Jude Harrison, Barry L. Marginean, John Przybylo, Kathleen Lindstrom, Natalie Soldwisch
  • Patent number: 8536088
    Abstract: In an image-forming method, a ribbon-shaped thermal transfer sheet with a dye layer and a protective material layer arranged side-by-side in the longitudinal direction is moved, and thermal energy is applied from a thermal head while arranging a recording medium to face the dye layer to thermally transfer the dye layer onto the recording medium to form an image. Thermal energy is applied while arranging the image to face the protective material layer to thereby form a protective layer on the image by thermal transfer. A ribbon-shaped surface-property-modifying sheet including a surface-property-modifying region for modifying the surface of the protective layer is moved, and the protective layer is aligned with the surface-property-modifying region of the surface-property-modifying sheet. Heat and pressure are applied from the thermal head and the surface-property-modifying sheet is detached after cooling to modify the surface condition of the protective layer.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: September 17, 2013
    Assignee: Sony Corporation
    Inventors: Takaaki Murakami, Ken Higuchi, Yasushi Hirumi
  • Patent number: 8536089
    Abstract: The invention relates to fungicidal compositions comprising as active ingredient a combination of components A) and B) as defined in the patent claims, to a method of controlling phytopathogenic diseases on crop plants using such a compositions and to a method of protecting natural substances of vegetable and/or animal origin and/or their processed forms using such a composition.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: September 17, 2013
    Assignee: Syngenta Crop Protection LLC
    Inventors: Harald Walter, Urs Neuenschwander, Ronald Zeun, Josef Ehrenfreund, Hans Tobler, Camilla Corsi, Clemens Lamberth
  • Patent number: 8536090
    Abstract: A use of a tannin and non tannin material phytocomposition or phytocomplex, either in a dry or liquid form, applied to the seedling seeds or seedling agamic multiplication members, or to implanted seedlings, to promote the starter effect, i.e. strong stimulation of the seedling initial growth. The phytocomposition is made by leaching a biomass of one or more of the following species: Castanea spp., Juglans spp., Eucalyptus spp., Quercus spp., Salix spp., Vitis spp., Mimosa ssp., Schinopsis spp., Olea europaea, Onobrychis viciifolia, Rhamnus spp., Artemisia spp., Lawsonia inermis, either in a single form or in a mixture in all mixing ratios.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: September 17, 2013
    Assignee: Gruppo Mauro Saviola S.R.L.
    Inventors: Enrica Bargiacchi, Gianluca Costa, Sergio Miele, Simone Magni
  • Patent number: 8536091
    Abstract: System, including methods compositions, and kits, for controlling the growth of fungi and other pathogens in plants using at least one alkamide, which may function by increasing or eliciting natural defense mechanisms of the plants against such pathogens.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: September 17, 2013
    Inventors: José López-Bucio, Jorge Molina-Torres, Luis Rafael Herrera-Estrella
  • Patent number: 8536092
    Abstract: The present invention relates to new insecticides of the formula (I) in which R1, R2, R3, R4, R5, R6, A, Q and n can have the definitions stated in the description, to a number of processes for preparing them and to their use as active compounds, more particularly to their use as pest control compositions.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: September 17, 2013
    Assignee: Bayer Cropscience AG
    Inventors: Bernd Alig, Rüdiger Fischer, Christian Funke, Rudolf F. Ernst Gesing, Achim Hense, Olga Malsam, Mark Wilhelm Drewes, Ulrich Görgens, Tetsuya Murata, Katsuaki Wada, Christian Arnold, Erich Sanwald