Abstract: A magnetic resonance imaging (MRI) water-fat separation method includes acquiring in-phase image raw measurement data and out-of-phase image raw measurement data with an MRI device, reconstructing an in-phase image and an out-of-phase image according to a system matrix and the raw measurement data using the penalty function regularized iterative reconstruction method, and calculating water and fat images according to the in-phase image and the out-of-phase image. The use of the penalty function regularized iterative method eliminates the need for k-space raw measurement data with a 100% sampling rate, thereby reducing the MRI scan time, shortening the entire imaging time, and improving the efficiency of the MRI device.

Abstract: According to one embodiment, there is provided a magnetic resonance imaging apparatus in which a gradient field power supply apparatus supplies currents to gradient field coils corresponding to spatial coordinate axis directions to form gradient fields in a static field space which change along the respective spatial coordinate axis directions, the gradient field power supply apparatus includes a transformer configured to supply power supplied to a primary winding to a current output circuit via a plurality of secondary windings, with the number of phases of the primary windings being equal to or a multiple of the number of phases of the secondary windings, and the secondary windings of the respective phases of output channels corresponding to the respective spatial coordinate axis directions being wound around the primary windings of the respective phases.

Abstract: An antenna configuration for use in a magnetic resonance apparatus has at least two individual antennas which each include at least one conductor loop, one tuning network and one matching network, wherein the individual antennas are each combined into separate modules which are positioned on and mounted to a support body and can be removed therefrom in a non-destructive fashion, is characterized in that the individual antennas are connected to each other through decoupling elements, wherein the decoupling elements are mounted to the support body in an undetachable fashion. It is thereby possible to define individual antenna modules which can be arranged in a simple fashion around the measuring volume, are also electromagnetically decoupled from each other, and can be positioned close to the measuring volume in order to ensure that the received MRI image has a maximum, high signal-to-noise ratio.

Abstract: Locate information relating to use of a locate device to perform a locate operation may be acquired from one or more input devices, logged/stored in local memory of a locate device, formatted in various manners, processed and/or analyzed at the locate device itself, and/or transmitted to another device (e.g., a remote computer/server) for storage, processing and/or analysis. In one example, a locate device may include one or more environmental sensors and/or operational sensors, and the locate information may include environmental information and operational information derived from such sensors. Environmental and/or operational information may be used to control operation of the locate device, assess out-of-tolerance conditions in connection with use of the locate device, and/or provide alerts or other feedback. Additional enhancements are disclosed relating to improving the determination of a location (e.g.

Abstract: A vertical receiver antenna device includes first and second receiving, electrode units interconnected by a receiver antenna cable and connected to means for the electromagnetic surveying of electrically resistive targets potentially containing hydrocarbons. The receiver antenna is arranged in a tubular, non-magnetic antenna housing arranged vertically in subsea uncompacted material, and one of the first and second receiving electrode units being connected in a electrically conductive manner to the underlying structure, and the other one of the first and second receiving electrode units being arranged in a portion of the antenna housing distantly from the first one of first and second receiving electrode units.

Abstract: An operational amplifier has an input biased at a predetermined reference voltage. A control unit opens both second switches and third switches corresponding to unit batteries being non-detection object, closes fourth switch. The control unit further closes both one of first switches and one of third switches corresponding to one unit battery being a detection object to charge corresponding one of first capacitors. Thereafter, the control unit opens the fourth switch. The control unit further closes one of the second switches corresponding to the one unit battery being the detection object, instead of the one of the first switches. Thus, the control unit detects a voltage of each of the unit batteries.

Abstract: A ground monitor is disclosed. The ground monitor may be configured to conduct a ground continuity test based on a determined ground resistance. The ground monitor may be operable to determine the ground resistance as a function of a voltage differential detected during application of a test current.

Abstract: A display panel and a testing method of the display panel are provided. The display panel has a display region and a non-display region and includes a first substrate, a second substrate, and a display medium. The display panel further includes scan lines, data lines, pixel units, at least one testing line, and at least one testing pad. The scan lines and the data lines are located on the first substrate within the display region. The pixel units are located on the first substrate within the display region. Each pixel unit electrically connects one of the scan lines and one of the data lines. The testing line is located on the first substrate within the non-display region, crosses over the scan lines, and is insulated from the scan lines. The testing pad is located on the first substrate within the non-display region and electrically connected to the testing line.

Abstract: An interface device provides one or more electrical connection points disposed on a connector sleeve. The connection points provide electrical communication between a lead connector end of an implantable medical lead and one or more leads of a testing device in such a manner as to minimize potential damage to the lead connector end.

Abstract: A method for testing a mask article includes the steps of electrically connecting the mask article to an electrical sensor, applying a bias voltage to a plurality of testing sites of the mask article with a conductor, measuring at least one current distribution of the testing sites with the electrical sensor, and determining the quality of the mask article by taking the at least one current distribution into consideration.

Abstract: A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.

Abstract: A wireless in-plane strain and displacement sensor includes an electrical conductor fixedly coupled to a substrate subject to strain conditions. The electrical conductor is shaped between its ends for storage of an electric field and a magnetic field, and remains electrically unconnected to define an unconnected open-circuit having inductance and capacitance. In the presence of a time-varying magnetic field, the electrical conductor so-shaped resonates to generate harmonic electric and magnetic field responses. The sensor also includes at least one electrically unconnected electrode having an end and a free portion extending from the end thereof. The end of each electrode is fixedly coupled to the substrate and the free portion thereof remains unencumbered and spaced apart from a portion of the electrical conductor so-shaped. More specifically, at least some of the free portion is disposed at a location lying within the magnetic field response generated by the electrical conductor.

Abstract: In an example embodiment, an apparatus includes a sensing device. The sensing device includes circuitry configured to sense self-capacitance and circuitry configured to sense mutual-capacitance, each configured to detect capacitance values corresponding to whether an object is proximate to a touch screen. The sensing device is configured to measure a first capacitance value using the self-capacitance circuitry during self-capacitance sensing operations and to measure a second capacitance value using the mutual-capacitance circuitry during mutual-capacitance sensing operations.

Abstract: A method for use in determining the thickness of a layer of interest in a multi-layer structure. A first electrode is positioned in contact with a first surface of the multi-layer structure, and a second electrode is positioned in contact with a second surface of the multi-layer structure. The second surface is substantially opposite the first surface. The first electrode is pressed against the multi-layer structure at a predetermined sampling pressure, and the structure is optionally adjusted to a predetermined sampling temperature. The electrical impedance between the first electrode and the second electrode is measured.

Abstract: A capacitive proximity sensor (100) comprises a sensor unit (10) and a sense circuit unit (20). The sensor unit (10) includes a sensor electrode (11), a shield electrode (12) and an auxiliary electrode (13). The sensor electrode (11) is connected to a C-V conversion circuit (21) and the shield electrode (12) is connected to a shield drive circuit (24). The auxiliary electrode (13) is connected via a change-over switch (30) to the C-V conversion circuit (21) or the shield drive circuit (24). The capacitance values (C1, C2) switched by the change-over switch (30) and detected at the C-V conversion circuit (21) are compared to arbitrarily set a range of a sense region on the sensor electrode (11).

Abstract: Provided is a test apparatus comprising a plurality of testing sections and a synchronizing section that synchronizes operation of at least two testing sections among the plurality of testing sections. Each testing section transmits a synchronization standby command to the synchronizing section when a predetermined condition is fulfilled during execution of the corresponding program and the testing section enters a synchronization standby state, and on a condition that the synchronization standby commands have been received from all of one or more predetermined testing sections among the plurality of testing sections, the synchronizing section supplies a synchronization signal, which ends the synchronization standby state, in synchronization to two or more predetermined testing sections among the plurality of testing sections.

Abstract: A method and an apparatus for verifying or testing test substrates, i.e. wafers and other electronic semiconductor components, in a prober under defined thermal conditions. Such a verifying apparatus, known to the person skilled in the art as a prober, has a housing having at least two housing sections, in one housing section of which, designated hereinafter as test chamber, the test substrate to be verified is held by a chuck and is set to a defined temperature, and in the other housing section of which, designated hereinafter as probe chamber, probes are held. For verification purposes, the test substrate and the probes are positioned relative to one another by means of at least one positioning device and the probes subsequently make contact with the test substrate.

Abstract: The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC devices at elevated temperatures may be useful for ‘burn-in’, for ‘hot sort’ performance testing that may be used in electronic devices such as DRAM memory, logic, communication devices, and microprocessors. The power sink function may be implemented as an additional isolated area of active devices, or as a section of the circuit that is not involved in the testing procedure. Alternately, the power dissipation circuit may consist of a resistive path between two external pins that are not used for IC operation, where the resistor may be on the IC or on the package. This allows for control of the temperature level and profile by simple adjustment of the voltage between the two external pins.

Abstract: A circuit board tester and method that precisely aligns the probe plate and circuit board is disclosed. With a circuit board and probe plate mounting within a housing having a top and bottom, hinged together, at closure there may be slight misalignments of the two. By making one of the two plates floating, or laterally slideable with respect to each other, it is possible to make final alignment at closure. One of the two plates can be provided with a pin and the other with a pin receiving alignment block. With the lateral sideability, the pin and block can insure proper probe alignment. Additional systems for correcting misaligned pins or blocks are also disclosed.

Abstract: A probe card includes a circuit board, a flexible substrate, and a plurality of probes. The flexible substrate includes a plurality of arrayed conductive strips. The plurality of conductive strips is electrically connected to the printed circuit board. The plurality of probes is fixed to the printed circuit board, and the end of each probe is attached to one corresponding conductive strip.

Abstract: The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.

Abstract: A method of detecting a failure of an alternator supplying three-phase electricity to a load, the method comprising the steps of determining a duty ratio for each of the phases at the output of the alternator, determining phase differences between the phases at the output of the alternator; and determining the presence of a failure as a function of the phase differences and as a function of a comparison of the duty ratios. A power supply device is also provided for implementing the method.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction.

Abstract: A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation.

Abstract: A level shifting circuit and methodology involving a switching current generator responsive to switching of an input signal for producing a switching current to switch an output signal, and a holding current generator for producing a holding current to hold the logic level of the output signal in accordance with the logic level of the input signal. The holding current is produced independently of the switching current.

Abstract: The driver circuit includes a first controlling circuit that outputs, to a gate of the auxiliary pMOS transistor, a first controlling signal that rises in synchronization with a rising of the first pulse signal and falls after a delay from a falling of the first pulse signal. The driver circuit includes a second controlling circuit that outputs, to a gate of the auxiliary nMOS transistor, a second controlling signal that rises in synchronization with a rising of the second pulse signal and falls after a delay from a falling of the second pulse signal.

Abstract: A transmitter includes a power amplifier (PA) and a direct current (DC) voltage tuning circuit. The PA is arranged for receiving a radio-frequency (RF) clock derived from a clock source, and producing an output signal according to at least the RF clock. The DC voltage tuning circuit is arranged for tuning at least one DC voltage supplied to the PA for pulling mitigation of the clock source. A method of pulling mitigation of a source clock by a power amplifier (PA) includes adjusting a direct current (DC) voltage supplied to the PA.

Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

Abstract: An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device.

Abstract: A constant switching current flip-flop includes a latch circuit that provides latch outputs of the flip-flop, whereby the latch outputs are reset to zero at the beginning of each clock cycle to eliminate pattern dependent switching currents. The latch circuit is reset responsive to control signals provided without significant delay.

Abstract: Integrated circuits having analog-to-digital converters are provided. Analog-to-digital converters may contain latched comparators. A latched comparator may include inputs configured to receive a differential input voltage signal, a differential reference voltage signal, and a clock signal. The comparator may include a preamplifier, a latching circuit, a level shifter, and a flip-flop coupled in series. The preamplifier may include large input transistors for minimizing offset, stacked tail transistors, and diode-connected load transistors for minimizing kickback noise. The preamplifier may be used to generate amplified voltage signals. The latching circuit may include a first pair of cross-coupled pull-down transistors, a second pair of cross-coupled pull-up transistors, and precharge transistors.

Abstract: An apparatus, system, and method are provided for a differential integrated input circuit. The apparatus includes n-type semiconductor devices and p-type semiconductor devices. The p-type semiconductor devices are cross-coupled with the n-type semiconductor devices. Each of the p-type semiconductor devices biases a corresponding n-type semiconductor device.

Abstract: A frequency-voltage converting circuit 13 is composed of a switch unit including switches SW1 and SW2, electrostatic capacitive elements C and C10 to C13, and switches CSW0 to CSW3. The electrostatic capacitive elements C10 to C13 are composed of elements having mutually different absolute values of capacitance and are provided so as to cover a frequency range intended by a designer. The electrostatic capacitance values are weighted by, for example, 2. The electrostatic capacitive elements C11 to C13 are selected by, for example, the switches CSW0 to CSW3 based on 4-bit frequency adjustment control signals SELC0 to SELC3, thereby carrying out frequency switching.

Abstract: A semiconductor integrated circuit includes a first output driver configured to drive a first comparison signal, which is generated by comparing a voltage of a pad coupled to an external resistor with an upper-limit reference voltage, according to drivability determined by a pull-up code and a pull-down code, and output the driven signal as first output data; and a second output driver configured to drive a second comparison signal, which is generated by comparing the voltage of the pad with a lower-limit reference voltage, according to the drivability determined by the pull-up code and the pull-down code, and output the driven signal as second output data.

Abstract: An output circuit providing isolation between inputs and the output employs first and second opto-couplers for isolation. Pulse activation of the first opto-coupler turns on an output transistor and pulse activation of the second opto-coupler turns off the output transistor. An input stage of the output circuit is and light emitting devices of the first and second opto-couplers are powered by a first power source and an output stage of the output circuit is powered from an external power source. Power consumption by the input stage of output circuit occurs only during pulse activation of the first and second opto-couplers.

Abstract: A gate driver including: a first input; a first output driver having a first gate drive signal output, wherein the first output driver is connected to the first input; a second input; a second output driver having a second gate drive signal output, wherein the second output driver is connected to the second input; a first converter configured to convert an input voltage level to a first converted voltage level, wherein the converter receives an input voltage from a first high side gate driver output; a multiplexer with a first input connected to the first converter, a second input connected to a low side output, and an output; and an under voltage monitor connected to the output of the multiplexer.

Abstract: A multiplex driving circuit receives m master signals and n slave signals, and includes m driving modules for generating m×n gate driving signals. Each driving module includes a voltage boost stage and n driving stages. The voltage boost stage is used for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage. The n driving stages receives the n slave signals, respectively, and receives the first high voltage signal. In response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals.

Abstract: A driving circuit outputs an output voltage as a driving signal to the gate of a semiconductor element based on a control signal given from an input circuit. The output voltage is at “H” (ON level) if it is determined by a power supply voltage VCC, and is at “L” (OFF level) if it is determined by a ground voltage GND. A reference power supply section includes a series connection of resistors. The reference power supply section obtains a voltage determined by dividing a potential difference between the power supply voltage VCC and the ground voltage GND by a predetermined dividing ratio (resistance ratio between the resistors) as a reference voltage. A buffer circuit applies an output voltage as a reference signal determined by the reference voltage to the source of the semiconductor element.

Abstract: A drive waveform signal is pulse-modulated and a modulated signal is generated, the obtained modulated signal is power-amplified, and then, a drive signal is demodulated using a low pass filter. Thus obtained drive signal is negatively fed back, and thereby, the resonance peak of the low pass filter is suppressed. In this regard, by bringing gain in a wider frequency domain to take a fixed value or more, a drive signal having a voltage exceeding a power supply voltage may be stably generated.

Abstract: A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.

Abstract: Embodiments of a power-on and brown-out detector are described. In an embodiment, a power-on and brown-out detector for a power supply includes a power-on detection module, a brown-out detection module, and a logic module. The power-on detection module is connected to the power supply and is configured to generate a power-on signal in response to a voltage increase of the power supply. The brown-out detection module is connected to the power supply and is configured to generate a brown-out signal in response to a voltage charge by the power supply and a subsequent voltage decrease of the power supply. The logic module is configured to generate a control signal in response to the power-on signal and the brown-out signal. The power-on detection module is further configured to be activated or deactivated by the control signal. Other embodiments are also described.

Abstract: A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division.

Abstract: An integrated circuit with at least two LC-based phase-locked loop circuits and a high-speed serial interface circuit having multiple channels is provided. Each phase-locked loop circuit may include an oscillator having a varactor and multiple inductors. The oscillator may be configured to generate signals at different frequency ranges as determined by the inductors and the varactor. The LC-based phase-locked loop circuits may be produced such that all frequency ranges together provide the continuous coverage of an octave, thereby enabling the phase-locked loop circuits to generate a clock signal with high quality factors and desirable phase noise and jitter performance at an arbitrary frequency. Since the channels of the high-speed serial interface circuit may receive a clock signal having an arbitrary frequency, the high-speed serial interface circuit may be configured to support any communications protocol.

Abstract: This disclosure describes methods and techniques using Digital Phase Lock Loops (DPLLs) within a source chip to automatically phase align a plurality of clock signals at a plurality of clock pins on a plurality of target chips of varying distances and corresponding delays from the source chip by using each transmitted clock signal's reflected signal as a tuning reference.

Abstract: An integer-N phase-locked loop based clock generator for generating an output clock signal with a frequency N multiples of a reference clock signal, and a method for same, wherein N is a positive integer. The integer-N clock phase-locked loop based generator comprises a reference clock, a voltage controlled oscillator, a clock divider, a first and second phase generator for generating a plurality of phases of the reference clock signal and divided down output clock signal, a plurality of phase frequency detectors and charge pumps. The method comprises generating a reference clock and an output clock signals, generating a plurality of phases of a divided down output clock signal and reference clock signal, comparing the plurality of phases, and changing the frequency of the output clock signal based on the comparison.

Abstract: An apparatus comprises digitally controlled oscillator circuitry, feedback circuitry operatively coupled to the digitally controlled oscillator circuitry, and comparison circuitry operatively coupled to the digitally controlled oscillator circuitry and the feedback circuitry. The feedback circuitry, in response to a clock signal generated by the digitally controlled oscillator circuitry, generates a first digital value representing a detected phase of the clock signal for a given clock signal cycle. The comparison circuitry, in response to the first digital value and to a second digital value representing a reference phase, generates a phase error value. The phase error value is useable to generate a first digital control word provided to the digitally controlled oscillator circuitry for controlling a frequency associated with the clock signal.

Abstract: A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal.

Abstract: Multi-protocol driver slew rate calibration systems for calibrating slew rate control signal values are provided. Embodiments include generating, by a first phase rotator, a first clock signal; generating, by the second phase rotator, a second clock signal; initially setting, by a calibration controller, phase selector amounts such that the first clock signal is delayed relative to the second clock signal; determining whether the first clock signal is delayed relative to the second clock signal; if the first clock signal is delayed, changing the second phase selector amount; and if the first clock signal is not delayed, using the first clock signal and the second clock signal to calibrate values of control signals provided to control a slew rate of a calibration clock delay line such that the slew rate of the calibration clock delay line substantially matches a target slew rate.