Abstract: Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

Abstract: According to one embodiment, a semiconductor memory device includes first and second select transistors, memory cells, a driver circuit, first transfer transistors, and a detection circuit. The memory cells are stacked above a semiconductor substrate. The driver circuit outputs a first voltage. The first transfer transistors transfer the first voltage to associated word lines and select gate lines. In data erase, the detection circuit detects a second voltage applied to bit lines and/or a source line and generates a flag in accordance with the detection result. The driver circuit changes the value of the first voltage in response to the flag to cut off the first transfer transistors.

Abstract: A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories.

Abstract: A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines.

Abstract: According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases.

Abstract: A nonvolatile memory device is programmed by performing a plurality of program loops each comprising applying a program voltage to a selected wordline to change a threshold voltage of a selected memory cell, and applying a verification voltage to the selected wordline to verify a program state of the selected memory cell. In each program loop, the nonvolatile memory device determines a program condition and increments the program voltage by an amount determined according to the program condition.

Abstract: A semiconductor memory device having a read word line, a write word line and a sub-word driver operable to select the read word line using a main word signal and an inverse read block signal. The sub-word line selects the write word line using the main word signal and an inverse write block signal. The sub-word driver has a first inverter circuit using the main word signal as an input and outputting the read word line. The sub-word driver has a first transistor having a drain, a source, and a gate connected to the read word line, a low potential power source, and the inverse write block signal, respectively, and a second transistor having a drain, a source, and a gate connected to a power source terminal of the first inverter circuit, a power source, and the inverse write block signal, respectively, and can select the write word line.

Abstract: A memory string includes a semiconductor layer, a charge accumulation layer, and a conductive layer. The semiconductor layer extends in a direction perpendicular to the semiconductor substrate and functions as a body of a memory cell. The charge accumulation layer may accumulate charges. The conductive layer sandwiches the charge accumulation layer with the semiconductor layer, and functions as a gate of the memory cell. The control circuit performs, before a read operation, a refresh operation of rendering the selected memory cell and a non-selected memory cell conductive to conduct a current from a first end to a second end of the memory string.

Abstract: A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a n-type floating gate, a coupling gate, a first n-type source/drain, a second n-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a p-type semiconductor substrate. The n-type floating gate is formed on the gate dielectric layer. The first n-type source/drain and the second n-type source/drain are formed in the p-type semiconductor substrate. The first and second contact plugs are formed on the first and second n-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the n-type floating gate, and the third contact plug is formed on the capacitor dielectric layer.

Abstract: Methods and systems are disclosed for erasing split-gate non-volatile memory (NVM) cells using select-gate erase voltages that are adjusted to reduce select-gate to control-gate break-down failures. The adjusted select-gate erase voltages provide bias voltages on the select-gates that are configured to have the same polarity as the control-gate erase voltages applied during erase operations and that are different from select-gate read voltages applied during read operations. Certain additional embodiments use discrete charge storage layers for the split-gate NVM cells and include split-gate NVM cells having gap dielectric layer thicknesses that are dependent upon control gate dielectric layer widths.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract: Data stripes and addressing for flash memory devices are provided. Flash memory devices illustratively have a plurality of programmable devices that are capable of simultaneously storing data. A plurality of erasure blocks are within each of the programmable devices, and each erasure block has pages of transistors. The flash memory devices are logically organized as a plurality of stripes. Each stripe has a height and a width. In an embodiment, the stripe height is greater than one page. In another embodiment, the stripe width is less than all of the programmable devices within the flash memory device.

Abstract: Embodiments relate to a method for representing data in a graphene-based memory device. The method includes applying a first voltage to a back gate of a graphene-based memory device and a second voltage to a first graphene layer of the graphene-based memory device. The graphene-based memory device includes the first graphene layer and a second graphene layer and a first insulation layer located between the first and second graphene layers. The first insulation layer has an opening between the first and second graphene layers. The back gate is located on an opposite side of the second graphene layer from the first insulation layer. The first graphene layer is configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the back gate.

Abstract: According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract: A semiconductor apparatus includes: a memory cell block configured to store data; a fuse block including a plurality of fuses configured to store fuse information; an I/O driver configured to output the data transmitted through a global line to a pad; and a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode.

Abstract: A bidirectional shift register includes a first register circuit and a second register circuit. The first register circuit includes a first register stage and a first output buffer stage with n numbers of scanning signal output ends. The first register stage is electrically coupled to a third voltage source. The first output buffer stage is electrically coupled to a second voltage source and a first voltage source. The second register circuit has a similar circuit structure to the first register circuit; wherein the first register circuit and the second register circuit each use n+1 numbers clock signal lines, and the n is a positive integer.

Abstract: To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.

Abstract: Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises, for each memory device of a plurality of memory devices, based on testing performed on the memory device, determining whether the memory device has any defective memory locations, and if so, identifying the one or more defective memory locations, and generating data that identifies the one or more defective memory locations on the memory device; and assembling a memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises, for each memory device of the memory module having one or more defective memory locations, storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module.

Abstract: A semiconductor integrated circuit includes an internal reference voltage generation unit configured to generate an internal reference voltage; a high voltage generation unit configured to pump an external driving voltage based on the internal reference voltage applied from the internal reference voltage generation unit, and generate a high voltage having a specified level; and a reference voltage transfer unit configured to generate a test reference voltage from a reference voltage in a package test mode to correspond to a change in a driving operation of the external driving voltage applied from outside, and monitor and force the internal reference voltage.

Abstract: A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation.

Abstract: A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.

Abstract: A voltage supply circuit includes a high voltage generator configured to generate an operating voltage, a global word line switch configured to transfer the operating voltage to global word lines, a plurality of local line switches coupled to the global word lines and configured to transfer the operating voltage to corresponding local word lines, a precharge unit configured to supply a precharge voltage to an unselect local line switch adjacent to a select local line switch to which the operating voltage will be supplied, from among the plurality of local line switches, in a preparation section before an operation is started, and a coupling unit configured to couple the unselect local line switch and the global word line switch when the operation is started.

Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.

Abstract: A system and method to select a reference cell is disclosed. In a particular embodiment, a method is disclosed that includes receiving an address corresponding to a bit cell within a first bank of a memory. The method also includes accessing a second reference cell of a second bank of the memory in response to a first reference cell in the first bank being indicated as bypassed.

Abstract: Disclosed herein is a storage control device that includes a temperature sensor, temperature information selection section, refresh command reception section and trigger issuance frequency setting section.

Abstract: Disclosed herein is a semiconductor device having self-refresh modes in which a refresh operation of storage data is periodically performed asynchronously with an external clock signal. The semiconductor device performs the refresh operation on n memory cells in response to an auto-refresh command. The semiconductor device periodically performs the refresh operation on m memory cells included in the memory cell array during the self-refresh mode, where m is smaller than n.

Abstract: A system for controlling a refresh operation of a plurality of stacked semiconductor chips includes a first semiconductor configured to output a refresh signal for performing a refresh operation, and a semiconductor chip discrimination signal, and a plurality of second semiconductor chips configured to perform a refresh operation at different timings in response to the refresh signal, and the semiconductor chip discrimination signal.

Abstract: A semiconductor memory device includes a first fuse having one end coupled with a first bit line and configured to be programmed with a data, a second fuse having one end coupled with a second bit line and configured to be programmed with the data; a program controller coupled with the other ends of the first fuse and the second fuse and configured to perform a program operation on at least one of the first fuse and the second fuse in response to a program voltage, and a read controller coupled with the other ends of the first fuse and the second fuse and configured to perform a read operation on the first fuse and the second fuse in response to a read voltage.

Abstract: A bitcell can include an insulating area, a first doping, a second doping, and a gate terminal for the insulating area. The second doping can be proximate to the first doping and proximate to the insulating area. The second doping can be characterized by a lower threshold voltage than the first doping. The bitcell can be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating area between the gate terminal and the first doping.

Abstract: An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.

Abstract: A dual rail memory operable at a first voltage and a second voltage includes an input circuit, an output circuit and a clock generator circuit coupled with the input circuit. The input circuit is operable to receive at least a first input signal referenced to the first voltage and to generate a second input signal referenced to the second voltage. The output circuit is operable to receive at least a first output signal referenced to the second voltage and to generate a second output signal referenced to the first voltage. The clock generator circuit is operable to receive a first clock signal referenced to the first voltage and to generate a second clock signal referenced to the second voltage, a logic state of the second clock signal being a function of a logic state of the first clock signal.

Abstract: A data storage system is disclosed including a data storage device having a controller coupled to non-volatile semiconductor memory and a power device having a common power rail and first, second, and third spindle phase switching elements, the common power rail receiving an input voltage and providing power to the data storage device and the power device. The data storage system further includes an inductor coupled between outputs of the first and second spindle phase switching elements, and a charge storage element coupled between the second spindle phase switching element output and ground. The power device further includes control circuitry that controls the first and second spindle phase switching elements to generate boost output voltage for charging the charge storage element during a boost mode, the boost output voltage enabling the controller to perform a data operation in an event of an interruption of power to the data storage system.

Abstract: A memory operative to provide concurrent two-port read and two-port write access functionality includes a memory array comprising first and second pluralities of single-port memory cells organized into a plurality of rows of memory banks, and multiple checksum modules. The second plurality of memory cells are operative as spare memory banks. Each of the checksum modules is associated with a corresponding one of the rows of memory banks. The memory further includes a first controller and multiple mapping tables. The first controller and at least a portion of the first and second pluralities of memory cells enable the memory array to support two-port read or single-port write operations. A second controller is operative to receive read and write access requests, and to map logical and spare memory bank identifiers to corresponding physical memory bank identifiers via the mapping tables to thereby emulate concurrent two-port read and two-port write access functionality.

Abstract: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.

Abstract: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.

Abstract: Methods for determining by acoustic ranging relative positions of marine seismic streamers in a network of streamers are described, as well as streamer configurations and systems which overcome weak or non-existent acoustic positioning signals. The acoustic network includes a plurality of acoustic transceiver pairs, and the methods include implementing a network solution-based reconfiguration of the acoustic transceiver pairs. When the network of streamers changes more than a critical amount, the network is reconfigured, the critical amount being when the network solution-based reconfiguration is no longer adequate to provide enough acoustic signals to give reasonable relative positions of the acoustic transceiver pairs in the network due to their spatial relation.

Abstract: A method and apparatus for correcting an input seismic trace. The method includes receiving the input seismic trace and creating a t by Q gather using the input seismic trace, where t represents traveltime, Q represents absorption parameter, and the t by Q gather has traveltime as the vertical axis and a ratio of t and Q as the horizontal axis. The ratio of t and Q is referred to as R. The method further includes applying an interpolation algorithm to the t by Q gather to derive a corrected input seismic trace.

Abstract: Method for separating signals recorded by a seismic receiver and generated with at least two vibratory seismic sources driven with no listening time. The method includes receiving seismic data that includes data d recorded by the seismic receiver and data related to the first and second vibratory seismic sources; computing a source separation matrix based on the data related to the first and second vibratory seismic sources; calculating first and second earth impulse responses HA and HB corresponding to the two vibratory seismic sources, respectively, based on the data d recorded by the seismic receiver, the data related to the two vibratory seismic sources and the source separation matrix; and separating the signals recorded by the seismic receiver based on the first and second earth impulse responses HA and HB such that signals the two vibratory seismic sources are disentangled.

Abstract: Techniques are disclosed for performing time-lapse monitor surveys with sparsely sampled monitor data sets. An accurate 3D representation (e.g., image) of a target area (e.g., a hydrocarbon bearing subsurface reservoir) is constructed (12) using the sparsely sampled monitor data set (11). The sparsely sampled monitor data set may be so limited that it alone is insufficient to generate an accurate 3D representation of the target area, but accuracy is enabled through use of certain external information (14). The external information may be one or more alternative predicted models (25) that are representative of different predictions regarding how the target area may change over a lapse of time. The alternative models may, for example, reflect differences in permeability of at least a portion of the target area. The sparsely sampled monitor data set may then be processed to determine (23) which of the alternative models is representative of the target area.

Abstract: A retrograde display mechanism of a timepiece includes a retrograde display mechanism main body having a time value driving wheel that rotates once every day and that has a time value finger which advances a time value including a date or a day. A time value transmitting wheel has a time value transmitting wheel tooth portion and a drive cam portion which are rotated by one tooth every day by the time value finger. A fan-shaped wheel operating lever has a cam follower portion and a fan-shaped wheel operating tooth portion engaged with the drive cam portion, and a fan-shaped wheel and a fan-shaped wheel display portion which mesh with the fan-shaped wheel operating tooth portion to rotate in response to rocking of the operating lever. The fan-shaped wheel rapidly rotates reversely to return to an initial position whenever the end of the month or the end of the week passes.

Abstract: A temperature-compensated resonator includes a body used in deformation, wherein the core (58, 58?, 18) of the body (3, 5, 7, 15, 23, 25, 27, 33, 35, 37, 43, 45, 47) is formed from a plate formed at a cut angle (??) in a quartz crystal determining the first and second orders temperature coefficients (?, ?, ??, ??). According to the invention, the body (3, 5, 7, 15, 23, 25, 27, 33, 35, 37, 43, 45, 47) includes a coating (52, 54, 56, 52?, 54?, 56?, 16) deposited at least partially on the core (58, 58?, 18) and having first and second orders Young's modulus variations (CTE1, CTE2, CTE1?, CTE2?) according to temperature of opposite signs respectively to the first and second orders temperature coefficients (?, ?, ??, ??) of the resonator so as to render compensated first and second orders temperature coefficients substantially zero.

Abstract: The invention relates to a timepiece with an analogue display, including a timepiece movement (1) provided with a mechanical output, located on an arbour (2) of said movement, and a display assembly (30) provided with at least one time display device (31, 32, 111, 112) driven by said mechanical output, wherein the display assembly is separate from the timepiece movement (1) and linked to a fixed part (10) of said movement (1) by support means which enables said display device to take several different positions around the output arbour (2) of the movement. According to the invention, the support means of the display assembly includes an intermediate support (34, 70, 72, 70?) secured to the fixed part (10) of the timepiece movement (1) and provided with support members (36, 87, 89, 87?, 89?) allowing said at least one display device (31, 32, 111, 112) to be assembled in several positions on the intermediate support (34, 70, 72, 70?). The invention concerns the field of timepiece display members.

Abstract: A timed vibrating system for habit programming featuring a microprocessor, a vibrator, and a battery. A switch allows a user to control whether or not the vibration of the vibrator is audible. A cap on the housing allows a user to control the frequency with which the vibrator vibrates. Each vibration, or alert, reminds the user to clear his thoughts and rid his mind of worry so that he can maintain a positive outlook on his disease. The system can be worn on the user's body, for example around his neck on in his pocket.

Abstract: A magnetic recording system including follows: a recording head, a recording medium that includes a first recording medium layer, a second recording medium layer, and a substrate. The magnetic recording system includes an electric field applying device applying an electric field and a magnetic field applying device applying a magnetic field to the recording medium, a movement mechanism that moves them to an arbitrary position. The magnetic recording system has a function of controlling an applying direction of at least one of the electric field applying device and the magnetic field applying device, and the recording head is arranged at a position facing the recording medium.

Abstract: According to one embodiment, in a magnetic disk, a reflecting layer with a higher reflectance to near-field light than a magnetic recording layer is provided in the magnetic recording layer so as to be flat. A magnetic head performs magnetic recording on the magnetic recording layer while locally heating the magnetic recording layer based on the near-field light.

Abstract: An audiovisual distribution system includes a central server and a plurality of audiovisual units. Each unit includes structure for interactively communicating with the user for selecting a piece or a menu, a payment device, a computer network card, and a permanent semiconductor memory containing a multitask operating system comprising at least a hard disc access management task. The order for performing a selected piece is processed as a hard disc sequential access task. The hard disc is declared as a peripheral corresponding to the network card of the unit, enabling a request to be sent through the network to the server for processing.

Abstract: Address information that has been error correction encoded is recorded on a second version of a recording medium after being transformed such that such that the address decoding cannot be performed by a playback device that is not compatible with the second version of the recording medium. The address decoding for the second version of the recording medium cannot be performed by the incompatible playback device (for example, a playback device that was manufactured to be compatible only with a first version of the recording medium). In other words, in the playback device that is not compatible with the second version of the recording medium, a state is created in which address errors cannot be corrected, so access is impossible (recording and playback are impossible).

Abstract: A machine readable information storage medium, a reproducing method and apparatus which reproduces data from the storage medium, and a recording method and apparatus for recording data on the storage medium. The information storage medium includes a control area which stores within a data structure information usable by the recording or reproducing apparatus to record or reproduce the data on or from the storage medium. The information stored within the data structure includes a version corresponding to a specification, a revision number of recording speed, and an extended part version field.

Abstract: In an optical recording method, recording parameters (WU) to be used for recording are obtained using recommended recording parameter values (WR) read from an optical recording medium and previously obtained vector information (PC) and approximation coefficients (Ca, Cb) (S24). Writing to the optical recording medium is performed using the obtained recording parameters (S17). The vector information (PC) includes a vector component of the parameters obtained statistically with respect to parameter difference values (DF) between optimal recording parameter values (WO) and the recommended recording parameter values (WR) over a plurality of optical recording media so as to strengthen mutual correlation between the parameters.