Patents Issued in June 10, 2014
  • Patent number: 8748294
    Abstract: There is provided an SOS substrate with reduced stress. The SOS substrate is a silicon-on-sapphire (SOS) substrate comprising a sapphire substrate and a monocrystalline silicon film on or above the sapphire substrate. The stress of the silicon film of the SOS substrate as measured by a Raman shift method is 2.5×108 Pa or less across an entire in-plane area of the SOS substrate.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: June 10, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Shoji Akiyama
  • Patent number: 8748295
    Abstract: Test structures for semiconductor devices, methods of forming test structures, semiconductor devices, methods of manufacturing thereof, and testing methods for semiconductor devices are disclosed. In one embodiment, a test structure for a semiconductor device includes at least one first contact pad disposed in a first material layer in a scribe line region of the semiconductor device. The at least one first contact pad has a first width. The test structure also includes at least one second contact pad disposed in a second material layer proximate the at least one first contact pad in the first material layer. The at least one second contact pad has a second width that is greater than the first width.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Erdem Kaltalioglu, Matthias Hierlemann
  • Patent number: 8748296
    Abstract: A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In one embodiment, the method includes forming an edge exclusion material on an upper surface and near an edge of a base substrate. A stressor layer is then formed on exposed portions of the upper surface of the base substrate and atop the edge exclusion material, A portion of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana, Davood Shahrjerdi, Norma E. Sosa Cortes
  • Patent number: 8748297
    Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gudrun Stranzl, Martin Zgaga, Markus Kahn, Guenter Denifl
  • Patent number: 8748298
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: June 10, 2014
    Assignee: International Rectifier Corporation
    Inventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal
  • Patent number: 8748299
    Abstract: A semiconductor device includes an isolation layer pattern, an epitaxial layer pattern, a gate insulation layer pattern and a gate electrode. The isolation layer pattern is formed on a substrate, and defines an active region in the substrate. The isolation layer pattern extends in a second direction. The epitaxial layer pattern is formed on the active region and the isolation layer pattern, and has a width larger than that of the active region in a first direction perpendicular to the second direction. The gate insulation layer pattern is formed on the epitaxial layer pattern. The gate electrode is formed on the gate insulation layer pattern.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Suk Shin
  • Patent number: 8748300
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Megumi Ishiduki, Ryota Katsumata, Tomo Ohsawa, Mitsuru Sato, Masaru Kidoh, Hiroyasu Tanaka
  • Patent number: 8748301
    Abstract: Provided are: a diffusing agent composition for ink-jet; a method for production of electrode and solar battery using the diffusing agent composition; and a solar battery produced by the method for production. The diffusing agent composition for ink-jet includes (a) a silicon compound, (b) an impurity-diffusing component and (c) a solvent, in which: the solvent (c) contains (c1) a solvent having a boiling point of no higher than 100° C. and (c2) a solvent having a boiling point of 180 to 230° C.; and the solvent (c1) is contained at a ratio of 70 to 90% by mass and the solvent (c2) is contained at a ratio of 1 to 20% by mass both relative to the total mass of the composition.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: June 10, 2014
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Toshiro Morita, Katsuya Tanitsu
  • Patent number: 8748302
    Abstract: In a replacement gate approach, the dielectric material for laterally encapsulating the gate electrode structures may be provided in the form of a first interlayer dielectric material having superior gap filling capabilities and a second interlayer dielectric material that provides high etch resistivity and robustness during a planarization process. In this manner, undue material erosion upon replacing the placeholder material may be avoided, which results in reduced yield loss and superior device uniformity.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: June 10, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Christopher M. Prindle, Johannes F. Groschopf, Andreas R. Ott
  • Patent number: 8748303
    Abstract: A method for fabricating a semiconductor device includes forming ohmic electrodes on a source region and a drain region of a nitride semiconductor layer, forming a low-resistance layer between an uppermost surface of the nitride semiconductor layer and the ohmic electrodes by annealing the nitride semiconductor layer, removing the ohmic electrodes from at least one of the source region and the drain region after forming the low-resistance layer, and forming at least one of a source electrode and a drain electrode on the low-resistance layer, the at least one of a source electrode and a drain electrode having an edge, a distance between the edge and a gate electrode is longer than a distance between an edge of the low-resistance layer and the gate electrode.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: June 10, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Shinya Mizuno
  • Patent number: 8748304
    Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive thick film composition for use in a solar cell device.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: June 10, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Haixin Yang, Roberto Irizarry, Patricia J. Ollivier
  • Patent number: 8748305
    Abstract: A semiconductor device is provided which includes a semiconductor substrate having a plurality of microelectronic elements formed therein; an interconnect structure formed over the substrate, the interconnect structure including metal layers isolated from one another by an inter-metal dielectric, the metal layers including a topmost metal layer; dummy metal vias formed between at least two metal layers and disposed within a region of the interconnect structure; and a bonding pad formed over the topmost metal layer such that the bonding pad is aligned with the region of the interconnect structure.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 8748306
    Abstract: A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Yang Lei, Hung-Jui Kuo, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu
  • Patent number: 8748307
    Abstract: A method for processing a wafer in accordance with various embodiments may include: forming a passivation over the wafer; forming a protection layer over at least a surface of the passivation facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation; forming a mask layer over at least a surface of the protection layer facing away from the wafer, wherein the mask layer includes a material that is selectively etchable to the material of the protection layer; etching the wafer using the mask layer as a mask; selectively etching the material of the mask layer to remove the mask layer from the protection layer, after etching the wafer; and selectively etching the material of the protection layer to remove the protection layer from the passivation, after selectively etching the material of the mask layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Joachim Hirschler, Gudrun Stranzl
  • Patent number: 8748308
    Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Alvin J. Joseph, Anthony K. Stamper
  • Patent number: 8748309
    Abstract: Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 10, 2014
    Assignees: GLOBALFOUNDRIES, Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 8748310
    Abstract: A method for producing a metal contact structure of a photovoltaic solar cell, including: applying an electrically non-conductive insulating layer to a semiconductor substrate, applying a metal contact layer to the insulating layer, and generating a plurality of local electrically conductive connections between the semiconductor substrate and the contact layer right through the insulating layer. The metal contact layer is formed using two pastes containing metal particles: the first paste containing metal particles is applied to local regions, and the second paste containing metal particles is applied covering at least the regions covered with the first paste and partial regions located therebetween.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: June 10, 2014
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung E.V.
    Inventors: Daniel Biro, Benjamin Thaidigsmann, Florian Clement, Robert Woehl, Edgar-Allan Wotke
  • Patent number: 8748311
    Abstract: Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: William M. Hiatt, Kyle K. Kirby
  • Patent number: 8748312
    Abstract: A method of manufacturing a substrate for mounting an electronic device, includes forming at least one through-hole in a plate-shaped substrate body in a thickness direction thereof. An electrode substrate having at least one core on an upper surface thereof is formed such that the at least one core corresponds to the at least one through-hole. The electrode substrate is coupled to the substrate body by inserting the at least one core into the at least one through-hole. A portion of the coupled electrode substrate is removed except for the at least one core.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Wan Seo, Hyung Kun Kim
  • Patent number: 8748313
    Abstract: A method for making a mask for semiconductor manufacturing. The method includes providing a base layer, forming a conductive layer on the base layer, and forming a photoresist layer on the conductive layer. Additionally, the method includes exposing selectively the photoresist layer to an energy illumination, developing the photoresist layer by removing a first portion of the photoresist layer, and depositing a metal layer by an electroforming process. The electroforming process includes submerging the conductive layer into a chemical bath, and applying a deposition voltage across a negative electrode and a positive electrode. Moreover, the method includes removing a second portion of the photoresist layer, and removing a first portion of the conductive layer.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: June 10, 2014
    Assignees: Semiconductor Manufaturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Hsin Chin Chen
  • Patent number: 8748314
    Abstract: There is provided a method of manufacturing a semiconductor device, which includes forming a TiN film as a hard mask directly on a second p-SiCOH film formed on a substrate, forming an opening passing through the TiN film and the second p-SiCOH film by photolithography and etching, cleaning the inside of the opening, removing the TiN film after cleaning the inside, and forming a second metal film filling the opening directly on the second p-SiCOH film after removing the TiN film.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuya Usami
  • Patent number: 8748315
    Abstract: The present disclosure relates to a method of forming a back-side illuminated CMOS image sensor (BSI CIS). In some embodiments, the method comprises forming a plurality of photodetectors within a front-side of a semiconductor substrate. An implant is performed on the back-side of the semiconductor substrate to form an implantation region having a doping concentration that is greater in the center than at the edges of the semiconductor substrate. The back-side of the workpiece is then exposed to an etchant, having an etch rate that is inversely proportional to the doping concentration, which thins the semiconductor substrate to a thickness that allows for light to pass through the back-side of the substrate to the plurality of photodetectors. By implanting the substrate prior to etching, the etching rate is made uniform over the back-side of the substrate improving total thickness variation between the photodetectors and the back-side of the substrate.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: En-Ting Lee, Kun-El Chen, Yu-Sheng Wang, Chien-Chung Chen, Huai-Tei Yang
  • Patent number: 8748316
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes polishing a peripheral portion of the semiconductor substrate, and forming a protective film to be an insulating film, on a surface of the semiconductor substrate including a surface exposed by the polishing.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Shirono, Mie Matsuo, Hideo Numata, Kazumasa Tanida, Tsuyoshi Matsumura
  • Patent number: 8748317
    Abstract: A dielectric layer is deposited on a working surface of a substrate, wherein the dielectric layer contains or consists of a dielectric polymer. The dielectric layer is partially cured. A portion of the partially cured dielectric layer is removed using a chemical mechanical polishing process. Then the curing of remnant portions of the partially cured dielectric layer is continued to form a dielectric structure. The partially cured dielectric layer shows high removal rates during chemical mechanical polishing. With remnant portions of the dielectric layer provided in cavities, high volume insulating structures can be provided in an efficient manner.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Schmidt, Daniel Schloegl, Marcella Johanna Hartl, Philipp Sebastian Koch, Roland Strasser
  • Patent number: 8748318
    Abstract: The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a radiation-imageable layer over a material. A lattice pattern is then formed within the radiation-imageable layer, with the lattice pattern defining a plurality of islands of the radiation-imageable layer. The lattice-patterned radiation-imageable layer is utilized as a mask while subjecting the material under the lattice-patterned layer to an etch which transfers the lattice pattern into the material. The etch forms a plurality of pillars which extend only partially into the material, with the pillars being spaced from one another by gaps. The gaps are subsequently narrowed with a second material which only partially fills the gaps.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8748319
    Abstract: Embodiments of the invention may provide a method of printing one or more print tracks on a print support, or substrate, comprising two or more printing steps in each of which a layer of material is deposited on the print support according to a predetermined print profile. In each printing step, subsequent to the first step, each layer of material is deposited at least partially on top of the layer of material printed in the preceding printing step, so that each layer of printed material has an identical or different print profile with respect to at least a layer of material underneath. The method may further comprise depositing material in each printing step that is equivalent to or different from the material deposited in at least one of other the print layers.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: June 10, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Marco Galiazzo, Andrea Baccini, Giorgio Cellere, Luigi De Santi, Gianfranco Pasqualin, Tommaso Vercesi
  • Patent number: 8748320
    Abstract: A method of connecting to a first metal layer in a semiconductor flow process. Disclosed embodiments connect to the first metal layer by etching a first portion of a viahole through an etch stop layer and a gate insulation layer to reach a first metal layer, depositing a second metal layer such that the second metal layer contacts the first metal layer within the viahole, and etching a second portion of the viahole through a first passivation layer and an organic layer to reach the second metal layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 10, 2014
    Assignee: Apple Inc.
    Inventors: Ming-Chin Hung, Young Bae Park, Chun-Yao Huang, Shih Chang Chang, John Z. Zhong
  • Patent number: 8748321
    Abstract: Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Anton deVilliers, Erik Byers, Scott E. Sills
  • Patent number: 8748322
    Abstract: A method of etching silicon oxide from a trench is described which allows more homogeneous etch rates across a varying pattern on a patterned substrate. The method also provides a more rectilinear profile following the etch process. Methods include a sequential exposure of gapfill silicon oxide. The gapfill silicon oxide is exposed to a local plasma treatment prior to a remote-plasma dry etch which may produce salt by-product on the surface. The local plasma treatment has been found to condition the gapfill silicon oxide such that the etch process proceeds at a more even rate within each trench and across multiple trenches. The salt by-product may be removed by raising the temperature in a subsequent sublimation step.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: June 10, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Nancy Fung, David T. Or, Qingjun Zhou, Lina Zhu, Jeremiah T. Pender, Srinivas D. Nemani, Sean S. Kang, Sergey G. Belostotskiy, Chinh Dinh
  • Patent number: 8748323
    Abstract: A patterning method is provided. First, a substrate having an objective material layer thereon is provided. Thereafter, a mask layer is formed on the objective material layer. Afterwards, a patterned layer is formed over the mask layer, wherein a material of the patterned layer includes a metal-containing substance. Then, the mask layer is patterned to form a patterned mask layer. Further, the objective material layer is patterned, using the patterned mask layer as a mask.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: June 10, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Han-Hui Hsu, Shih-Ping Hong, An-Chi Wei, Ming-Tsung Wu
  • Patent number: 8748324
    Abstract: Systems and methods for separating components of a multilayer stack of electronic components. The multilayer stack includes an electronic assembly, a substrate, and a sacrificial anode portion that is located between the electronic assembly and the substrate and that operatively attaches the electronic assembly to the substrate. The systems and methods may include locating the multilayer stack within an electrically conductive fluid to form an electrochemical cell. The systems and methods further may include generating a potential difference between a cathode portion of the electronic assembly and the sacrificial anode portion such that the cathode portion forms a cathode of the electrochemical cell and the sacrificial anode portion forms an anode of the electrochemical cell.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: June 10, 2014
    Assignee: The Boeing Company
    Inventors: Robyn L. Woo, Xiaobo Zhang, Christopher M. Fetzer, Eric M. Rehder
  • Patent number: 8748325
    Abstract: A polyimide film is effectively formed on a complicated surface. The polyimide film is formed by reacting, on the surface, diamine monomer and tetracarboxylic acid dianhydride monomer both of which are dissolved within carbon dioxide in a supercritical states, together with a polyamic acid resulting from a reaction between the diamine monomer and the tetracarboxylic acid dianhydride reached to the surface.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 10, 2014
    Inventors: Mitsuhiro Horikawa, Hiroyuki Ode, Masashi Haruki, Shigeki Takishima, Shinichi Kihara
  • Patent number: 8748326
    Abstract: Provided is a forming device and method making it possible to obtain a low-temperature polysilicon film in which the size of crystal grains fluctuates minimally, and is uniform. A mask has laser-light-blocking areas and laser-light-transmission areas arranged in the form of a grid such that the light-blocking areas and transmission areas are not adjacent to one another. Laser light is directed by the microlenses through the masks to planned channel-area-formation areas. The laser light transmitted by the transmission areas is directed onto an a-Si:H film, annealing and polycrystallizing the irradiated parts thereof. The mask is then removed, and when the entire planned channel-area-formation area is irradiated with laser light, the already-polycrystallized area, having a higher melting point, does not melt, while the area in an amorphous state melts and solidifies, leading to polycrystallization.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: June 10, 2014
    Assignee: V Technology Co., Ltd.
    Inventors: Koichi Kajiyama, Kuniyuki Hamano, Michinobu Mizumura
  • Patent number: 8748327
    Abstract: Disclosed are lead free glass frit powder for manufacturing a silicon solar cell, its producing method, a metal paste composition containing the same and a silicon solar cell. The lead free glass frit powder for manufacturing a silicon solar cell includes Bi2O3; B2O3; and any one metal oxide selected from the group consisting of ZnO, Al2O3 and BaCO3, or mixtures thereof. The glass frit powder is free of lead, and thus, it is environmental friendly. A front electrode of a solar cell formed using the glass frit powder has low resistance against contact with a substrate and high adhesion to the substrate.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: June 10, 2014
    Assignee: LG Chem, Ltd.
    Inventors: Jong-Wuk Park, Min-Seo Kim, Jong-Taik Lee
  • Patent number: 8748328
    Abstract: An optical glass having a refractive index nd of 1.70 or greater and an Abbé number of 50 or greater. Given as mole percentages, it comprises: B2O3 (20 to 80 percent), SiO2 (0 to 30 percent), Li2O (1 to 25 percent), ZnO (0 to 20 percent), La2O3 (4 to 30 percent), Gd2O3 (1 to 25 percent), Y2O3 (0 to 20 percent), ZrO2 (0 to 5 percent), MgO (0 to 25 percent), CaO (0 to 15 percent), and SrO (0 to 10 percent), with the combined quantity of the above components being 97 percent or greater. The molar ratio of {ZnO/(La2O3+Gd2O3+Y2O3)} is 0.8 or less and the molar ratio of {(CaO+SrO+BaO)/(La2O3+Gd2O3+Y2O3)} is 0.8 or less. Ta2O5 may be incorporated as an optional component, with the molar ratio {(ZrO2+Ta2O5)/(La2O3+Gd2O3+Y2O3)} being 0.4 or less.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: June 10, 2014
    Assignee: Hoya Corporation
    Inventor: Yasuhiro Fujiwara
  • Patent number: 8748329
    Abstract: A dielectric ceramic composition that contains, as its main constituent, (Ba1-x-yCaxSry)(Ti1-z-wZrzHfw)O3 (in the formula, 0?x+y?0.2, 0?z+w?0.1), and contains CuO and Bi2O3, and the dielectric ceramic composition has a feature that the total content of the CuO and Bi2O3 is 10 parts by weight or more with respect to 100 parts by weight of the main constituent, and the molar ratio CuO/(CuO+Bi2O3) is 0.5 or less.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 10, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masanori Nakamura, Masahiro Otsuka, Shoichiro Suzuki, Koichi Banno, Taisuke Kanzaki, Akihiro Shiota
  • Patent number: 8748330
    Abstract: This disclosure provides methods of making an enhanced activity nanostructured thin film catalyst by radiation annealing, typically laser annealing, typically under inert atmosphere. Typically the inert gas has a residual oxygen level of 100 ppm. Typically the irradiation has an incident energy fluence of at least 30 mJ/mm2. In some embodiments, the radiation annealing is accomplished by laser annealing. In some embodiments, the nanostructured thin film catalyst is provided on a continuous web.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: June 10, 2014
    Assignee: 3M Innovative Properties Company
    Inventors: Mark K. Debe, Robert L. W. Smithson, Charles J. Studiner, IV, Susan M. Hendricks, Michael J. Kurkowski, Andrew J. L. Steinbach
  • Patent number: 8748331
    Abstract: A method of manufacturing a remediation material uses a biogenic material as a substrate and involves preparing the surface of the substrate to enable a chemical reaction, and performing template-driven surface derivatization on the substrate to provide a net positive charge on the substrate. The remediation material may be placed into contact with surface water, ground water, soil, or sediment by at least one of a permeable reactive barrier, direct well injection, or direct introduction of the remediation material into soil or sediment, to remove contaminants from the surface water, ground water, soil, or sediment.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: June 10, 2014
    Assignee: The United States of America as Represented by the Secretary of the Army
    Inventors: Jeffrey W. Talley, Steven Larson, Lawrence G. Wolfe, Brian D. Fisher
  • Patent number: 8748332
    Abstract: Provided is a method for cleaning a used denitration catalyst, which prevents release of mercury to the atmosphere by collecting and removing mercury which would have been released to the atmosphere in the process of cleaning the used denitration catalyst. The method comprises immersing the used denitration catalyst mainly composed of titanium oxide and having been used in exhaust gas containing mercury in a cleaning liquid, and stirring the cleaning liquid to dissolve and remove catalyst poisons including the mercury from the used denitration catalyst, wherein a waste gas generated in the step of stirring the cleaning liquid is conducted to a flue having a mercury removal device so as to remove the mercury, and then vented to the atmosphere.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: June 10, 2014
    Assignee: Babcock-Hitachi Kabushiki Kaisha
    Inventors: Seiji Ikemoto, Yasuyoshi Kato, Keiichiro Kai
  • Patent number: 8748333
    Abstract: Surface-modified zeolites and methods for preparing surface-modified zeolites are provided. A hybrid polymer formed from a silicon alkoxide and a metal alkoxide, a co-monomer, or both, is contacted with a zeolite suspension. The zeolite suspension comprises a sodium-, an ammonium-, or a hydrogen-form zeolite and a solvent. The hybrid polymer and zeolite suspension are contacted under conditions sufficient to deposit hybrid polymer on external surfaces of the zeolite to form a treated zeolite. Solvent is removed therefrom. The treated zeolite is dried and calcinated to form a dried and calcinated treated zeolite. Forming of the zeolite suspension and the contacting, removing, drying, and calcinating steps are provided in one selectivation sequence to produce a surface-modified zeolite from the ammonium-form zeolite and the hydrogen-form zeolite. If the dried and calcinated treated zeolite is a sodium-form zeolite, the sodium is exchanged with ammonium and then additionally dried and calcinated.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: June 10, 2014
    Assignee: UOP LLC
    Inventors: Laszlo T. Nemeth, Feng Xu
  • Patent number: 8748334
    Abstract: This invention provides a process for producing an electrode catalyst for a fuel cell, comprising a first support step of producing metallic fine particles having an average particle diameter of 0.1 to 1.5 nm provided at regulated particle intervals on an electroconductive carbon carrier, and a second support step of growing a metal identical to or dissimilar to the metal using the metallic fine particles as a nucleus. In the first support step, the metallic fine particles are supported by an immersion method. The above constitution can provide an electrode catalyst for a fuel cell, which has a high level of percentage support, has a high level of dispersibility, and has improved methanol oxidation activity per weight of the catalyst. Further, when treatment in an atmosphere containing hydrogen is carried out at a low temperature below 100° C., the methanol oxidation activity per active surface area can be improved without lowering the active area.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: June 10, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Shigeru Konishi
  • Patent number: 8748335
    Abstract: A photodegradation catalyst or a photodegradation catalyst precursor comprises a plurality of domains of an oxide of a first metal distributed in a substrate of a halide or oxyhalide of a second metal, wherein the mole percentage of the halide or oxyhalide of the second metal is above 50%. Additionally, a method of preparing a photodegradation catalyst or a photodegradation catalyst precursor, a photodegradation catalyst or a photodegradation catalyst precursor obtained from the method and a method of treating organic pollutants or substances in air or water by using the photodegradation catalyst or the photodegradation catalyst precursor are illustrated.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: June 10, 2014
    Assignee: Microvast, Inc.
    Inventors: Xiao Ping Zhou, Fei Chen, Jeff Qiang Xu
  • Patent number: 8748336
    Abstract: A process of contacting an alkylene oxide with 2-methoxy-1-propanol (PM1) in the presence of an oligomeric Schiff base metal complex catalyst is disclosed. Further, a process involving contacting an alkylene oxide with an alkyl alcohol using an oligomeric Schiff base metal complex as a catalyst is also disclosed. Additionally, novel compositions which can be used as catalysts in processes involving the contacting of an alkyl alcohol with an alkylene oxide are also disclosed.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: June 10, 2014
    Assignee: Dow Global Technologies LLC
    Inventors: Tina L. Arrowood, Paul R. Elowe, Jason C. MacDonald, Ernesto Occhiello
  • Patent number: 8748337
    Abstract: The present invention relates to a method for preparing a multi-metals/activated carbon composite, more particularly to a method for preparing a multi-metals/activated carbon composite, which is prepared by electrochemical electroplating of an alloy plate comprising at least two metals and activated carbons fixed on a conductive support under a predetermined condition. The multi-metals/activated carbon composite prepared in accordance with the present invention has improved adhesion force and specific surface area than those of a conventional composite obtained by continuously plating activated carbons, in which metal salts are impregnated, or metals and good reactivity due to the introduction of pure metals. Since the composition and content of metals can be controlled accurately, the multi-metals/activated carbon composite is useful as an active material for filters for removing gaseous or liquid pollutants, secondary cells, fuel cells, capacitors, hydrogen storage electrodes, etc.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: June 10, 2014
    Assignee: INHA—Industry Partnership Institute
    Inventors: Soo-Jin Park, Byung-Joo Kim
  • Patent number: 8748338
    Abstract: A toxin immobilization particle and method of fabrication is provided that includes a polysulfide-rubber polymer coated activated carbon particle that provides enhanced toxin adsorption. A porous activated carbon particle have a size range up to 2 mm is used. The polysulfide-rubber polymer coated activated carbon particle includes a polymer-dose range of up to 1.64 grams of sulfur per gram of activated carbon particles, where the toxins can include mercury, PCBs, chlorinated pesticides or polycyclic aromatic hydrocarbons. The method of forming the toxin immobilization particle includes condensing a polymer in a sulfide mixture to form a polysulfide-rubber polymer compound and coating an activated carbon particle with the polysulfide-rubber polymer. The levels of sulfur loading in the toxin immobilization particles are controlled by the polymer dose during the coating process, where the polysulfide polymer coated activated carbon particle provides enhanced toxin adsorption.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: June 10, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Richard G. Luthy, Eun Ah Kim
  • Patent number: 8748339
    Abstract: The present invention relates to a composition, comprising a 5-amino-3-oxo-2,3-dihydro-pyrazole of the formula I as defined in the claims and the description and at least one active compound II selected from groups A) to I) in a synergistically effective amount.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: June 10, 2014
    Assignee: BASF SE
    Inventors: Markus Gewehr, Jochen Dietz, Thomas Grote, Egon Haden
  • Patent number: 8748340
    Abstract: This document discloses pesticidal compostions comprising molecules having the following formulas: and processes related thereto.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: June 10, 2014
    Assignee: Dow AgroSciecnes LLC.
    Inventors: Gary D. Crouse, William Thomas Lambert, Thomas C. Sparks, Vidyadhar B. Hegde
  • Patent number: 8748341
    Abstract: The present invention relates to synergistic mixtures comprising, as active components, chlorfenapyr as insecticidal compound I and a fungicidal compound II selected from the group of azoxystrobin, coumethoxystrobin, coumoxystrobin, dimoxystrobin, enestroburin, fluoxastrobin, kresoxim-methyl, metominostrobin, orysastrobin, pico-xystrobin, pyraclostrobin, pyrametostrobin, pyraoxystrobin, pyribencarb, trifloxysstrobin, 2-(ortho-((2,5-dimethylphenyl-oxymethylen)phenyl)-3-methoxy-acrylic acid methyl ester, 2-(2-(3-(2,6-dichlorophenyl)-1-methyl-allylideneaminooxymethyl)-phenyl)-2-methoxyimino-N-methyl-acetamide.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 10, 2014
    Assignee: BASF SE
    Inventors: Markus Gewehr, Egon Haden, Lutz Brahm
  • Patent number: 8748342
    Abstract: The present invention relates to an agrochemical mixture for increasing the health of a plant, comprising as active ingredients a herbicidal compound (I) selected from the group consisting of: benzoic acids, pyridine carboxylic acids, quinoline carboxylic acids, and benazolin-ethyl; and a fungicidal compound (II) in synergistically effective amounts. The present invention further relates to a method for improving the health of a plant, wherein the plant, the locus where the plant is growing or is expected to grow or plant propagation material from which the plant grows is treated with an effective amount of a mixture as defined above. In addition, the invention relates to the use of a mixture as defined above for synergistically increasing the health of a plant.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: June 10, 2014
    Assignee: BASF SE
    Inventors: Markus Gewehr, Robert John Gladwin, Lutz Brahm
  • Patent number: 8748343
    Abstract: There are described herbicidal compositions which comprise at least one herbicidally active compound of the formula (I) and at least one crop-plant-protecting compound as safener. In this formula (I), V is an optionally substituted radical selected from the group consisting of isoxazol-4-yl, pyrazol-4-yl, cyclohexane-1,3-dion-2-yl and 3-oxopropionitril-2-yl and R9 is nitro, amino, halogen or a carbon-containing radical.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 10, 2014
    Assignee: Bayer Cropscience AG
    Inventors: Frank Ziemer, Lothar Willms, Hermann Bieringer, Erwin Hacker