Abstract: When an image forming apparatus shifts to a power saving mode, a controller unit further reduces power consumption by switching AC current on/off every predetermined amount of time. When AC current input from a commercial AC power supply is turned off, a DC voltage generating circuit normally can no longer supply a DC voltage, rendering the controller unit unable to operate. Accordingly, the controller unit operates using a charge accumulated in a smoothing capacitor while the AC current is not being supplied. An AC cutting circuit is switched on before a both-end voltage at the smoothing capacitor drops below a lower limit of operation voltage of the DC voltage generating circuit, and the smoothing capacitor is recharged.

Abstract: In one embodiment, a synchronous rectifier controller is configured to initiate forming an off-time interval for a first period of time responsively to the controller forming a disable state of a switching signal wherein the control circuit maintains the switching signal in the disable state for at least the off-time interval. The controller is also configured to restart forming the off-time interval responsively to a voltage of a synchronous rectifier becoming a first value prior to expiration of the first period of time.

Abstract: Provided are improvements for systems and methods of alternating current (AC) to direct current (DC) power regulation. The system improvements include a regulation circuit having a microprocessor that controls a silicon controlled rectifier circuit. Method improvements include one or more of SCR load sharing, adaptive voltage droop compensation, and/or voltage rebound compensation.

Abstract: In the present invention, a power conversion device is provided with an inverter for converting power output from a power source; a first power supply bus, connected to the positive electrode side of the inverter and the power source; a second power supply bus, connected to the negative electrode sides of the inverter and the power source; a first conductor that forms, along with the first power supply bus, a capacitor; a second conductor that forms, along with the second power supply bus, a capacitor; and a connection circuit, comprising a resistor, that electrically connects the first conductor and the second conductor.

Abstract: Provided is a power converter 3 that directly converts polyphase AC power to AC power. A converter circuit has a plurality of first switching elements 311, 313 and 315 that are connected to each phase R, S or T of the polyphase AC power to enable switching for turning on current-carrying bidirectionally, and a plurality of second switching elements 312, 314 and 316 that are connected to each phase to enable switching for turning on current-carrying bidirectionally. The converter circuit comprises input lines R, S and T connected to each input terminal, and output lines P and N connected to each output terminal. Parts of wiring 347 and 348 of protection circuits 32 are located between output lines P and N. The wiring distance between each protection circuit 32 and the corresponding switching element can be shortened.

Abstract: Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only if a match is detected on the pre-search bits are the main-search CAM cells powered-up to normal voltage levels and the search of the main-search bits activated. The main-search CAM cells are powered to normal voltage levels during read and write operations.

Abstract: A content addressable memory (CAM) system includes one or more CAM cells, each including a bit cell to store a bit and a complementary bit, and a compare circuit to compare a reference input to the stored bit and to the stored complementary bit. The compare circuit may be implemented to compare a single-ended reference input to each of the stored bit and the complementary bit. The compare circuit may include a pass circuit to selectively provide the reference input to an output under control of the stored bit and the stored complementary bit, a pull-up circuit to selectively pull-up the output under control of the reference input and the stored complementary bit, and a pull-down circuit to selectively pull-down the output under control of the reference input and the stored bit. The reference input may be provided to multiple CAM cells, which may share compare circuitry.

Abstract: Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.

Abstract: A memory structure with reduced-reflection signals at least includes a processing unit; a lumped circuit unit, connected to the processing unit; a plurality of memories, connected to the lumped circuit unit; and a reflected signal absorption unit, disposed at one end of the lumped circuit unit. Thereby, with the cooperation of the processing unit with each memory for signal transmission, the reflected signal absorption unit can be used to absorb the reflected signals so as to reduce the number of reflected signals during signal transmission, achieving the effect of stable operation for the memories.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A semiconductor device includes a first memory block including first vertical strings, a second memory block including second vertical strings coupled in series with the first vertical strings, wherein the second memory block is stacked on the first memory block, first bit lines located between the first memory block and the second memory block and electrically coupled to the first and second vertical strings, first source lines located under the first memory block and electrically coupled to the first vertical strings, and second source lines located above the second memory block and electrically coupled to the second vertical strings.

Abstract: Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.

Abstract: Provided are resistive random access memory (ReRAM) cells forming arrays and methods of operating such cells and arrays. The ReRAM cells of the same array may have the same structure, such as have the same bottom electrodes, top electrodes, and resistive switching layers. Yet, these cells may be operated in a different manner. For example, some ReRAM cells may be restively switched using lower switching voltages than other cells. The cells may also have different data retention characteristics. These differences may be achieved by using different forming operations for different cells or, more specifically, flowing forming currents in different directions for different cells. The resulting conductive paths formed within the resistive switching layers are believed to switch at or near different electrode interfaces, i.e., within a so called switching zone. In some embodiments, a switching zone of a ReRAM cell may be changed even after the initial formation.

Abstract: A thermodynamic bit apparatus, method and system. A thermodynamic bit is a device that returns a true or false state with a probability that depends on its internal state, which can be controlled via the application of positive feedback. A thermodynamic bit can include two or more memristors connected in series. A forward bias can be applied to the thermodynamic bit to read the state of the thermodynamic bit. A negative feedback can be applied to the thermodynamic bit during application of a forward bias to the thermodynamic bit. Also, a reverse bias can be applied to the thermodynamic bit to refresh or reinforce the state of the thermodynamic bit.

Abstract: A nonvolatile memory device is provided which includes a main area including main cells connected to word lines and main bit lines; a reference area including reference cells connected to the word lines and reference bit lines and programmed using the same write condition as that of the main area; a reference sense amplifier circuit configured to read data written at the reference area through the reference bit lines at a read operation; and control logic configured to control the reference sense amplifier circuit such that data written at the reference area is shifted with a weight scheme and then read, the data written at the reference area being used as a read reference value of the main area at a read operation.

Abstract: Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.

Abstract: The present invention relates to an Sb—Te—Ti phase-change thin-film material applicable to a phase-change memory and preparation thereof. The Sb—Te—Ti phase-change memory material of the present invention is formed by doping an Sb—Te phase-change material with Ti, Ti forms bonds with both Sb and Te, and the Sb—Te—Ti phase-change memory material has a chemical formula SbxTeyTi100-x-y, where 0<x<80 and 0<y<100-x. When the Sb—Te—Ti phase-change memory material is a Ti—Sb2Te3 phase-change memory material, Ti atoms replace Sb atoms, and phase separation does not occur. In a crystallization process of an Sb—Te phase-change material in the prior art, gain growth dominates, so the phase change rate is high, but the retention cannot meet industrial requirements.

Abstract: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

Abstract: A p-channel flash memory device including a 3D NAND array has excellent performance characteristics. Techniques for operating 3D, p-channel NAND arrays include selective programming, selective (bit) erase, and block erase. Selective programming bias arrangements induce band-to-band tunneling current hot electron injection to increase threshold voltages in selected cells. Selective erase biasing arrangements induce ?FN hole tunneling to decrease threshold voltages in selected cells. Also, block erase bias arrangements induce ?FN hole tunneling in selected blocks of cells.

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

Abstract: Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.

Abstract: An EEPROM cell control circuit is provided which includes a signal input circuit configured to receive control signals for controlling an EEPROM cell from an external device; a bit line control circuit configured to provide a positive voltage and a negative voltage to two bit lines connected with the EEPROM cell in response to the control signals; and a word line control circuit configured to control a sense gate line in response to the control signals at a sense operation and to apply a positive voltage and a negative voltage to a word line.

Abstract: According to one embodiment, a semiconductor memory device includes first hookup transistors connected to word lines, a first dummy hookup transistor connected to first dummy word line, and a second dummy hookup transistor connected to second dummy word line. A group of hookup transistors formed by the first hookup transistors, the first dummy hookup transistor, and the second dummy hookup transistor is aligned on either of one row and rows. The first dummy hookup transistor and the second dummy hookup transistor are arranged at least at one end of the group of hookup transistors.

Abstract: Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region. A test application may be stored in the general purpose region, and the test application can be executed to run a test of the memory locations in the test region. The results of the test may be stored in the general purpose region. At the completion of the test, the test results may be provided from the general purpose region and displayed to a user. The virtual partitions may be removed prior to shipping the electronic device for distribution.

Abstract: An EEPROM cell is provided which includes a control gate; a tunneling plate; a floating plate configured to form a capacitor area with the control plate and the tunneling plate; an inverter configured to sense a voltage level of the floating plate; a first transfer gate connected with the tunneling plate and configured to transfer an operating voltage selectively applied from first and second bit lines to the tunneling plate; a protection circuit connected with the inverter and configured to float the inverter at non-read or write/erase operations of an adjacent EEPROM cell; and a second transfer gate configured to transfer an output voltage of the inverter. This configuration is enable to use all the same gate oxide (i.e. 26 ?) and ultra low operation voltages (i.e. ±2V) in EEPROM cell.

Abstract: A multi-port memory device includes a plurality of serial I/O data pads for providing a serial input/output (I/O) data communication; a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data communication with the ports; a plurality of first data buses for transferring first signals from the ports to the banks; a plurality of second data buses for transferring second signals from the banks to the ports; and a switching unit for connecting the first data buses with the second data buses in response to a control signal.

Abstract: Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells.

Abstract: Described embodiments provide a memory having at least one sense amplifier with inputs coupled to at least one pair of bit lines. One of the pair of bit lines is precharged to a power supply voltage and a second one of the pair is precharged to ground. A first switch DC-couples the first one of the pair of bit lines to a first input of a cross-coupled amplifier. A first capacitor AC-couples the second one of the pair of bit lines to a second input of the cross-coupled amplifier. Then a memory cell coupled between the first and second one of the pair of bit lines is enabled. A switch then decouples the first input from the bit line, a second capacitor is used to inject a charge of current into the first input of the cross-coupled amplifier, and then the cross-coupled amplifier is enabled.

Abstract: Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

Abstract: Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency. Other embodiments are also disclosed and claimed.

Abstract: A stacked memory device includes a plurality of interconnected memory chips and a controller to control the plurality of memory chips to perform refresh operations during non-overlapping time periods. Each memory chip includes a plurality of ranks, and each rank includes at least one memory bank. In one arrangement, the controller controls the refresh operation to be selectively performed for a first rank in each of the memory chips during the non-overlapping time periods independently from a refresh operation performed for a second rank in each memory chip. Delay circuits or other logic may be included to ensure that the refresh operations do not overlap.

Abstract: A memory subsystem includes an adaptive output voltage to provide a voltage based on a power profile of a memory device of the memory subsystem. A charge pump increases the voltage to a level needed to write data to the memory device. The voltage provided is based on the power profile of the memory device, which indicates a voltage level that provides good efficiency for the charge pump, and is within maximum levels for the memory device. The voltage can be higher than a nominal voltage indicated for the memory device in a specification.

Abstract: A controlling method of a connector, the connector, and a memory storage device are provided. The controlling method includes following steps. A first clock signal generated by a first oscillator in the connector is obtained. A second clock signal generated by a second oscillator in the connector is obtained. A frequency shift of the first oscillator is smaller than a frequency shift of the second oscillator. A detection window information corresponding to the second clock signal is corrected according to the first clock signal and the second clock signal. The first oscillator is turned off. A signal stream including a first signal is received. A detection window is generated according to the corrected detection window information and the second clock signal, and whether the first signal is a burst signal is determined according to the detection window. Thereby, the power consumption of the connector is reduced.

Abstract: A vibration generating device including a working platform, an opposite platform and a driving unit is provided. The working platform carries a workpiece disposed on one side of the working platform. The opposite platform is adjacent to another side of the working platform. The working platform and the opposite platform contact to each other via at least two bumps reversely protruded between the working platform and the opposite platform. The driving unit is coupled to the working platform or the opposite platform to drive the working platform or the opposite platform to move in a horizontal direction, and the working platform generates a vibration in a vertical direction.

Abstract: The present invention relates to a beverage container with a helical or spiral shape. The container of the present invention provides efficient and effective mixing of ingredients without the need for additional parts or components to facilitate mixing.

Abstract: A system for bone cement includes a vial holder configured for receiving a vial and including a holding structure for maintaining the vial in the vial holder. The vial includes a monomer component for bone cement. A holder chamber is configured to receive and secure the vial holder. The vial holder is advanced toward a vial-breaking device for breaking the vial and releasing its contents into the holder chamber past the elastomeric seal. Once the vial holder is advanced further the elastomeric seal is deformed to form a seal and prevent fumes produced from escaping from the device.

Abstract: An autorotation and revolution magnetic stirring device for producing conductive golden particles comprises a mounting holder, a rotary electric motor, a flask, a magnetic stirrer, and a magnetic rotor. The rotary electric motor is fixed to the mounting holder. The flask is rotatably mounted to the mounting holder. The rotary electric motor provides rotary power to make the flask rotate. The magnetic rotor is put into the flask. The magnetic rotor rotates due to the magnetic force from the magnetic stirrer. In the present invention, the solvents in the flask rotate due to the rotary of the flask and the rotary of the magnetic rotor. “Revolution” and “autorotation” exist at the same time, so the solvents are stirred more adequately and more evenly so as to obtain an excellent surface treatment effect.

Abstract: A system for pumping or mixing a fluid using a rotating pumping or mixing element and various other components for use in a pumping or mixing system are disclosed.

Abstract: A rotor/stator type mixer implements the particle size breakup apparatus and includes a stator having a plurality of openings formed thereon and a rotor disposed on the inside of the stator and spaced away from the stator with a specific gap. The rotor, which is disposed inwardly of the stator having the plurality of openings formed thereon so that it can be spaced away from the stator with the specific gap, has a rotor peripheral wall that faces opposite the inside of the stator peripheral wall and is disposed inwardly radially of the peripheral wall of the stator having the plurality of openings formed thereon so that it can be spaced away from the stator with the specific gap. In addition, the rotor has a plurality of openings formed thereon.

Abstract: An information processing apparatus is provided, which includes: a signal initialization unit that acquires an initial value of a pressure signal that is obtained after receive, by a receiving unit, of an elasticity wave from an object; an impulse response initialization unit that acquires an initial value of an impulse response of the receiving unit; and an output unit that outputs a modified pressure signal, wherein the output unit has: a signal modifying unit that modifies the pressure signal in use of the impulse response; a signal constraining unit that modifies the pressure signal based on a plurality of constraint conditions; an impulse response modifying unit that modifies the impulse response; and an impulse response constraining unit that modifies the impulse response based on constraint conditions which are time-bandwidth characteristics, and wherein the output unit generates the modified pressure signal by iteratively executing the processes.

Abstract: Provided is an electronic device including a modulation unit (22) that modulates a sound signal to a modulation wave for a parametric speaker; an oscillator (12) to which the modulation wave is input; an equalizer (26) that corrects a frequency characteristic of a sound wave that is demodulated by the modulation wave; and a control unit (20) that selects a carrier frequency of the modulation wave and changes setting of the equalizer (26) on the basis of the selected carrier frequency. Thus, it is possible to provide the electronic device capable of correcting the frequency characteristic of the sound wave that is demodulated, for each carrier frequency of the modulation wave.

Abstract: Discloses herein is a system of acquiring seismic date in a marine environment, which includes: seismic streamers towed by a vessel; and means for detecting and/or locating marine mammals, characterised in that said marine mammal detection and/or location means are secured to said seismic streamers.

Abstract: An acoustic logging tool is provided with a first acoustic source that generates an acoustic signal primarily directed into the formation, the acoustic signal including a noise signal carried axially along the tool, a second acoustic source adapted to generate a noise canceling signal along the tool that actively and significantly cancels the noise signal, and a plurality of acoustic sensors axially spaced from each other along the tool and spaced from the first acoustic source and the second acoustic source. The acoustic sensors receive and record indications of pressure signals resulting from the acoustic signal and the noise canceling signal. The pressure signal indications may be processed in order to generate information regarding the formation.

Abstract: A method for torsional wave logging in a borehole of a subterranean formation. The method includes obtaining a torsional wave measurement of the borehole, wherein the torsional wave measurement represents characteristics of a torsional wave propagating within a cylindrical layered structure associated with the borehole, wherein the cylindrical layered structure comprises the subterranean formation and a completion of the borehole, analyzing, by a computer processor, the torsional wave measurement to generate a quality measure of the completion, and displaying the quality measure of the completion.

Abstract: To perform noise attenuation for seismic surveying, a sensor assembly is deployed on a ground surface, where the sensor assembly has a seismic sensor to measure seismic waves propagated through a subterranean structure, and a divergence sensor comprising a pressure sensor to measure noise. First data is received from the seismic sensor, and second data is received from the divergence sensor. The first data and the second data are combined to attenuate noise in the first data.

Abstract: A method of synchronization between downhole components includes: generating a dual tone synchronization signal by a signal generator in a first downhole component disposed in a borehole in an earth formation, the dual tone signal including a first constituent periodic signal having a first frequency f1 and a second constituent periodic signal having a second frequency f2 that is different from the first frequency; transmitting the synchronization signal to a second downhole component disposed in the borehole; receiving the synchronization signal by a signal processor in the second downhole component, calculating a phase difference between the first constituent signal and the second constituent signal, and calculating a transmission delay based on the phase difference; and synchronizing operation of the first and second downhole components based on the delay.

Abstract: An indoor ultrasonic location tracking system that can utilize standard audio speakers to provide indoor ranging information to modern mobile devices like smartphones and tablets. The method uses a communication scheme based on linearly increasing frequency modulated chirps in the audio bandwidth just above the human hearing frequency range where mobile devices are still sensitive. The method uses gradual frequency and amplitude changes that minimize human perceivable (psychoacoustic) artifacts derived from the non-ideal impulse response of audio speakers. Chirps also benefit from Pulse Compression, which improves ranging resolution and resilience to both Doppler shifts and multi-path propagation that plague indoor environments. The method supports the decoding of multiple unique identifier packets simultaneously. A Time-Difference-of-Arrival pseudo-ranging technique allows for localization without explicit synchronization with the broadcasting infrastructure.

Abstract: A domestic appliance with timer control for the treatment of contents, the domestic appliance comprising a timer configured to track a treatment time period, a display configured to display a plurality of screens, at least one user input component programmed to receive a treatment time input corresponding to a treatment time and receive an expiration function input corresponding to an expiration function subsequent to receiving the treatment time input, and a controller programmed to set the timer with the treatment time in accordance with the received treatment time input and set the expiration function.