Patents Issued in July 10, 2014
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Publication number: 20140193926Abstract: The invention provides a novel class of reactive fluorescent agents that are based on a pyrene sulfonic acid nucleus. The agents are readily incorporated into conjugates with other species by reacting the reactive group with a group of complementary reactivity on the other species of the conjugate. Also provided are methods of using the compounds of the invention to detect and/or quantify an analyte in a sample. In an exemplary embodiment, the invention provides multi-color assays incorporating the compounds of the invention.Type: ApplicationFiled: November 14, 2013Publication date: July 10, 2014Applicant: LIFE TECHNOLOGIES CORPORATIONInventors: Richard HAUGLAND, Wai-Yee Leung, Jixiang Liu
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Publication number: 20140193927Abstract: The present invention pertains to the field of cancer prediction. Specifically, it relates to a method for predicting the risk of recurrence of bladder cancer in a subject after treatment of bladder cancer comprising the steps of determining the amount of at least one biomarker selected from the biomarkers shown in Table, and comparing the amount of said at least one biomarker with a reference amount for said at least one biomarker, whereby the risk of recurrence of bladder cancer is to be predicted. The present invention also contemplates a method for identifying a subject being in need of a further bladder cancer therapy. Encompassed are, furthermore, diagnostic devices and kits for carrying out said methods.Type: ApplicationFiled: June 8, 2012Publication date: July 10, 2014Inventors: Christoph Schröder, Harish Srinivasan, Jörg Hiheisel, François Radvanyi
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Publication number: 20140193928Abstract: Provided is a current application device capable of applying a test current of a magnitude necessary for testing of a semiconductor element without any trouble. A current application device 1 is configured to have a contacting section having a plurality of projections 21 for contacting a contact region 24 inside an active region 23 of a semiconductor element 22 and applying the test current thereto, and a pressing section 3 which presses the contacting section 2 against the semiconductor element 22 such that each projection 21 contacts the contact region 24. A plurality of the projections 21 are arranged such that an arrangement density of outside projections 21 is larger than the arrangement density of inside projections 21.Type: ApplicationFiled: January 6, 2014Publication date: July 10, 2014Applicant: Honda Motor Co., Ltd.Inventors: Satoshi Hasegawa, Shigeto Akahori, Shinya Maita, Hitoshi Saito, Yoko Yamaji
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Publication number: 20140193929Abstract: A low-cost integrated reflector and heat spreader for high-density high power solid-state (e.g., LED) lighting arrays includes a base structure onto which is applied a sacrificial material. A relatively thick thermal spray coating is applied over the base structure and sacrificial material. The sacrificial material is removed. A channel(s) is thereby provided within the thermal spray coating layer and in physical contact with the base structure. The channel may be filled with a cooling fluid. A pulsating heat pipe heat spreader may thereby be provided. A reflective material may be provided either over another surface of the base structure or alternatively over the thermal spray coating layer to provide a surface for reflecting and directing light emitted from a solid state light source that may be secured to the integrated reflector and heat spreader.Type: ApplicationFiled: December 9, 2013Publication date: July 10, 2014Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: John S. Paschkewitz, Eric Shrader
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Publication number: 20140193930Abstract: An LED package with an extended top electrode and an extended bottom electrode is formed from a first metal and a second metal. An LED is on an inner end of the first metal. An outer end of the first metal has been bent upward twice 90 degrees to form a top flat as an extended top electrode of the package. An outer end of the second metal has been bent downward twice 90 degrees to form a bottom flat as an extended bottom electrode of the package. The LED and a bonding wire may be encapsulated with glue.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: Cheng Kung Capital, LLCInventor: Jiahn-Chang Wu
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Publication number: 20140193931Abstract: A method according to embodiments of the invention includes positioning a flexible film (48) over a wafer of semiconductor light emitting devices, each semiconductor light emitting device including a semiconductor structure (13) including a light emitting layer sandwiched between an n-type region and a p-type region. The wafer of semiconductor light emitting devices is bonded to a substrate (50) via the flexible film (48). After bonding, the flexible film (48) is in direct contact with the semiconductor structures (13). The method further includes dividing the wafer after bonding the wafer to the substrate (50).Type: ApplicationFiled: July 30, 2012Publication date: July 10, 2014Applicant: KONINKLIJKE PHILIPS N.V.Inventors: Grigoriy Basin, John Edward Epler, Paul Scott Martin
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Publication number: 20140193932Abstract: A method for manufacturing a light-emitting device comprises the steps of: providing a first substrate; forming a semiconductor structure on the first substrate, wherein the semiconductor structure comprises a first type semiconductor layer, a second type semiconductor layer, and an active layer between the first type semiconductor layer and the second type semiconductor layer; forming an isolation region through the second type semiconductor and the active layer to separate the semiconductor structure into a first part and a second part on the first substrate; and injecting an electrical current with a current density to the second part to make the second part to be permanently broken-down; wherein after the second part is permanently broken-down, the first part is capable of generating electromagnetic radiation and the second part is incapable of generating electromagnetic radiation.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: Epistar CorporationInventors: Rong-Ren LEE, Cheng-Hong CHEN, Chih-Peng NI, Chun-Yu LIN
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Publication number: 20140193933Abstract: A method for manufacturing a semiconductor optical device includes the steps of preparing a mold having an imprint pattern; forming a substrate product including a semiconductor layer; forming a first resin layer on the semiconductor layer; forming a diffraction grating pattern having periodic projections and recesses in the first resin layer using the mold, the projection of the diffraction grating pattern having a top portion and a base portion; changing a duty ratio of the diffraction grating pattern by dry-etching the first resin layer; forming a second resin layer on the first resin layer so as to cover the projection and the recess; removing the top portion by etching back the first and second resin layers; and selectively etching the first resin layer so as to have a reverse pattern to the diffraction grating pattern; and etching the semiconductor layer through the first resin layer.Type: ApplicationFiled: January 7, 2014Publication date: July 10, 2014Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Kenji SAKURAI
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Publication number: 20140193934Abstract: An organic light emitting display resulting in an improved aperture ratio and a manufacturing method thereof. The organic light emitting display that includes a plurality of pixels arranged between first and second substrates, each of said pixels includes a plurality of thin film transistors, an organic light emitting diode, and a capacitor. The thin film transistors and the organic light emitting diode are formed on the first substrate and the capacitor is formed on the second substrate, and the thin film transistors and the capacitor are electrically connected with each other upon the first substrate being bonded to the second substrate.Type: ApplicationFiled: April 9, 2013Publication date: July 10, 2014Applicant: Samsung Display Co., LtdInventor: Eun-Ah Kim
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Publication number: 20140193935Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.Type: ApplicationFiled: October 16, 2013Publication date: July 10, 2014Applicant: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORKInventors: James S. IM, Ui-Jin CHUNG
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Publication number: 20140193936Abstract: A method of fabricating an organic light emitting device includes forming a first electrode layer on a substrate, surface-treating the first electrode layer with CF4 plasma, forming a first common layer containing pentacene on the surface-treated first electrode layer, forming an organic light emitting layer on the first common layer, forming a second common layer on the organic light emitting layer, and forming a second electrode layer on the second common layer. The CF4 plasma treatment enhances the luminous efficiency of the organic light emitting device.Type: ApplicationFiled: July 31, 2013Publication date: July 10, 2014Inventors: Hyun Ju CHOI, CHANG HO LEE, ILSOO OH, HeeJoo KO, DAE YUP SHIN, KeonHa CHOI, CHANGMIN LEE, INJAE LEE, Pyungeun JEON, SEJIN CHO, JinYoung YUN, Bora LEE, BEOMJOON KIM, Yeon woo LEE, Ji Hye SHIM, Joongwon SIM
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Publication number: 20140193937Abstract: A method of forming a layer of an electronic device, for example an organic light-emitting device, the method comprising the step of depositing a precursor layer comprising a compound of formula (I) and reacting the compound of formula (I) in a ring-opening addition reaction: Core-(Reactive Group)n??(I) wherein Core is a non-polymeric core group; and each Reactive Group, which may be the same or different in each occurrence, is a group of formula (II): wherein Sp1 independently in each occurrence represents a spacer group; w independently in each occurrence is 0 or 1; Ar in each occurrence independently represents an aryl or heteroaryl group; R1 in each occurrence independently represents H or a substituent, with the proviso that at least one R1 is a substituent; n is at least 1; and * is a point of attachment of the group of formula (II) to the Core; and wherein the compound of formula (I) reacts with itself or with a non-polymeric co-reactant.Type: ApplicationFiled: January 9, 2014Publication date: July 10, 2014Applicants: Sumitomo Chemical Company Limited, Cambridge Display Technology, Ltd.Inventors: Martin Humphries, Florence Bourcet
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Publication number: 20140193938Abstract: A chemically sensitive sensor with a lightly doped region that affects an overlap capacitance between a gate and an electrode of the chemical sensitive sensor. The lightly doped region extends beneath and adjacent to a gate region of the chemical sensitive sensor. Modifying the gain of the chemically sensitive sensor is achieved by manipulating the lightly doped region under the electrodes.Type: ApplicationFiled: February 12, 2014Publication date: July 10, 2014Applicant: LIFE TECHNOLOGIES CORPORATIONInventor: Keith G. FIFE
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Publication number: 20140193939Abstract: An apparatus for forming a solar cell includes a housing defining a vacuum chamber, a rotatable substrate support, at least one inner heater and at least one outer heater. The substrate support is inside the vacuum chamber configured to hold a substrate. The at least one inner heater is between a center of the vacuum chamber and the substrate support, and is configured to heat a back surface of a substrate on the substrate support. The at least one outer heater is between an outer surface of the vacuum chamber and the substrate support, and is configured to heat a front surface of a substrate on the substrate support.Type: ApplicationFiled: January 4, 2013Publication date: July 10, 2014Applicant: TSMC SOLAR LTD.Inventors: Edward TENG, Ying-Chen CHAO, Chih-Jen YANG
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Publication number: 20140193940Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Szu-Ying Chen, Tzu-Jui Wang, Dun-Nian Yaung, Jen-Cheng Liu
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Publication number: 20140193941Abstract: A method for manufacturing a solar cell includes forming a first electrode on a substrate, removing a portion of the first electrode to form a first electrode opening, forming a light absorbing layer on the first electrode and in the first electrode opening, and applying a laser beam to the substrate to create an interface reaction between the first electrode and at least the light absorbing layer, thereby removing a portion of the light absorbing layer to form a light absorbing layer opening.Type: ApplicationFiled: November 22, 2013Publication date: July 10, 2014Applicant: SAMSUNG SDI CO., LTD.Inventors: Min-Sung Kim, Min-Kyu Kim, Su-Yeon Kim, Yuk-Hyun Nam, Ku-Hyun Kang
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Publication number: 20140193942Abstract: A method for depositing one or more thin-film layers on a flexible polyimide substrate having opposing front and back outer surfaces includes the following steps: (a) heating the flexible polyimide substrate such that a temperature of the front outer surface of the flexible polyimide substrate is higher than a temperature of the back outer surface of the flexible polyimide substrate, and (b) depositing the one or more thin-film layers on the front outer surface of the flexible polyimide substrate. A deposition zone for executing the method includes (a) one of more physical vapor deposition sources adapted to deposit one or more metallic materials on the front outer surface of the substrate, and (b) one or more radiant zone boundary heaters.Type: ApplicationFiled: January 8, 2014Publication date: July 10, 2014Applicant: Ascent Solar Technologies, Inc.Inventors: Lawrence M. Woods, Rosine Ribelin, Joseph H. Armstrong
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Publication number: 20140193943Abstract: A method for fabricating a Cu—In—Ga—Se film solar cell is provided. The method comprises: a) fabricating a molybdenum back electrode on a substrate; b) fabricating a Cu—In—Ga—Se absorbing layer on the back electrode by fractional sputtering in a plurality of sputter chambers; c) performing an annealing; d) fabricating an In2Se3 or ZnS buffer layer on the Cu—In—Ga—Se absorbing layer; e) fabricating an intrinsic zinc oxide high impedance layer on the In2Se3 or ZnS buffer layer; f) fabricating an indium tin oxide film low impedance layer on the intrinsic zinc oxide high impedance layer; g) fabricating an aluminum electrode on the indium tin oxide film low impedance layer.Type: ApplicationFiled: January 11, 2014Publication date: July 10, 2014Inventors: Liuyu Lin, Zhun Zhang
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Publication number: 20140193944Abstract: A polymer substrate and back contact structure for a photovoltaic element, and a photovoltaic element include a CIGS photovoltaic structure, a polymer substrate having a device side at which the photovoltaic element can be located and a back side opposite the device side. A layer of dielectric is formed at the back side of the polymer substrate. A metal structure is formed at the device side of the polymer substrate.Type: ApplicationFiled: March 13, 2014Publication date: July 10, 2014Applicant: ASCENT SOLAR TECHNOLOGIES, INC.Inventors: Lawrence M. Woods, Hobart Stevens, Joseph H. Armstrong
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Publication number: 20140193945Abstract: Disclosed herein is an aqueous alkaline etching solution comprising water and an alkaline material being selected from the group consisting of ammonium hydroxide, ammonium phosphate, ammonium carbonate, quaternary ammonium hydroxide, quaternary ammonium phosphate, quaternary ammonium carbonate, an alkali metal hydroxide, an alkaline earth metal hydroxide, or a combination comprising at least one of the foregoing alkaline materials; the aqueous alkaline solution being operative to etch aluminum oxide at a rate greater than or equal to about 2:1 over a rate at which it etches a metal oxide semiconductor to be protected; wherein the aqueous etching solution has a pH of 8 to 13.Type: ApplicationFiled: December 31, 2012Publication date: July 10, 2014Inventors: Yuanyuan Li, Kaige Sun, Thomas N. Jackson
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Publication number: 20140193946Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.Type: ApplicationFiled: March 10, 2014Publication date: July 10, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei YAMAZAKI, Takuya HIROHASHI, Masahiro TAKAHASHI, Takashi SHIMAZU
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Publication number: 20140193947Abstract: Oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film are reduced and electric characteristics of a transistor including the oxide semiconductor film are improved. Further, a highly reliable semiconductor device including the transistor including the oxide semiconductor film is provided. In the transistor including the oxide semiconductor film, at least one insulating film in contact with the oxide semiconductor film contains excess oxygen. By the excess oxygen included in the insulating film in contact with the oxide semiconductor film, oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced. Note that the insulating film including the excess oxygen has a profile of the excess oxygen concentration having two or more local maximum values in the depth direction.Type: ApplicationFiled: March 13, 2014Publication date: July 10, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei YAMAZAKI
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Publication number: 20140193948Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.Type: ApplicationFiled: March 10, 2014Publication date: July 10, 2014Applicant: RAYTHEON COMPANYInventors: Roland Gooch, Buu Diep, Thomas Allan Kocian, Stephen H. Black, Adam M. Kennedy
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Publication number: 20140193949Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a first substrate; bonding a second substrate to the first substrate, the second substrate including a microeelectromechanical system (MEMS) device; and bonding a third substrate to the first substrate.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventor: Ting-Hau Wu
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Publication number: 20140193950Abstract: An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.Type: ApplicationFiled: March 12, 2014Publication date: July 10, 2014Applicant: XINTEC INC.Inventors: Shu-Ming CHANG, Bai-Yao LOU, Ying-Nan WEN, Chien-Hung LIU
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Publication number: 20140193951Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.Type: ApplicationFiled: March 13, 2014Publication date: July 10, 2014Inventors: Heung-kyu Kwon, Su-chang Lee
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Publication number: 20140193952Abstract: Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating.Type: ApplicationFiled: January 4, 2013Publication date: July 10, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Jen Lin, Ai-Tee Ang, Yu-Jen Tseng, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
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Publication number: 20140193953Abstract: A semiconductor device mounting structure includes: a substrate with an opening provided therein; a frame member with a frame body and a protruding portion that protrudes from the frame body, the frame body being formed and accommodated in a groove around the opening; a coreless substrate provided above the substrate and supported by the protruding portion of the frame member; and semiconductor elements provided on the coreless substrate.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: FUJITSU LIMITEDInventors: Manabu WATANABE, Masateru KOIDE, Kenji FUKUZONO, Takashi KANDA
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Publication number: 20140193954Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: Renesas Electronics CorporationInventors: Naoto Taoka, Atsushi Nakamura, Naozumi Morino, Toshikazu Ishikawa, Nobuhiro Kinoshita
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Publication number: 20140193955Abstract: Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Matthew T. Currie
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Publication number: 20140193956Abstract: Fabrication methods for junctionless transistor and complementary junctionless transistor are provided. An isolation layer doped with a first-type ion is formed on a semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer. The active layer includes a first portion between a second portion and a third portion of the active layer. Portions of the isolation layer under the second and third portions of the active layer are removed to suspend the second and third portions of the active layer. A gate structure is formed on the first portion of the active layer. A source and a drain are formed by doping the second portion and the third portion of the active layer with the second-type ion on both sides of the gate structure. The source and the drain have a same doping type as the first portion of the active layer.Type: ApplicationFiled: December 30, 2013Publication date: July 10, 2014Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventor: DE YUAN XIAO
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Publication number: 20140193957Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Ashish K. Jha, Tae-Hoon Kim, Tae Hoon Lee, Chang Ho Maeng, Songkram Srivathanakul, Haiting Wang
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Publication number: 20140193958Abstract: The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: ApplicationFiled: March 12, 2014Publication date: July 10, 2014Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
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Publication number: 20140193959Abstract: A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate.Type: ApplicationFiled: March 10, 2014Publication date: July 10, 2014Applicant: Taiwan Semiconductor Manufacturing Company, LtdInventors: Ching-Hsiung Lo, Jam-Wem Lee, Wun-Jie Lin, Jen-Chou Tseng
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Publication number: 20140193960Abstract: A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.Type: ApplicationFiled: March 12, 2014Publication date: July 10, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masahiro Fukuda, Eiji Yoshida, Yosuke Shimamune
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Publication number: 20140193961Abstract: Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 K?˜30 K?) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc.) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.Type: ApplicationFiled: March 10, 2014Publication date: July 10, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Chyuan Tzeng, Luan C. Tran, Chen-Jong Wang, Kuo-Chi Tu, Hsiang-Fan Lee
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Publication number: 20140193962Abstract: A method of forming a semiconductor device is provided. The method includes preparing a substrate having a transistor region and an alignment region, forming a first trench and a second trench in the substrate of the transistor region and in the substrate of the alignment region, respectively, forming a drift region in the substrate of the transistor region, forming two third trenches respectively adjacent to two ends of the drift region, and forming an isolation pattern in the first trench, a buried dielectric pattern in the second trench, and dielectric patterns in the two third trenches, respectively. A depth of the first trench is less than a depth of the third trenches, and the depth of the first trench is equal or substantially equal to a depth of the second trench.Type: ApplicationFiled: March 10, 2014Publication date: July 10, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: YONGDON KIM
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Publication number: 20140193963Abstract: A technique for forming 3D semiconductor structure is disclosed. In one embodiment, a substrate having at least two vertically extending fins is provided. An insulating material is deposited in the trench between the fins. After planarization, an ion implant process is performed to change the properties of the insulating material, specifically, the implanted region has a higher etch rate than the remainder of the insulating material. This higher etch rate region is then removed. This process of implanting and removing can be repeated until the insulating material reaches the desired height. In some embodiments, the substrate may be subjected to an anneal process prior to the removal of the higher etch rate region. The Gaussian implant depth profile may change into a box-like implant depth profile during the anneal process via thermal diffusion.Type: ApplicationFiled: March 13, 2014Publication date: July 10, 2014Inventors: Ludovic Godet, Keping Han
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Publication number: 20140193964Abstract: The present invention provides a method of manufacturing a semiconductor device. The method at least comprises the following steps. First, the semiconductor device, which comprises a gate, a gate dielectric layer, an active layer, a source and a drain, is manufactured. However, the semiconductor device has a plurality of defects, and the active layer is a metal oxide thin film. After annealing the semiconductor device, it will be transferred into a chamber. A final step of injecting a supercritical fluid carried with a co-solvent into the chamber is then performed to modify the abovementioned defects.Type: ApplicationFiled: May 30, 2013Publication date: July 10, 2014Applicant: National Chiao Tung UniversityInventors: Po-Tsun LIU, Wei-Ya WANG, Li-Feng TENG
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Publication number: 20140193965Abstract: A method of: providing an off-axis 4H—SiC substrate, and etching the surface of the substrate with hydrogen or an inert gas.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Rachael L. Myers-Ward, David Kurt Gaskill, Charles R. Eddy, JR., Robert E. Stahlbush, Nadeemmullah A. Mahadik, Virginia D. Wheeler
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Publication number: 20140193966Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.Type: ApplicationFiled: March 7, 2014Publication date: July 10, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Byung-Kwan YOU, Kwang-Soo SEOL, Young-Woo PARK, Jin-Soo LIM
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Publication number: 20140193967Abstract: In a method of forming an epitaxial layer, an etching gas may be decomposed to form decomposed etching gases. A source gas may be decomposed to form decomposed source gases. The decomposed source gases may be applied to a substrate to form the epitaxial layer on the substrate. A portion of the epitaxial layer on a specific region of the substrate may be etched using the decomposed etching gases. Before the etching gas is introduced into the reaction chamber, the etching gas may be previously decomposed. The decomposed etching gases may then be introduced into the reaction chamber to etch the epitaxial layer on the substrate. As a result, the epitaxial layer on the substrate may have a uniform distribution.Type: ApplicationFiled: January 10, 2014Publication date: July 10, 2014Applicants: Kookje Electric Korea Co., Ltd., Samsung Electronics Co., Ltd.Inventors: Sung-Ho KANG, Bong-Jin KUH, Yong-Kyu JOO, Sung-Ho HEO, Hee-Seok KIM, Yong-Sung PARK
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Publication number: 20140193968Abstract: A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. Next, a second insulating film is formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film, upper part of the trench ton form a second gate electrode.Type: ApplicationFiled: December 9, 2013Publication date: July 10, 2014Applicant: Renesas Electronics CorporationInventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20140193969Abstract: Semiconductor structure including an etch stop material between a substrate and a stack of alternating insulating materials and first conductive materials, wherein the etch stop material comprises an amorphous aluminum oxide on the substrate and a crystalline aluminum oxide on the amorphous aluminum oxide; a channel material extending through the stack; and a second conductive material between the channel material and at least one of the first conductive materials in the stack of alternating insulating materials and first conductive materials, wherein the second conductive material is not between the channel material and the etch stop material. Also disclosed are methods of fabricating such semiconductor structures.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: Micron Technology, Inc.Inventors: Jeffery B. Hull, John M. Meldrim
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Publication number: 20140193970Abstract: An integrated circuit (IC) including a set of isolated wire structures disposed within a layer of the IC, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween. The method further includes forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures. The method further includes forming a photosensitive material over the capping layer. The method further includes forming an opening in the photosensitive material between the adjacent wiring structures to expose the capping layer. The method further includes removing the exposed capping layer.Type: ApplicationFiled: November 11, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee
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Publication number: 20140193971Abstract: The semiconductor device includes: a semiconductor substrate; an insulating film provided on a surface of the semiconductor substrate; a porous metal film provided on the insulating film; a protective film provided on the porous metal film, and having an opening portion for defining a pad region; and a wire wire-bonded to the porous metal film in the pad region. The stress generated by the impact of wire-bonding is mostly absorbed in the porous metal film owing to the distortion of the porous metal film, preventing generation of cracks in the insulating film.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: SEIKO INSTRUMENTS INC.Inventor: Masaru AKINO
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Publication number: 20140193972Abstract: Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed.Type: ApplicationFiled: January 7, 2013Publication date: July 10, 2014Applicant: Spansion LLCInventors: Scott A. BELL, Angela Tai HUI, Simon S. CHAN
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Publication number: 20140193973Abstract: A method forms interlayer connectors extending to conductive layers of a stack of W conductive layers interleaved with dielectric layers. The stack is etched to expose landing areas at W?1 conductive layers using a set of M etch masks. For each etch mask m, m going from 0 to M?1, there is a first etching step, at least one mask trimming step, and a subsequent etching step following each trimming step. The etch mask may cover Nm+1 of the landing areas and the open etch region may cover Nm of the landing areas. N equals 2 plus the number of trimming steps. The trimming step may be carried out so that the increased size open etch region overlies an additional 1/N of the landing areas. Part of the stack surface may be shielded during the removing step to create dummy areas without contact openings.Type: ApplicationFiled: January 7, 2013Publication date: July 10, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventor: Shih-Hung CHEN
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Publication number: 20140193974Abstract: A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.Type: ApplicationFiled: January 9, 2013Publication date: July 10, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ying LEE, Jyu-Horng SHIEH
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Publication number: 20140193975Abstract: The invention provides a composition for forming a titanium-containing resist underlayer film comprising: as component (A), a silicon-containing compound obtained by hydrolysis and/or condensation of one or more kinds of silicon compounds shown by the following general formula (A-I) and, as component (B), a titanium-containing compound obtained by hydrolysis and/or condensation of one or more kinds of hydrolysable titanium compounds shown by the following general formula (B-I). There can be provided a composition for forming a titanium-containing resist underlayer film to form a resist underlayer film having an excellent adhesiveness in fine patterning and an excellent etching selectivity relative to a conventional organic film and a silicon-containing film.Type: ApplicationFiled: December 16, 2013Publication date: July 10, 2014Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Tsutomu OGIHARA, Takafumi UEDA, Seiichiro TACHIBANA, Yoshinori TANEDA