Abstract: In a case where a semiconductor chip is mounted over a first package, 80 pads are coupled to 80 terminals of the package, and in a case where the semiconductor chip is mounted over a second package, 100 pads are coupled to 100 terminals of the second package. An internal circuit of the semiconductor chip operates as a microcomputer with 80 terminals in a case where electrodes are insulated from each other and operates as a microcomputer with 100 terminals in a case where the electrodes are shorted therebetween by an end part of a bonding wire. Therefore, a dedicated pad for setting the number of terminals of the packages is no longer required.

Abstract: A method of measuring a parameter of a device in a circuit includes providing a device under test (DUT). The DUT includes a metal oxide semiconductor (MOS) transistor having a gate, a source, and a drain coupled to a first voltage supply node. The method further includes coupling a constant current source to the source of the transistor, coupling an operational amplifier to the transistor, and measuring a parameter of the transistor.

Abstract: A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another.

Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

Abstract: A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.

Abstract: A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

Abstract: Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages.

Abstract: A data output driver includes a pull-up output pre-driver configured to output a plurality of pull-up signals, wherein whether each of the plurality of pull-up signals is enabled is determined in accordance with a driver mode signal, a pull-down output pre-driver configured to output a plurality of pull-down signals, wherein whether each of the plurality of pull-down signals is enabled is determined in accordance with the driver mode signal, and an output driver circuit configured to output data, wherein a driver strength of the output driver circuit is determined in accordance with the pull-up signals and pull-down signals.

Abstract: A high side driver circuit includes a driver stage having an input, an output, a first power terminal and a second power terminal, a transistor having a first power terminal, a second power terminal, and a control terminal coupled to the output of the driver stage, and a switch coupled between the second power terminal of the driver stage and the second power terminal of the transistor.

Abstract: A switching device for driving a load is provided. The switching device comprises a control terminal and has a conduction threshold which, when crossed by a control signal coupled to the control terminal, causes the switching device to conduct. A control circuit for generating the control signal is also provided. The control circuit is configured to generate a control signal having a first slew rate prior to the control signal crossing the conduction threshold and a second slew rate after the control signal has crossed the conduction threshold. The first slew rate may be faster than the second slew rate.

Abstract: A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage. This configuration has lower area penalty and better noise immunity.

Abstract: A method, system, and apparatus for driving a Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) are provided. A boosting capacitor is used in combination with two drivers to efficiently provide a boosting current to the SiC JFET and then a holding current to the SiC JFET. The boosting capacitor, upon discharge, creates the boosting current and once discharged the holding current is provided by one of the first and second drivers.

Abstract: An output circuit for a bus whose output node is connected to a bus, including a first current source connected to a first reference potential, a first semiconductor switching element connected between the first current source and the output node, a current control circuit for controlling the first semiconductor switching element such that the first current source and the output node are connected when a voltage of the output node is lower than a reference voltage, and the first current source and the output node are disconnected when a voltage of the output node is higher than the reference voltage, and a voltage generating circuit which is connected between the output node and a second reference potential, and includes a second semiconductor switching element turned on/off based on an output control signal.

Abstract: A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; and an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal, the electric charge control section and the first output section being connected to each other via a relay section for either electrically connecting the electric charge control section and the first output section to each other or electrically blocking the electric charge control section and the first output section from each other, the electric charge control section including a resistor connected to a second power source.

Abstract: Disclosed are frequency dividers, methods, apparatus, and other implementations, including a frequency divider that includes at least one input line to deliver at least one signal with a first frequency, a divider stage comprising multiple divider active components to produce output signals each with a second frequency equal to substantially half the first frequency, and an input stage electrically coupled to the divider stage to enable operation of the divider stage, the input stage including multiple additional active components. Each of the output signals is electrically coupled to an input of a different corresponding component of the multiple additional active components to electrically actuate the respective different corresponding components such that each of the multiple additional active components is periodically in an ON state while during the same time at least another of the multiple additional active components of the input stage is in an OFF state.

Abstract: Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.

Abstract: Clock circuits are presented for providing a clock signal using multiple reference clock signals, including a PLL operating from a PLL reference clock signal, an FLL operating from an FLL reference clock signal, and a multiplexer circuit that selectively provides up and down signals from either a PFD of the PLL or the FLL to a charge pump of the PLL according to a reference clock select signal.

Abstract: A variable frequency synthesizer and method of outputting the variable frequency is disclosed. The synthesizer comprises a first reference frequency, a direct digital synthesizer (DDS) receiving the first reference frequency and outputting a tuned frequency, a variable frequency comb generator receiving the tuned frequency and outputting a variable frequency comb comprised of a plurality of comb lines, a mixer receiving the variable frequency comb and a signal from an oscillator and outputting an intermediate frequency, a phase lock loop (PLL) receiving a second reference frequency and the intermediate frequency and outputting a phase lock signal, and the oscillator receiving the phase lock signal and outputting a variable synthesized frequency.

Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

Abstract: A circuit comprising 1) a master delay-locked loop comprising a phase detector for receiving a reference clock and generating an output, control logic for receiving the output from the phase detector and a delta delay input and generating a control output, a clock splitter for receiving the reference clock and generating differential clock output, a delay line for receiving the differential reference clock from the clock splitter and generating n phases of differential reference clock at output, a multiplexer for receiving the output from the delay line and the control logic output and generating a clock output, wherein the phase detector is for receiving the reference clock, and 2) a slave delay-locked loop for receiving the control logic output and a strobe input and generating a delay locked loop output.

Abstract: An apparatus and method for reducing effects of spurs in a phased-locked loop having a sigma-delta modulator and digital circuits. The apparatus includes a clock dithering circuit coupled to each of the sigma-delta modulator and the digital circuits. Each clock dithering circuit is configured to dither flanks of a respective first and second clock input signal, and generate a dithered clock output signal, one for each of the sigma-delta modulator and digital circuits. A frequency of each dithered clock output signal follows a frequency of the respective first and second clock input signals, and a phase between each dithered clock output signal and the respective first and second clock input signal is shifted and constantly changing.

Abstract: Disclosed is a wave shaping apparatus and a method for shaping an input pulse train signal alternating between a low level and a high level to provide a signal delaying a turn on of one output transistor with respect to a turn off of the other output transistor thus decreasing time, when both the transistors would be simultaneously conducting current.

Abstract: A method and apparatus to independently adjust the output rise and fall time of a transmitter for the purposes of improving high-speed signaling characteristics and reducing electromagnetic interference (EMI). Also described is an apparatus to provide a high-speed edge-rate control feature. The disclosed method and apparatus for rise and fall time equalization has a closed-loop calibration system that includes an actuation apparatus within the transmitter driver, a sensing means at the output of the transmitter to measure the degree of rise/fall time imbalance, and a calibration state machine operating on the sensor output to devise correction control inputs to the actuator in the transmitter driver to correct the rise/fall time imbalance. Also described is how the actuation apparatus within the transmitter driver can further be used to provide an open-loop edge-rate control feature for the transmitter.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

Abstract: Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response.

Abstract: Described herein is an integrated circuit which comprises: a first buffer, with positive trans-conductance, to drive a first signal with first phase; and a second buffer, with negative trans-conductance, to drive a second signal with second phase, wherein the first buffer and the second buffer are cross-coupled to one another.

Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.

Abstract: A delay element delays an output signal Dt from an arithmetic circuit and outputs a delayed signal Dd. An XOR element compares the output signal Dt with the delayed signal Dd, and outputs an XORout signal with the signal value “0” when the signals match each other, and outputs an XORout signal with the signal value “1” when the signals do not match each other. In a flip-flop, when the signal value of the XORout signal at the rise of a clock of a clock signal CK is “0”, the output signal Dt is output from a flip-flop, and when the signal value of the XORout signal at the rise of the clock becomes “1” even once, a fixed value of the signal value “0” continues to be output.

Abstract: An electronic device is described, the device including a first circuit arranged to transfer a signal with a first predetermined phase shift, a second circuit, connected in series with the first circuit, arranged to transfer a signal with a second predetermined phase shift, and a resistance connected in parallel with the first and second circuits, wherein the first circuit includes a first capacitance connected between a first pair of nodes, a second capacitance connected between a second pair of nodes, and a first transformer having a first winding connected between the first pair of nodes and a second winding connected between the second pair of nodes.

Abstract: An integrated circuit includes a high voltage transistor having a first terminal coupled to sense a high voltage terminal and a control terminal coupled to a regulated voltage, which is regulated with respect to a ground terminal and is substantially less than a high voltage that the high voltage terminal is adapted to withstand. A logic gate is also included and is coupled to be powered from the regulated voltage. The logic gate has an input threshold that is less than the regulated voltage. An input terminal of the logic gate is coupled to a second terminal of the high voltage transistor. An output of the logic gate is coupled to indicate that a voltage sensed between the high voltage terminal and the ground terminal is less than the input threshold voltage of the logic gate.

Abstract: A semiconductor device including a first function block operating at a first operation voltage having a first range and for generating a data signal, a second function block operating at a second operation voltage having a second range, and a voltage level control unit for performing or not performing a level shifting operation on a voltage level of the data signal depending on the existence or non-existence of a difference between the first operation voltage and the second operation voltage, and for transmitting a level-shifted data signal or the data signal to the second function block.

Abstract: The invention provides a level shift circuit which uses a low supply voltage level shift circuit as a first level shift element and a high supply voltage level shift circuit as a second level shift element and which is configured to switch these level shift circuits in accordance with supply voltage. The low supply voltage level shift circuit is in an operating state with its power supply turned ON when supply voltage is low and in a shut-down state with the power supply turned OFF to ensure the breakdown voltages of the elements when supply voltage is high. The high supply voltage level shift circuit is in a shut-down state with its power supply turned OFF when supply voltage is low and comes into an operating state with the power supply turned ON while ensuring the breakdown voltages of elements when supply voltage is high.

Abstract: A voltage conversion mask signal generation circuit generates a first main signal and a first mask signal by converting an output signal of the first transistor to a low-side voltage, and generating a second main signal and a second mask signal by converting an output signal of the second transistor to a low-side voltage. A mask signal generation circuit generating a third mask signal with higher sensitivity than the first and second mask signals with respect to a fluctuation in the high-side reference potential. A mask logical circuit generating a fourth mask signal by performing a AND operation between the first mask signal and the second mask signal, and masking the first and second main signals with the third and fourth mask signals; and a SR flip flop circuit generating the output signal from the masked first and second main signals.

Abstract: An integrator (100) comprises an amplification and phase shifting element (170) with a feedback path (130) forming a loop and comprising a capacitive element (140). An input signal is summed into the loop, and the loop is arranged to oscillate at an oscillation frequency higher than the frequencies of interest in the input signal. The loop includes a filter (160) for attenuating the oscillation signal to ensure that the amplification and phase shifting element (170) can provide amplification for the input signal. The input signal is integrated and the integrated signal perturbs the zero crossings of the oscillation signal.

Abstract: A biquad wideband signal processing circuit can operate over bandwidths of 50 MHz to 20 GHz or more. The biquad circuit employs a configuration of integrators (transconductors), buffers, and scalable summers that can be implemented using deep sub-micron CMOS technology. Combining this scaling with high gain/high bandwidth enables implementation of feedback and programmability for broadband analog signal processing. A biquad circuit implementing a number of parallel integrator lines having adjustable gain provides greater accuracy, stability, and bandwidth, and allows for control of process variations and temperature variation in real-time.

Abstract: The current-mode CMOS logarithmic function circuit provides an ultra-low power circuit that produces an output current proportional to the logarithm of the input current. An OTA (operational transconductance amplifier) constructed from CMOS transistors, in combination with two PMOS transistors configured in weak inversion mode for providing a reference voltage input and a voltage input from the input current to the OTA, provides the circuit with a high dynamic range, controllable amplitude, high accuracy, and insensitivity to temperature variation.

Abstract: A frequency mixer is disclosed. In an implementation, the multi-LO band switched-core includes a single field-effect transistor (FET) ring having a first mixer core and a second mixer core. The first mixer core and the second mixer core configured to connect to a radio frequency (RF) port and an intermediate frequency (IF) port. The frequency mixer also includes a first local oscillator (LO) transformer and a second LO transformer. The first LO transformer is configured to furnish a first LO signal occurring in a first limited range of frequencies to the first mixer core, and the second LO transformer is configured to furnish a second LO signal occurring in a second limited range of frequencies to the second mixer core.

Abstract: A signal processing arrangement including a signal processing stage that divides an input signal (Vin) applied to a signal input (In) of the signal processing stage into at least two subsignals (Vin_a, Vin_b) as a function of a signal amplitude (A) of the input signal (Vin), wherein the signal processing stage is designed for parallel signal processing of the subsignals (Vin_a, Vin_b), and a reconstruction stage connected to the signal processing stage and provides an output signal (Vout) by weighting and combining the at least two processed subsignals (Vin_a, Vin_b).

Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.

Abstract: A load control device includes a switching unit which is connected to a power source and a load in series and has a switch device having a transistor structure, a control unit configured to control start-up and stop of the load, and a gate driving unit, which is electrically insulated from the control unit and outputs a gate driving signal to the gate electrode of the switch device. The control unit controls the gate driving unit to supply a higher driving power to the gate electrode of the switch device for a predetermined period of time starting at the start-up of the load than that in a steady state.

Abstract: A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.

Abstract: This document discusses, among other things, a signal switch circuit including a first field effect transistor (FET) configured to couple a first node to a second node in an on-state and a charge pump circuit configured to provide a first supply voltage to control the FET, wherein a reference voltage of the charge pump circuit is coupled to a well of the FET to maintain a constant gate to source voltage of the FET during the on-state.

Abstract: There is provided a high frequency switch capable of suppressing deterioration in distortion characteristics. The high frequency switch includes: a common port outputting a transmission signal to an antenna; a plurality of transmission ports each having the transmission signal input thereto; and a plurality of switching units each connected between the plurality of transmission ports and the common port to conduct or block the transmission signal from each of the transmission ports to the common port, wherein each of the switching units has one or more metal oxide semiconductor field effect transistors (MOSFETs) formed on a silicon substrate, and a capacitor connected between a body terminal of a MOSFET connected to the common port among the MOSFETs and a terminal of the MOSFET connected to the common port.

Abstract: A cascode switch includes a first power transistor configured to be coupled to a load and a second power transistor coupled in series with the first power transistor so that the second power transistor is between ground and the first power transistor. The second power transistor is operable to switch on and off responsive to a pulse source coupled to a gate of the second power transistor. The first power transistor is operable to switch on and off responsive to the same pulse source as the second power transistor or a DC source coupled to a gate of the first power transistor. Alternatively or in addition, a transistor device is coupled to the gate of the first power transistor and operable to actively turn off the first power transistor independent of the load current.

Abstract: An apparatus selectively outputs one negative voltage from among a plurality of negative voltages. The apparatus includes a first switching unit configured to perform a switching operation and output a first voltage-on signal and a first voltage-off signal according to a selection signal and a first negative voltage signal, and a second switching unit configured to perform a switching operation and to output a second voltage-on signal and a second voltage-off signal according to the selection signal and a second negative voltage signal. The apparatus also includes a driving unit to select and output one negative voltage signal from among the first and second negative voltage signals according to the first negative voltage signal, the second negative voltage signal, the first voltage-on signal, the first voltage-off signal, the second voltage-on signal, and the second voltage-off signal.

Abstract: A bias circuit for an operating transistor has a first resistor disposed in a path for supplying a bias current to a base of the operating transistor, a first transistor for applying the bias current flowing to the first resistor, a second transistor for applying a corresponding current corresponding to the bias current supplied via at least one current mirror circuit, a third transistor having bases connected in common with the first transistor for applying the corresponding current, a second resistor for applying the corresponding current and obtaining a voltage drop corresponding to a voltage drop at the first resistor, and a fourth transistor receiving a reference voltage at an emitter side and having a base connected to an emitter side of the third transistor.

Abstract: A semiconductor integrated circuit according to an embodiment includes a transfer transistor including a first gate electrode, the first gate electrode and a diffusion layer being diode-connected with a first wiring, and a clock signal line to which a clock signal is supplied, at least a portion of a first partial clock signal line, which is a portion of the clock signal line, being formed above the first gate electrode.

Abstract: A semiconductor apparatus includes a control unit configured to generate a first pumping enable signal and a second pumping enable signal which are alternately enabled, in response to an active signal; a first pumping voltage generation unit configured to perform a pumping operation during an enable period of the first pumping enable signal and generate a first pumping voltage; and a second pumping voltage generation unit configured to perform a pumping operation during an enable period of the second pumping enable signal and generate a second pumping voltage.