Abstract: Disclosed are exemplary embodiments of devices for measuring voltage of a power supply. Also disclosed are exemplary embodiments of detection devices and temperature controllers comprising such devices for measuring voltage of a power supply. In exemplary embodiments, a device for measuring the voltage of a power supply generally includes a resistor, a capacitor, and a control unit. One end of the capacitor is connected with the resistor, while the other end of the capacitor is connected to ground. The control unit is connected with the power supply. The control unit includes a comparator connected with the capacitor, a reference power supply connected with the comparator, a timer, and a computing unit.

Abstract: A capacitance type occupant detection sensor includes a capacitive sensor, a reference electrode, a voltage application part, a current detector, a capacitance calculator, and a determination part. The capacitive sensor has a main electrode and is placed to a vehicle seat. The reference electrode is applied with reference voltage. The voltage application part applies detection voltage to the main electrode. The current detector detects detection current flowing through the main electrode. The capacitance calculator calculates a first capacitance between the main electrode and the reference electrode. The determination part determines an occupant of a vehicle. The capacitive sensor has a sub electrode. The determination part switches between an occupant detection mode and a wet detection mode. The capacitance calculator calculates first conductance, a second conductance, and a third conductance. The determination part determines whether the occupant exists and whether the vehicle seat is wet.

Abstract: In a method for producing a sensor element, a silicon nanowire having a diameter less than 50 nm is contacted via at least two points by electrodes. The nanowire and the electrodes are arranged on one plane on a substrate. Catalytically active metal nanoparticles having a diameter in the range of 0.5-50 nm are deposited on the surface of an insulating substrate and the surface and the metal nanoparticles deposited thereon are exposed to a gas flow containing a gaseous silicon component at a temperature in the range of 300-1100° C., whereupon, during a time period in the range of 10-200 minutes, a nanowire of a length in the range of 5-200 ?m projecting from the substrate is formed.

Abstract: Provided is an apparatus for determining the type of an analog sensor. The apparatus for determining the type of an analog sensor includes a determination module configured to receive an output signal output from the sensor and output a determination reference signal for determining the type of the sensor, and a controller configured to apply the output signal from the sensor to the determination module and determine the type of the sensor using the determination reference signal output from the determination module.

Abstract: A method may include applying a first current through the memory element and a first selection component. The memory element and the first selection component may be located along a memory line. The method may also include measuring a first potential difference across the memory line. The method may further include applying a second current through a second selection component, wherein the second selection component is located along a dummy line, and measuring a second potential difference across the dummy line. The method may additionally include determining the resistance of the memory element based on the first potential difference and the second potential difference. The first selection component may be activated and the second selection component may be deactivated to apply the first current. The first selection component may be deactivated and the second selection component may be activated to apply the second current.

Abstract: Method to extract timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning the incident laser beam on circuit feature of interest, temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. A Single-Photon Laser-Assisted Device Alteration apparatus applies picosecond laser pulses of wavelength having photon energy equal to or greater than the silicon band-gap. A Two-Photon Laser-Assisted Device Alteration apparatus applies femtosecond laser pulses of wavelength having photon energy equal to or greater than half the silicon band-gap at the area of interest. The laser pulses are synchronized with test vectors so that pass/fail ratios can be altered using either the single-photon or the two-photon absorption effect. A sequence of synthetic images with error data illustrates timing sensitive locations.

Abstract: A testing apparatus for providing per pin level setting is disclosed, and the testing apparatus includes a control unit and a filter circuit, where the control unit is electrically connected to the filter circuit. The control unit includes a field programmable gate array (FPGA) for providing a PWM signal. The filter circuit receives the PWM signal and outputs at least one DC voltage.

Abstract: An electronic package that has an array of pins may be tested for shorts and continuity in a parallel manner. The array of pins are allocated to four or more groups of pins such that each pin in each group is not adjacent to a pin from its own group of pins. One of the groups of pins is tested for continuity while placing a reference voltage level on all of the pins in the other groups of pins. A separate current source is coupled to each pin and a resultant voltage is measured. A short between one of the pins in the first group and a pin in one of the other groups can be detected when the resultant voltage on one of the pins in the first group is approximately equal to the reference voltage. Group-wise testing is repeated until all groups have been tested.

Abstract: A method of estimating stator resistance of an induction motor is provided. The method includes applying voltage pulses through two phase paths of the motor for a plurality of electrical cycles to inject current in the motor, wherein the voltage pulses are applied until rotor flux of the motor is substantially stabilized and measuring stator voltage and stator current in response to the applied voltage pulses for each of the plurality of electrical cycles. The method also includes calculating the stator resistance based upon the measured stator voltages and the stator currents.

Abstract: According to one embodiment, a semiconductor device includes a termination circuit and a controller. The termination circuit includes a first resistor connected to an external connection terminal, a plurality of first transistors of a first conductive type connected in parallel between the first resistor and a voltage source, a second resistor connected to the external connection terminal, and a plurality of second transistors of a second conductive type connected in parallel between the second resistor and ground. The controller is configured to control switching of the first and second transistors such that a combined resistance value of the first and second resistors and the termination circuit is constant.

Abstract: Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction.

Abstract: An application specific integrated circuit (ASIC) that includes a digital signal processing (DSP) core and a configurable logic block coupled to the DSP core. The configurable logic block including a plurality of interconnected logic modules to apply a pre-configured logic function to an input. Each of the plurality of logic modules including a controller and a plurality of logic components, the controller of each logic module dynamically reconfigures the connections between the controller's logic module and another logic module.

Abstract: To provide a charge pump circuit to manufacture a low-power-consumption PLD. A semiconductor device includes a first circuit and a second circuit electrically connected to the first circuit. A charge pump circuit formed of a transistor including an oxide semiconductor and a boosting control circuit controlling the charge pump circuit are provided between the first circuit and the second circuit. The first circuit and the charge pump circuit operate at first power supply voltage, and the boosting control circuit and the second circuit operate at second power supply voltage. The first power supply voltage is lower than the second power supply voltage.

Abstract: A programmable logic device that includes a storage device having smaller area and lower power consumption is provided. The programmable logic device includes a logic block including a storage device. The storage device includes a plurality of groups each including at least a first switch, a transistor that is turned on or off in accordance with a signal including configuration data input to a gate of the transistor through the first switch, and a second switch controlling the electrical connection between a first wiring and a second wiring together with the transistor when the second switch is turned on or off in accordance with the potential of the first wiring. In the logic block, the relationship between the logic level of a signal input and the logic level of a signal output is determined in accordance with the potential of the second wiring.

Abstract: A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.

Abstract: Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.

Abstract: A PLL circuit includes a divider configured to generate a divided signal having a cycle of T/M (where M is an integer greater than or equal to two) by dividing an oscillation signal; a phase comparator configured to generate a phase comparison result by calculating an exclusive logical OR of M reference signals and the divided signal, the M reference signals having the cycle of T and respective time intervals shifted sequentially by T/2M; a loop filter configured to generate a voltage signal using the phase comparison result as input; and a voltage-controlled oscillator configured to generate the oscillation signal by oscillating at a frequency depending on the voltage signal.

Abstract: Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.

Abstract: Buffers, integrated circuits, apparatuses, and methods for adjusting drive strength of a buffer are disclosed. In an example apparatus, the buffer includes a driver. The driver includes a pull-up circuit coupled to a supply voltage node and an output node, and also includes a pull-down circuit coupled to a reference voltage node and the output node. A drive adjust circuit is coupled to at least one of the pull-up circuit and the pull-down circuit, with the drive adjust circuit configured to receive a feedback signal and, based at least in part on the feedback signal, adjust a current conducted through the at least one of the pull-up and pull-down circuits.

Abstract: A driver circuit for a semiconductor switching device includes a drive power source, a capacitor and four switches, which form a bridge circuit. The capacitor is provided between the four switches. In one cycle of application of a voltage to a gate of the semiconductor switching device to turn on the semiconductor switch, the first and the second switches, which are diagonal, are turned off and the third and the fourth switches, which are diagonal, are turned on to charge the capacitor. Then only the first switch is turned on to apply the voltage to the gate, and lastly only the second switch is turned on to discharge the capacitor thereby to apply a negative voltage to the gate of the semiconductor switching device.

Abstract: A method, system, and apparatus for driving a Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) are provided. A boosting capacitor is used in combination with two drivers to efficiently provide a boosting current to the SiC JFET and then a holding current to the SiC JFET. The boosting capacitor, upon discharge, creates the boosting current and once discharged the holding current is provided by one of the first and second drivers.

Abstract: A power on reset circuit including: a startup circuit keeping an operation signal in an operating state during a power supply rises; a bias circuit keeping the operation signal in the operating state; a BGR circuit being activated during the operating state, and outputting a fixed voltage after a predetermined time elapses; a power supply divided voltage generation circuit outputting a reference voltage; an activation detection circuit generating a control signal which becomes inactive when a power supply rises and becomes active when the fixed voltage reaches a predetermined level; a comparator circuit outputting a power on signal and detecting as the power on signal when the reference voltage is greater than the fixed voltage; and a switch turning on and fixing an output of the comparator circuit to an inactive logical value while the control signal is inactive, and turning off while the control signal is active.

Abstract: A power-on circuit is connected to a video graphics array (VGA) connector of a display, a power supply unit (PSU), and a super input output (SIO) chip of a motherboard. The power-on circuit includes first to fourth electronic switches. The VGA connector is connected to the first electronic switch. The first electronic switch is connected to the second electronic switch. The second electronic switch is respectively connected to the third electronic switch and the fourth electronic switch. The fourth electronic switch is connected to the SIO chip. The power-on circuit could power on the motherboard via the power button on the display.

Abstract: A PLL circuit generating a generated clock in synchronization with an external clock by a phase locked loop includes a first detector for detecting whether or not the generated clock is in synchronization with the external clock, and a measuring device for measuring at least one of a high time from a rise to a fall of the external clock and a low time from a fall to a rise thereof. In a state that the generated clock and the external clock are in synchronization, when it is detected that a fluctuation of the high time or the low time becomes equal to or more than a predetermined value, the PLL circuit fixes a frequency of the generated clock to a frequency outputted at this time point, and continues output of the generated clock having the fixed frequency.

Abstract: A PLL circuit that operates in synchronization with an operating clock and generates and outputs a generated clock in synchronization with an external clock, including a multi-phase clock generating unit that generates multi-phase clocks including n clocks which have a same frequency and differ in phase one another, one of the clocks in the multi-phase clock being the operating clock, a frequency signal generating unit that outputs a frequency signal based on a phase difference signal from a phase comparator, an oscillating unit that generates and outputs a clock oscillating with a frequency corresponding to the frequency signal, and the phase comparator that measures a time difference between rising times or falling times of the inputted external clock and the oscillating unit based on the n clocks in the multi-phase clocks, and outputs a phase difference signal indicating the time difference based on a result of the measurement.

Abstract: According to one embodiment, a semiconductor device includes a first differential amplifier and a second differential amplifier. The first differential amplifier charges the first output terminal with a second voltage different from a first voltage. The first differential amplifier uses a first clock signal, stopping the charging at the first output terminal, receives first complementary data of the first voltage at the rising edge of a second clock signal, and outputs the first complementary data at the second voltage. The second differential amplifier charges the second output terminal with the second voltage. The second differential amplifier uses a third clock signal, stopping the charging at the second output terminal, receives second complementary data of the first voltage at the rising edge of a fourth clock signal, and outputs the second complementary data at the second voltage.

Abstract: A current-mode D latch includes a first load element, a second load element, a first bias current source, a first switch transistor, a second switch transistor, a first stage circuit and a second stage circuit. The first switch transistor is controlled by an inverted reset signal. The second switch transistor is controlled by a reset signal. When an inverted clock signal is in a first level state and the reset signal is inactive, the first input signal is converted into the first output signal and the first inverted input signal is converted into the first inverted output signal by the first stage circuit. When a clock signal is in the first level state and the reset signal is inactive, the first output signal and the first inverted output signal are maintained by the second stage circuit.

Abstract: A root-mean-square (RMS) detector includes detection circuitry having as an input a radio frequency signal, target voltage and a set voltage and a RMS signal as an output, and a gain stage within the detection circuitry to produce the RMS signal as an output. The gain stage provides for faster settling times of the detector.

Abstract: A signal generation circuit includes a limiter and a mixer. The limiter receives an input signal, allows the input signal to be off a scale at a limit voltage, and generates a phase signal indicating a phase component of the input signal. The mixer receives the input signal and the phase signal, and generates an amplitude signal indicating an amplitude component of the input signal.

Abstract: Waveforms generators include a splitter that splits a digital input signal into a number of split signals each having a split signal frequency bandwidth that is substantially similar to a digital input signal frequency bandwidth. The split signals are mixed with associated digital, harmonic signals to generate a number of digital, mixed signals, which are then converted to analog signals at an effective sample rate that is different from a first order harmonic signal of at least one of the digital, harmonic mixers. A number of analog, harmonic mixers mix the associated analog signals with associated analog, harmonic signals to generate mixed, analog signals. The mixed, analog signals are combined into an output signal having an output signal bandwidth that is greater than a bandwidth of at least one of the number of DACs.

Abstract: A capacitive switch includes: a first conductive cantilever, a second conductive cantilever, a substrate, a coplanar waveguide arranged on the substrate, the coplanar waveguide includes a first conductor configured to transmit an electrical signal, a second conductor and a third conductor are arranged as ground wires on two sides of the first conductor; an insulation medium layer is arranged on the first conductor, a conducting layer is arranged on the insulation medium layer; the first conductive cantilever is connected to the second conductor by using a first fixed end, the second conductive cantilever is connected to the third conductor by using a second fixed end; when a direct-current signal is transmitted on the capacitive switch, a first free end of the first conductive cantilever and a second free end of the second conductive cantilever contact the conducting layer.

Abstract: A stack package may include a plurality of chips stacked with a plurality of layers; and a chip selection controller configured to provide a reference and chip selection control signal to the plurality of chips. Each chip may comprise: a reference signal controller configured to transmit the reference signal through a first line interconnecting the plurality of chips; a chip selection delay unit configured to control a delay timing point of the chip selection control signal to transmit the control result to each node of a second line interconnecting the plurality of chips; a delay-time-difference sensing unit configured to calculate a delay time difference between a signal applied to each node of the first and second line to generate chip selection information corresponding to the calculated delay time difference; and a memory unit configured to store the chip selection information.

Abstract: Charge pump systems and methods for the operation thereof can be configured for delivering charge to a primary circuit node. A sequential charging pattern of at least a subset of a series-connected plurality of charge-pump stages connected between a supply voltage node and the primary circuit node can be selectively initiated. For example, the sequential charging pattern can be initiated one time for every N cycles of a given clock signal, wherein N is a selectively adjustable integer value greater than or equal to 1.

Abstract: An integrated circuit includes a first circuit. The first circuit includes a first transistor having a first dopant type. The first circuit further includes a first cascode transistor having the first dopant type, wherein the first cascode transistor connected in series with the first transistor. The first circuit further includes a second transistor having a second dopant type opposite to the first dopant type, wherein the second transistor is connected in series with the first transistor. The first circuit includes a second cascode transistor having the second dopant type, wherein the second cascode transistor is connected in series with the second transistor. The integrated circuit further includes a first bias circuit configured to adjust a threshold voltage of at least one of the first cascode transistor or the second cascode transistor.

Abstract: A transconductance adjusting circuit includes: a voltage generating section configured to generate a first differential voltage; a first transconductance amplifier configured to receive the first differential voltage through a first positive-phase voltage transmission line and a first reversed-phase voltage transmission line, and output a second differential voltage through a second positive-phase voltage transmission line and a second reversed-phase voltage transmission line; a first control section configured to receive the second differential voltage and supply a first control voltage to the first transconductance amplifier; a second control section configured to receive the second differential voltage and supply a second control voltage to the first transconductance amplifier; a first resistor section that makes a connection between the first positive-phase voltage transmission line and the second positive-phase voltage transmission line; and a second resistor section that makes a connection between the f

Abstract: An apparatus that amplifies a signal, includes an amplifier configured to amplify the signal. The apparatus further includes a current supplier configured to supply a periodically variable current to the amplifier.

Abstract: A Class-D amplifier includes a pre-amplifier having an input configured to receive an amplifier reference voltage signal which is ramped at start-up at a fast rate. An integrator has a first input configured to receive an input signal from the pre-amplifier and a second input configured to receive an integrator reference voltage signal which is ramped at start-up at a slower rate. A modulator has an input coupled to an output of the integrator. The modulator generates a pulse width modulated output signal. Operation of the Class-D amplifier is controlled at start-up by applying a slow ramped signal as the integrator reference voltage signal and a fast ramped signal as the amplifier reference voltage so that the pulse width modulated output signal exhibits an increasing change in duty cycle in response to an increasing voltage of the integrator reference voltage signal, and no “pop” is introduced at start-up.

Abstract: A method for operating an amplifier module of a communication satellite involves establishing an undesired state of the amplifier module, storing state data, which indicate the undesired state, in a nonvolatile memory of the amplifier module, after the undesired state has been established, and deactivating the amplifier module after the storage of the state data.

Abstract: An output buffer circuit of a source driver includes an operational amplifier, having a first terminal as an output of the operational amplifier, and an output control unit, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, to generate a variable impedance of a signal output path between the first terminal and the second terminal, wherein when the operational amplifier charges or discharges the second terminal to reach a predetermined level, the output control unit change a value of the variable impedance of the signal output path.

Abstract: An envelope-tracking (ET) power supply may include a boost control pin. The boost control pin receives a boost enable signal that activates or enables a supplemental power supply in the ET power supply. The supplemental power supply facilitates the generation of a power supply signal for a selected processing stage, e.g., a power amplifier. The supplemental power supply helps the processing stage meet the demands on it caused by the signal that the processing stage needs to handle.

Abstract: A control device of a power amplifier includes: a limiter configured to limit a level of an input signal to the power amplifier; and a control unit configured to, when the limiter operates, make an operation voltage of the power amplifier invariable and control load of an output matching circuit of the power amplifier based on an amplitude of the input signal, and, when the limiter does not operate, to make the load of the output matching circuit invariable and control the operation voltage of the power amplifier.

Abstract: A power supply injects a series of “tickle” pulses into a pulse width modulated (PWM) controller to induce the controller to generate PWM pulses at a minimum switching frequency, preferably one that is super-sonic (especially for audio applications). The switching frequency may also be selected or controlled such that it avoids resonances in the power supply. The “tickle” pulses may be clocked by the same clock that times the PWM controller, and they may be shaped to help ensure that the power supply maintains some regulation during low-load conditions.

Abstract: An impedance matching network for a radio frequency (RF) amplifier includes multiple stages connected to each other in a first to last order. A first stage produces an RE output signal, and a last stage receives an RF input signal. Each stage includes a first inductor connected to produce an output signal, a second inductor connected to receive an input signal from a next stage, a capacitor connected between the first and second inductors and a ground. In addition, each stage other than the first stage further includes a first switch to by-pass the first and second inductors, a second switch connected between the first and second inductors and the ground, and a controller for controlling, the first and second switches to select a particular power level of a set of power levels.

Abstract: An electronic biasing circuit provides a DC bias voltage to a circuit to be biased. The biasing circuit has a first transistor and a second transistor. A gate of the first transistor is connected to a gate of the second transistor and supplies the DC bias voltage. A source of the first transistor is connected to a supply reference voltage. A source of the second transistor is connected to the supply reference voltage via a resistor element. The currents flowing through the first and second transistor are forced to be equal. A third transistor is connected in series with the first transistor and a fourth transistor is connected in series with the second transistor. Currents flowing through the third and fourth transistors are forced to be equal.

Abstract: According to one embodiment, an amplification device includes an input terminal into which an input signal is inputted, a first amplifier, an output terminal, a variable impedance module connected at an output end of the first amplifier, a second amplifier, a reference impedance element connected at an output end of the second amplifier, a magnitude comparator, a phase comparator, and a controller. The controller is configured to control impedance of the variable impedance module so that impedance at a point between the first amplifier and the variable impedance approaches a first value.

Abstract: In a portable radio transceiver, a power amplifier system includes a saturation detector that detects power amplifier saturation in response to duty cycle of the amplifier transistor collector voltage waveform. The saturation detection output signal can be used by a power control circuit to back off or reduce the amplification level of the power amplifier to avoid power amplifier control loop saturation.

Abstract: An radio frequency amplifying circuit includes an amplifying transistor configured to amplify a radio frequency signal input to a base of the amplifying transistor via a matching network to output the amplified radio frequency signal, a first bias transistor connected to the amplifying transistor based on a current-mirror connection to supply a bias to the amplifying transistor, and a second bias transistor connected to the base of the amplifying transistor based on an emitter-follower connection to supply a bias to the amplifying transistor.

Abstract: A radio frequency amplification stage comprising: an amplifier for receiving an input signal to be amplified and a power supply voltage; and a power supply voltage stage for supplying said power supply voltage, comprising: means for providing a reference signal representing the envelope of the input signal; means for selecting one of a plurality of supply voltage levels in dependence on the reference signal; and means for generating an adjusted selected power supply voltage, comprising an ac amplifier for amplifying a difference between the reference signal and one of the selected supply voltage level or the adjusted selected supply voltage level, and a summer for summing the amplified difference with the selected supply voltage to thereby generate the adjusted supply voltage.

Abstract: An electronic oscillator circuit has a first oscillator, for supplying a first oscillation signal, a second oscillator, for supplying a second oscillation signal, a first controller for delivering the first control signal as a function of a phase difference between a first controller input and a second controller input of the first controller; a second controller for delivering the second control signal as a function of a phase difference between a first controller input of the second controller and a second controller input of the second controller; a resonator; at least a second resonance frequency, with a first phase shift dependent on the difference between the frequency of a second exciting signal and the second resonance frequency and processing means, for receiving the first oscillator signal and the second oscillator signal, determining their mutual proportion, looking up a frequency compensation factor in a prestored table and outputting a compensated oscillation signal.

Abstract: An optical module for an atomic oscillator using a quantum interference effect includes a light source part to emit resonant light having two different wavelengths, a gas cell in which an alkali metal atom gas is enclosed and to which the resonant light is irradiated, a light detection part to detect an intensity of the resonant light transmitted through the gas cell, and a gas-flow generation part to generate a flow of the alkali metal atom gas.