Abstract: Disclosed is an integrated circuit comprising a substrate (10) including at least one light sensor (12); an interconnect structure (20) over the substrate; at least one passivation layer (30) over the interconnect structure, said passivation layer including a first area over the at least one light sensor; and a gas sensor such as a moisture sensor (50) at least partially on a further area of the at least one passivation layer, wherein the gas sensor comprises a gas sensitive layer (46?) in between a first electrode (42) and a second electrode (44), the gas sensitive layer further comprising a portion (46?) over the first area. A method of manufacturing such an IC is also disclosed.

Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.

Abstract: The present invention relates to a CMOS compatible MEMS microphone, comprising: an SOI substrate, wherein a CMOS circuitry is accommodated on its silicon device layer; a microphone diaphragm formed with a part of the silicon device layer, wherein the microphone diaphragm is doped to become conductive; a microphone backplate including CMOS passivation layers with a metal layer sandwiched and a plurality of through holes, provided above the silicon device layer, wherein the plurality of through holes are formed in the portions thereof opposite to the microphone diaphragm, and the metal layer forms an electrode plate of the backplate; a plurality of dimples protruding from the lower surface of the microphone backplate opposite to the diaphragm; and an air gap, provided between the diaphragm and the microphone backplate, wherein a spacer forming a boundary of the air gap is provided outside of the diaphragm or on the edge of the diaphragm; wherein a back hole is formed to be open in substrate underneath the diaph

Abstract: Disclosed herein an inertial sensor and a method of manufacturing the same. An inertial sensor 100 according to a preferred embodiment of the present invention is configured to include a plate-shaped membrane 110, a mass body 120 that includes an adhesive part 123 disposed under a central portion 113 of the membrane 110 and provided at the central portion thereof and a patterning part 125 provided at an outer side of the adhesive part 123 and patterned to vertically penetrate therethrough, and a first adhesive layer 130 that is formed between the membrane 110 and the adhesive part 123 and is provided at an inner side of the patterning part 125. An area of the first adhesive layer 130 is narrow by isotropic etching using the patterning part 125 as a mask, thereby making it possible to improve sensitivity of the inertial sensor 100.

Abstract: A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.

Abstract: Methods for forming a back contact on a thin film photovoltaic device are provided that include applying a conductive paste onto a surface defined by a p-type absorber layer (e.g., comprising cadmium telluride) of a p-n junction and curing the conductive paste to form a conductive coating on the surface defined by a p-type absorber layer of the p-n junction. The conductive paste can include a conductive material, a solvent system, and a binder such that during curing an acid from the conductive paste reacts to enrich the surface with tellurium while copper is deposited onto the Te enriched surface. The acid is then substantially consumed during curing.

Abstract: Vapor deposition apparatus for forming stacked thin films on discrete photovoltaic module substrates conveyed in a continuous non-stop manner through the apparatus are provided. The apparatus includes a first sublimation compartment positioned over a first deposition area of said apparatus, a second sublimation compartment positioned over a second deposition area of said apparatus, and an internal divider positioned therebetween and defining a middle seal member. An actuator is attached to the internal divider and is configured to move the internal divider to control intermixing of first source material vapors and second source material vapors within the first deposition area and the second deposition area. Methods are also generally provided for depositing stacked thin films on a substrate.

Abstract: Scribing and deposition processes can be used to interconnect cells within photovoltaic modules.

Abstract: A method of manufacturing a light absorbing layer for a solar cell by performing thermal treatment on a specimen configured to include thin films of one or more of copper, indium, and gallium on a substrate and element selenium, includes steps of: heating a wall of a chamber up to a predefined thin film formation temperature in order to maintain a selenium vapor pressure; mounting the specimen and the element selenium on the susceptor at the room temperature and loading the susceptor in the chamber; and heating the specimen in the lower portion of the susceptor and, at the same time, heating the element selenium in the upper portion of the susceptor.

Abstract: A deposition apparatus for performing a deposition process on a substrate includes: an injection unit including a plasma generating member which receives a raw material gas and converts the raw material gas to a deposition source material in a radical form; and a plasma processor disposed adjacent to the injection unit and facing a side of the injection unit, wherein the plasma processor performs a plasma process in a direction facing the substrate.

Abstract: A display panel manufacturing method includes forming a gate electrode on a substrate and a gate insulator, a semiconductor layer, and an etch stop layer covering the gate electrode. A photoresist layer covering on the etch stop layer is pattern from two opposite side of the substrate by two photolithography processes to form a photoresist pattern. The etch stop layer is dry etched to form an etch stop pattern via the photoresist pattern. The photoresist pattern is formed again by two photolithography processes. The semiconductor layer is wet etched to form a semiconductor pattern via the photoresist pattern. A source electrode and a drain electrode is formed corresponding to two opposite sides of the gate electrode to orderly cover the etch pattern, the semiconductor pattern, and the gate insulator.

Abstract: An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith.

Abstract: Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.

Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.

Abstract: A method is described for interconnecting first, 27, and second, 22, components on a substrate, 21. The method comprises attaching said first component, 27, to said substrate, attaching said second component, 22, to said substrate, 21, said first and second components being positioned relative to each other on said substrate to form a gap, 31, therebetween. The method further comprises the step of depositing a layer, 24, of electrically insulating material in said gap, and electrically connecting said first component, 27, with said second component, 22, by depositing, upon said electrically insulating layer, a layer of electrically conducting material, 26, which is in contact with and extends from a surface of said first electronic component, across said gap, 31, and said layer of electrically insulating material, 24, and to a surface of said second electronic component, 22. The method is characterized in that a plasma deposition process is used to deposit at least one of said layers of material.

Abstract: A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends. Injecting liquid solder into the reservoirs and allowing it to cool provides solidified solder on the distal ends, which after mask removal produces a solder bumped substrate which we position on a wafer to leave a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating joins the wafer and substrate. The gap is optionally filled with a material comprising an underfill.

Abstract: A method for manufacturing an IGBT includes: forming oxide layers on the surfaces of the front and the back of an N-type substrate; forming a buffer layer in the surface of the back of the N-type substrate; forming protection layers on the surfaces of the oxide layers; removing the protection layer and the oxide layer overlying the front of the N-type substrate while reserving the oxide layer and the protection layer on the back of the N-type substrate for protection of the back of the N-type substrate; forming a front IGBT structure and applying a protection film on the surface of the front IGBT structure for protection of the front IGBT structure; removing the protection layer and the oxide layer overlying the back of the N-type substrate; forming a back IGBT structure and a back metal layer; and removing the protection film overlying the surface of the front IGBT structure.

Abstract: A method for manufacturing a semiconductor device, includes providing a silicon semiconductor substrate which is manufactured by a floating zone method; and performing thermal diffusion at a heat treatment temperature that is equal to or higher than 1290° C. and that is lower than a melting temperature of a silicon crystal to form a diffusion layer with a depth of 50 ?m or more in the silicon semiconductor substrate, the thermal diffusion including a first heat treatment performed in an oxygen atmosphere or a mixed gas atmosphere of oxygen and inert gas, and a second heat treatment performed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen to form the diffusion layer. The method suppresses the occurrence of crystal defects, reduces the amount of inert gas used, and reduces manufacturing costs.

Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is carbon-containing silicon nitride formed using a hydrocarbon reagent. A second layer of the hard mask is chlorine-containing silicon nitride formed on the first layer using a chlorinated silane reagent. After SiGe epitaxial source/drain regions are formed, the hard mask is removed using a wet etch which removes the second layer at a rate at least three times faster than the first layer.

Abstract: A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element. A first annealing process is performed, wherein an intrinsic stress is created at least in the first semiconductor material by stress memorization, and thereafter the first portion of the dielectric layer is removed. A layer of a metal is formed, and a second annealing process is performed, wherein the metal and the first semiconductor material react chemically to form a silicide. The second portion of the dielectric layer substantially prevents a chemical reaction between the second semiconductor material and the metal.

Abstract: A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

Abstract: A method of manufacturing a package may include: providing a first device having a first redistribution layer (RDL) and an insulator layer disposed over the first RDL; and forming a first micro-bump line over the insulator layer of the first device. The first micro-bump line may extend laterally over a surface of the insulator layer facing away from the first RDL, and a first inductor of the package comprises the first RDL and the first micro-bump line.

Abstract: The method includes forming an array of first separation walls on an underlying layer. A block co-polymer (BCP) layer is formed to fill inside regions of the first separation walls and gaps between the first separation walls. The BCP layer is phase-separated to include first domains that provide second separation walls covering inner sidewalls and outer sidewalls of the first separation walls and second domains that are separated from each other by the first domains.

Abstract: A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.

Abstract: Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.

Abstract: Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device.

Abstract: Embodiments of mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. Embodiments of mechanisms for a hybrid bonding and a integrated system are also provided.

Abstract: The invention relates to a process for thinning the active silicon layer of a substrate, which comprises an insulator layer between the active layer and a support, this process comprising one step of sacrificial thinning of active layer by formation of a sacrificial oxide layer by sacrificial thermal oxidation and deoxidation of the sacrificial oxide layer. The process is noteworthy in that it comprises: a step of forming a complementary oxide layer, on the active layer, using an oxidizing plasma, this layer having a thickness profile complementary to that of oxide layer, so that the sum of the thicknesses of the oxide layer and of the sacrificial silicon oxide layer are constant over the surface of the treated substrate, a step of deoxidation of this oxide layer, so as to thin active layer by a uniform thickness.

Abstract: To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.

Abstract: A substrate carrier arrangement (10, 11) for a coating system (12) is provided, comprising a carrier (1) which comprises at least one support region (3) having a support surface (30), on which a substrate support (2) is arranged, and which support region comprises in the support surface (30) at least one first and one second gas inlet (4, 5), wherein the first gas inlet (4) is at a smaller distance from a center (M) of the support surface (30) than the second gas inlet (5) and wherein the first and second gas inlet (4, 5) comprise mutually independent gas feeds (40, 50) which are arranged to supply gases having mutually different thermal conductivities. A coating system comprising a substrate carrier arrangement and a method for performing a coating process are also provided.

Abstract: A semiconductive substrate (1) is described that is suitable for realising electronic and/or optoelectronic devices of the type comprising at least one substrate (3), in particular of single crystal silicon, and an overlying layer of single crystal silicon (5). Advantageously, according to the invention, the semiconductive substrate (1) comprises at least one functional coupling layer (10) suitable for reducing the defects linked to the differences in the materials used. In particular, the functional coupling layer 10 comprises a corrugated portion (6) made in the layer of single crystal silicon (5) and suitable for reducing the defects linked to the differences in lattice constant of such materials used.

Abstract: An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.

Abstract: A method of fabricating a semiconductor device may include conformally forming a gate insulating layer on a substrate having a recess, conformally forming a barrier layer containing fluorine-free tungsten nitride on the substrate with the gate insulating layer using an atomic layer deposition process, and forming a gate electrode on the barrier layer to fill at least a portion of the recess.

Abstract: Embodiments of the disclosure generally relate to methods of adjusting transistor flat band voltage, and transistor gates formed using the same. In one embodiment, a method sequentially includes cleaning a substrate, annealing the substrate in a nitrogen-containing environment to form silicon-nitrogen bonds, hydroxylating the substrate surface, and depositing a hafnium oxide layer over the substrate. In another embodiment, the method further includes depositing an aluminum oxide layer over the substrate prior to depositing the hafnium oxide layer, and then annealing the substrate.

Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.

Abstract: According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.

Abstract: A method of manufacturing a spacer for an electronic memory including a substrate; a first gate structure; a stack including a plurality of layers whereof at least one of the layers is able to store electric charges, the method including depositing a spacer material layer, at least on the area covered by the stack; ion beam machining the spacer material layer, the ion beam machining being carried out with controlled stopping so as to preserve a residual portion of the thickness of the spacer material layer covering the stack; plasma etching the residual portion of the thickness of the spacer material layer.

Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.

Abstract: A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure.

Abstract: The invention relates to a method for manufacturing a semiconductor wafer including a conductive via extending from a main surface of the wafer, said the via having a shape factor greater than five, the wafer including a dielectric layer, the method including: producing, by means of deep etching, at least one recess in the semiconductor wafer, the recess extending from the main surface of the wafer and having a shape factor greater than five, the recess including a side surface; forming at least one dielectric layer in the recess, including two treatments in a controlled-pressure reactor, one of said the treatments including the chemical vapor deposition, at sub-atmospheric pressure, of a dielectric onto the side surface of the recess, the chemical deposition being carried out at a temperature lower than 400° C.

Abstract: A method for processing a workpiece may include: providing a workpiece including a first region and a second region; forming a porous metal layer over the first region and the second region; wherein the first region and the second region are configured such that an adhesive force between the second region and the porous metal layer is lower than an adhesive force between the first region and the porous metal layer.

Abstract: A method of depositing a film is provided. In the method, one operation of a unit of film deposition process is performed by carrying a substrate into a processing chamber, by depositing a nitride film on the substrate, and by carrying the substrate out of the processing chamber after finishing depositing the nitride film on the substrate. The one operation is repeated a predetermined plurality of number of times continuously to deposit the nitride film on a plurality of substrates continuously. After that, an inside of the processing chamber is oxidized by supplying an oxidation gas into the processing chamber.

Abstract: Provided is a polishing method including a step of preparing a substrate having (1) silicon nitride as a stopper, and to a direction of a surface subjected to polishing from the stopper, (2) at least a portion of a wiring metal, and (3) at least a portion of an insulating material; a step of supplying a CMP slurry, and thereby polishing the (2) wiring metal and (3) insulating material on the direction of the surface subjected to polishing; and a step of stopping polishing before the (1) silicon nitride is exposed and completely removed, in which method the CMP slurry contains (A) a copolymer of (a) a monomer that is anionic and does not contain a hydrophobic substituent and (b) a monomer containing a hydrophobic substituent; (B) an abrasive grain; (C) an acid; (D) an oxidizing agent; and (E) a liquid medium, the component (B) has a zeta potential of +10 mV or more in the CMP slurry, and the copolymerization ratio (a):(b) of the component (A) is 25:75 to 75:25 as a molar ratio, with the pH being 5.0 or less.

Abstract: A composition for forming a resist underlayer film for lithography, including a polymer having a repeating structural unit of Formula (1): R1 is a hydrogen atom or a methyl group and Q1 is a group of Formula (2) or Formula (3): (wherein R2, R3, R5, and R6 are independently a hydrogen atom or a linear or branched hydrocarbon group having a carbon atom number of 1 to 4, R4 is a hydrogen atom or a methyl group, R7 is a linear or branched hydrocarbon group having a carbon atom number of 1 to 6, a C1-4 alkoxy group, a C1-4 alkylthio group, a halogen atom, a cyano group, or a nitro group, w1 is an integer of 0 to 3, w2 is an integer of 0 to 2, and x is an integer of 0 to 3), and v1 and v2 are independently 0 or 1; and an organic solvent.

Abstract: A method of fabricating multiple gate lengths simultaneously on a single chip surface. Hard masking materials which are used as spacers in a field effects transistor generation process are converted into a spacer mask to increase the line density on the chip surface. These hard masking spacers are further patterned by either trimming or by enlarging a portion of a spacer at various locations on a chip surface, to enable formation of multiple gate lengths on a single chip, using a series of process steps which make use of combinations of hydrophobic and hydrophilic materials.