Abstract: Process and dosing station (1) for the preparation of a solution of a non-caking agent, wherein a concentrate of the non-caking agent is circulated in a loop (6) and wherein the concentrate is subsequently diluted by water to obtain the solution. A flow of the concentrate can be drawn from the circulation loop (6) and mixed with a flow of water. The obtained solution can subsequently be fed into a second recirculation loop (12). A flow of solution can be drawn off from the second recirculation loop for being dosed into an amount of salt.

Abstract: OLED materials having the formula: T-A(-S-B(-P-B)m-S-A)n-T where A are independently selected rod-shaped, rigid molecular core units, S are independently selected flexible spacer units, B are polymerisable crosslinking groups independently selected, P are spacer groups independently selected, T are independently selected end groups, m are independently selected from values of from 1 to 4, n is equal to I to 3.

Abstract: The present invention relates to oxocarbon-, pseudooxocarbon- and radialene compounds as well as to their use as doping agent for doping an organic semiconductive matrix material, as blocker material, as charge injection layer, as electrode material as well as organic semiconductor, as well as electronic components and organic semiconductive materials using them.

Abstract: A composition filled with actinide powder, comprising an organic matrix and an actinide powder or a mixture of actinide powders, comprises at least: a plasticizer comprising an alkane whose longest radical chain comprises at least a few tens of carbon atoms and is in a volume content of between 20% and 70% of the total volume of the organic compounds alone; a binder comprising at least one aromatic polymer and/or polymethyl methacrylate and which is in a volume content of between 20% and 50% of the total volume of the organic compounds alone; a dispersant comprising a carboxylic acid or salts thereof, the volume content of which is less than 10% of the total volume of the organic compounds alone; said actinide powder or said mixture of actinide powders represent between 40% and 65% of the volume of the filled matrix.

Abstract: According to some embodiments, a winch apparatus comprises a winch housing and a winch drum rotationally mounted to the housing. The winch drum is configured to rotate around its central axis. The winch drum comprises a slotted keyhole for coupling a winch line to the winch drum. The slotted keyhole comprises an opening at a first end configured to receive the winch line positioned in the slotted keyhole and an opening at a second end configured to retain the winch line. A longitudinal axis of the slotted keyhole is offset from the direction the winch line pays onto the winch drum.

Abstract: A drawworks for a drilling device for lowering and hoisting a load such as a drill string or parts thereof includes a frame comprising a first bearing point, a second bearing point, and a third bearing point, a winding drum, and a first bearing device connected to the frame for the winding drum. The first bearing device is arranged so that a center of respective bearing forces is located at each of the first bearing point, at the second bearing point, and at the third bearing point.

Abstract: A bridge lifting support bracket is disclosed, which comprises a supporting mechanism, comprising a bracket having a depressed area at a face thereof and a lifting portion disposed at two sides of the bracket, respectively; and at least two jacks, disposed on a bottom face of the lifting portions, respectively. As such, a space for receiving a jack properly is secured by digging out a space of a concrete protection layer of a lower structure and using a supporting mechanism cooperating therewith when only a small space or a closely tight bonding with no seam existing between a bridge and a pier, whereby a lifting process of the bridge may be safely performed.

Abstract: Fittings can be configured to mechanically couple a rod to a post. In certain embodiments, rods and posts are joined to form railing systems. Fittings can include a first threaded end coupled to a second end. The second end can include a compliant member configured to provide an interference fit between the fitting and the rod.

Abstract: A non-volatile memory cell and a magnetic field-partitioned non-volatile memory for multi-bit storage are provided. The non-volatile memory cell for multi-bit storage includes a bottom electrode. A resistance-changing memory material covers the bottom electrode. A top electrode including a high-mobility material is disposed on the resistance-changing memory material. The top electrode has two post portions supporting a bar-shaped portion. At least two bits are stored in portions of the resistance-changing memory material connecting to the top electrode when an external magnetic field is applied along different directions.

Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.

Abstract: At least one example embodiment discloses a semiconductor device including a first wiring on a substrate. A second wiring is on the first wiring. A first cell is between the first wiring and the second wiring. The first cell has a first selector and a first resistive change device. A third wiring is on the second wiring. A second cell is between the second wiring and the third wiring. The second cell has a second selector and a second resistive change device. The second selector has a different thickness from the first selector.

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract: A photodetector 1A comprises an optical element 10, having a structure including first regions and second regions periodically arranged with respect to the first regions along a plane perpendicular to a predetermined direction, for generating an electric field component in the predetermined direction when light is incident thereon along the predetermined direction; and a semiconductor multilayer body 4 having a quantum cascade structure, arranged on the other side opposite from one side in the predetermined direction with respect to the optical element, for producing a current according to the electric field component in the predetermined direction generated by the optical element 10; while the quantum cascade structure includes an active region 4b for exciting an electron and an injector region 4c for transporting the electron, the active region 4b being formed on the outermost surface on the one side of the injector region 4c in the quantum cascade structure.

Abstract: An infrared solid-state imaging device with unit detecting sections in a matrix form, wherein the unit detecting section includes: an infrared light guiding layer; a first reflecting layer on the infrared light guiding layer; an infrared light detecting section on the first reflecting layer, the infrared light detecting section including an infrared light absorbing layer and upper and lower contact layers; and first metal wiring connected to the upper contact layer, wherein a side wall of the unit detecting section is inclined at an angle smaller than 45° to a normal direction, to form a groove between the adjacent unit detecting sections, a first insulating layer is provided on the side wall of the unit detecting section and second metal wiring is provided on the first insulating layer, and a refractive index of the first reflecting layer is lower than that of the lower contact layer.

Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.

Abstract: A quantum computing device magnetic memory is described. The quantum computing device magnetic memory is coupled with a quantum processor including at least one quantum device corresponding to at least one qubit. The quantum computing device magnetic memory includes magnetic storage cells coupled with the quantum device(s) and bit lines coupled to the magnetic storage cells. Each of the magnetic storage cells includes at least one magnetic junction. The magnetic junction(s) include a reference layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The magnetic junction(s) are configured to allow the free layer to be switched between stable magnetic states. The magnetic junction(s) are configured such that the free layer has a nonzero initial writing spin transfer torque in an absence of thermal fluctuations.

Abstract: An organic light-emitting display apparatus and a method for forming the same, the apparatus including a transparent protection layer on a substrate; a via insulation layer on the transparent protection layer; a pixel electrode on the via insulation layer; an opposite electrode on the pixel electrode; and an intermediate layer between the pixel electrode and the opposite electrode, the intermediate layer including an organic emission layer.

Abstract: Disclosed is an organic light emitting device including a first electrode, a second electrode, and an organic laminate formed between the first and second electrodes. The organic laminate includes, a multilayer-light emitting structure that includes two or more light emitting layers emitting light of different colors and a charge transport control layer formed at boundaries between the two or more light emitting layers and controlling the amount of charges transported between the two or more light emitting layer. A first light emitting layer of the two or more light emitting layers is between a hole transport layer and the charge transport control layer and formed of a mixture including a first dopant and a host of a hole transport material. Both a hole transport layer and the charge transport control layer are formed of the same material as the host of the first light emitting layer.

Abstract: Provided is an organic electroluminescent element which has improved driving voltage and improved current efficiency. An organic electroluminescent element having the above-mentioned improved characteristics is provided by using, as a material for organic electroluminescent elements, a polycyclic aromatic compound in which a nitrogen atom and another heteroatom or a metal atom (X) are adjacent to each other in a non-aromatic ring.

Abstract: A semiconductor device includes: a gate electrode layer; a gate insulating film provided on the gate electrode layer; a semiconductor layer provided, in opposition to the gate electrode layer, on the gate insulating film; and a source-drain electrode layer provided on the semiconductor layer and on the gate insulating film. A face, in opposition to the gate insulating film, of the semiconductor layer is located above a face of a section, located on the gate insulating film, of the source-drain electrode layer.

Abstract: The present specification discloses an organic electroluminescent device including an anode, a cathode, a light emitting layer provided between the cathode and the anode, a first p-type organic material layer provided between the cathode and the light emitting layer, and a first n-type organic material layer provided between the first p-type organic material layer and the light emitting layer.

Abstract: An optoelectronic component may include a carrier, a protective layer on or above the carrier, a first electrode on or above the protective layer, an organic functional layer structure on or above the first electrode, and a second electrode on or above the organic functional layer structure. The protective layer has a lower transmission than the carrier for electromagnetic radiation having a wavelength of less than approximately 400 nm at least in one wavelength range. The protective layer includes a glass.

Abstract: Various embodiments may relate to a process for producing a scattering layer for electromagnetic radiation. The process may include applying scattering centers onto a carrier, applying glass onto the scattering centers, and liquefying of the glass so that a part of the liquefied glass flows between the scattering centers toward the surface of the carrier, in such a way that a part of the liquefied glass still remains above the scattering centers.

Abstract: An organic light emitting device including a first electrode connected to a thin film transistor formed on a substrate, a second electrode opposite to the first electrode, and an organic laminate formed between the first electrode and the second electrode and including a hole transport layer, a multilayer-light emitting structure, and an electron transport layer. The multilayer-light emitting structure includes at least two light emitting layers emitting light of different colors through recombination of electrons and holes injected through the first and second electrodes, and a charge transport control layer formed of a bipolar material transporting both electrons and holes at boundaries between the at least two light emitting layers and controlling the amount of charges transported between the at least two light emitting layers.

Abstract: Provided is a display device, including: a plurality of pixels that are provided between a first substrate and a light-transparent second substrate, the plurality of pixels each including a light-reflective first electrode, an organic layer, and a light-transparent second electrode in order from the first substrate side, the organic layer including at least a light-emission layer; a first light-shielding layer that is provided in a region between the plurality of pixels on one side of the second substrate; and a second light-shielding layer that is provided between the first light-shielding layer and the first substrate, the second light-shielding layer facing at least part of the first light-shielding layer.

Abstract: Novel metal complexes containing azole fused pyridine ligands useful for providing more efficient and more stable phosphorescent emitter for OLED applications are disclosed.

Abstract: A non-volatile memory device includes a gate electrode, a data storage layer provided on the gate electrode, and a source electrode and a drain electrode provided on the data storage layer and spaced apart from each other. The data storage layer comprises three layers that form hetero-interfaces and have different permittivities from one another.

Abstract: An organic light-emitting display device according to one embodiment of the present disclosure includes a substrate, a thin-film transistor formed on the substrate, a planarization layer formed on the thin-film transistor, an organic light-emitting element formed on the planarization layer, the emitting element including an organic light-emitting layer and a cathode, and a lower auxiliary wiring between the organic light-emitting element and the planarization layer, the wiring electrically connected with the cathode.

Abstract: Provided are a display device and a method of manufacturing the same. A display device includes a coplanar thin-film transistor and a capacitor. The coplanar thin-film transistor comprises a gate electrode, an active layer including an oxide semiconductor, a source electrode and a drain electrode. The capacitor comprises a lower electrode, intermediate electrode and upper electrode. And the lower electrode is comprised of the same material as the active layer, and is conductivized. Also, the upper electrode is connected to the lower electrode. By using the conductivized lower electrode, the capacitor is configured to operate as multiple capacitors. Thus, the size of the capacitor is reduced, and sufficient capacitance may be secured with the capacitor with a smaller area. In this way, the area of each sub-pixel in the display device may be reduced, thereby achieving high resolution.

Abstract: An organic EL element manufacturing method includes coating ink which contains a functional layer forming material in a coating region which is configured by a pixel electrode and a partition wall which surrounds a periphery of the pixel electrode, where, in the coating ink, the ink is coated so as to satisfy the following expressions (1) to (3) in a case where a contact angle of the ink with respect to the side surface of the partition wall is set to ?bc and a contact angle with respect to a surface of the coating region where the ink is coated is set to ?lc.

Abstract: Provided are a resin composition and a substrate that are capable of being used for manufacturing an electronic device having excellent light extraction efficiency. The resin composition contains a crystalline polymer and a solvent dissolving the crystalline polymer. The resin composition is used to form a layer, and a haze value of the layer is 5% or more. Further, a method of manufacturing the electronic device by using such a substrate, and the electronic device are also provided.

Abstract: The present invention provides a touch panel, including a lower substrate, an organic light-emitting component, disposed on the lower substrate, a nano silver sensing layer, disposed on the organic light emitting component, and an upper substrate, disposed on the nano silver sensing layer.

Abstract: Compounds comprising a 3,9-linked oligocarbazole moiety and a dibenzothiophene, dibenzofuran, dibenzoselenophene, aza-dibenzothiophene, aza-dibenzofuran, or aza-dibenzoselenophene are provided. The 3,9-linked oligocarbazole and dibenzo or aza-dibenzo moiety are separated by an aromatic spacer. The compounds may be used as non-emissive materials for phosphorescent OLEDs to provide devise having improved performance.

Abstract: A light emitting device having a structure in which oxygen and moisture are prevented from reaching light emitting elements, and a method of manufacturing the same, are provided. Further, the light emitting elements are sealed by using a small number of process steps, without enclosing a drying agent. The present invention has a top surface emission structure. A substrate on which the light emitting elements are formed is bonded to a transparent sealing substrate. The structure is one in which a transparent second sealing material covers the entire surface of a pixel region when bonding the two substrates, and a first sealing material (having a higher viscosity than the second sealing material), which contains a gap material (filler, fine particles, or the like) for protecting a gap between the two substrates, surrounds the pixel region. The two substrates are sealed by the first sealing material and the second sealing material.

Abstract: A display device in which variations in luminance due to variations in characteristics of transistors are reduced, and image quality degradation due to variations in resistance values is prevented. The invention comprises a transistor whose channel portion is formed of an amorphous semiconductor or an organic semiconductor, a connecting wiring connected to a source electrode or a drain electrode of the transistor, a light emitting element having a laminated structure which includes a pixel electrode, an electro luminescent layer, and a counter electrode, an insulating layer surrounding an end portion of the pixel electrode, and an auxiliary wiring formed in the same layer as a gate electrode of the transistor, a connecting wiring, or the pixel electrode. Further, the connecting wiring is connected to the pixel electrode, and the auxiliary wiring is connected to the counter electrode via an opening portion provided in the insulating layer.

Abstract: A display substrate includes an active pattern, a gate electrode, a first insulation layer and a pixel electrode. The active pattern is disposed on a base substrate. The active pattern includes a metal oxide semiconductor. The gate electrode overlaps the active pattern. The first insulation layer covers the gate electrode and the active pattern, and a contact hole is defined in the first insulation layer. The pixel electrode is electrically connected to the active pattern via the contact hole penetrating the first insulation layer. A first angle defined by a bottom surface of the first insulation layer and a sidewall of the first insulation layer exposed by the contact hole is between about 30° and about 50°.

Abstract: The present invention provides an image sensor including an oxide semiconductor layer formed on a gate electrode, an oxide film formed on a surface of a channel region of the oxide semiconductor layer, source and drain electrodes formed on the oxide semiconductor layer and spaced apart from each other with the channel region interposed therebetween, an anti-etching film formed on the source and drain electrodes and configured to cover the oxide film, and a photodiode connected to the drain electrode.

Abstract: In a semiconductor device including an oxide semiconductor film, defects in the oxide semiconductor film are reduced. In addition, the electrical characteristics of a semiconductor device including an oxide semiconductor film are improved. Furthermore, the reliability of a semiconductor device including an oxide semiconductor film is improved. A semiconductor device including an oxide semiconductor layer and a pair of electrodes in contact with the oxide semiconductor layer and containing copper, aluminum, gold, or silver is provided.

Abstract: A disclosed display device includes a first oxide semiconductor layer and an oxide semiconductor connection wire both formed from an oxide semiconductor material layer over a substrate. The oxide semiconductor connection wire is integrally connected to the first oxide semiconductor layer and has a lower sheet resistance than the first oxide semiconductor layer. The display device also includes a first gate electrode either over the first oxide semiconductor layer or between the first oxide semiconductor layer and the substrate. The display device further includes a first gate insulation layer between the first oxide semiconductor layer and the first gate electrode.

Abstract: A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface.

Abstract: A semiconductor device can detect a defective or faulty part caused by copper (Cu) ions migrated from a through silicon via (TSV), resulting in improvement of device characteristics and reliability. The semiconductor device includes: a semiconductor substrate including an active region defined by a device isolation region; a through silicon via (TSV) formed to pass through the semiconductor substrate; and a test unit formed in the vicinity of the TSV so as to determine the presence or absence of metal pollution caused by the TSV.

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory devices having a resistance switching element, particularly resistive random access memory (RRAM) devices. In one aspect, a selector device includes a first barrier structure comprising a first metal and a first semiconductor or a first low bandgap dielectric material, and a second barrier structure comprising a second metal and a second semiconductor or a second low bandgap dielectric material. The selector device additionally includes an insulator interposed between the first semiconductor or the first low bandgap dielectric material and the second semiconductor or the second low bandgap dielectric material. The first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure.

Abstract: A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

Abstract: A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.

Abstract: A TFT array substrate having compensated gate signal delays is disclosed. The TFT array substrate includes a plurality of gate lines, a plurality of data lines insulatedly intersecting with the plurality of the gate lines, and a plurality of TFT switches, each of which is connected with one of the gate lines and one of the data lines. The TFT array substrate also includes a plurality of driving units, where the driving units are located at both ends of the gate lines, and each of the driving units is connected with at least one gate line to drive the TFT switches connected to the at least one gate line.

Abstract: A pixel structure is provided. The pixel structure includes a scan line, a data line, an active device, a covering layer, and a reflective pixel electrode. The active device is electrically connected with the scan line and the data line. The covering layer covers the scan line, the data line, and the active device. The reflective pixel electrode is disposed on the covering layer, and electrically connected with the active device. The reflective pixel electrode includes a first region having a plurality of first protruding structures and a second region having a planar surface. The area occupied by the first region is 50% to 70% of the total area of the reflective pixel electrode, and the area occupied by the second region is 30% to 50% of the total area of the reflective pixel electrode.

Abstract: A display device is configured that the common electrode wiring layer is divided in a source wiring layer direction, the metal wiring layer is disposed above the source wiring layer at a position in contact with the upper part of the common electrode wiring layer, and the metal wiring layer is not disposed at a position where the common electrode wiring layer is divided. Alternatively, the metal wiring layer is not disposed at a position between the same colors as those at the division position of the common electrode wiring layer.

Abstract: The tunneling channel of a field effect transistor comprising a plurality of tunneling elements contacting a channel substrate. Applying a source-drain voltage of greater than a turn-on voltage produces a source-drain current of greater than about 10 pA. Applying a source-drain voltage of less than a turn-on voltage produces a source-drain current of less than about 10 pA. The turn-on voltage at room temperature is between about 0.1V and about 40V.