Abstract: A segment of a two wire combined power and data network system for automation comprising a trunk, a spur mounted thereon and a fault protection device, in which said fault protection device comprises a control means adapted to monitor the current of said spur, and isolation means adapted to fully or partially isolate said spur from said trunk upon receipt of an activation signal from said control means, in which said control means comprises a failure status determination algorithm comprising an intermittent fault count over time step and a fault duration step, in which said intermittent fault count over time step is satisfied if a pre-determined number of separate faults are detected over a first pre-determined time period, in which said fault duration step is satisfied if a fault is detected which persists for longer than a second pre-determined time period, and in which said control means issues said activation signal upon determination of a failure status on said spur which satisfies the intermittent fault

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

Abstract: Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.

Abstract: A driving circuit includes a common well. The driving circuit further includes a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured to receive a first signal, and having a second terminal connected to the common well. The driving circuit further includes a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured to receive the first signal, wherein a second terminal of the second output buffer is disconnected from the common well.

Abstract: The application generally relates to apparatus for driving high voltage power switching devices such as IGBTs.

Abstract: The invention provides a motor driver including pre-drivers for a bridge circuit, delay circuits, and a delay setting register, wherein in order to suppress short-circuit current caused at the time of signal switching in the bridge circuit, the delay circuits are set based on delay time information in the delay setting register so as to control signals input into the pre-drivers. The signals input into the individual pre-drivers are delayed differently by the delay circuits based on the delay time information in the delay setting register, thereby preventing a short-circuit current flow caused by an offset in the timing of the individual pre-drivers being turned on and off.

Abstract: An integrated circuit (IC) having a pin having some dead-time when the pin is ineffective for use for a first purpose. The pin is used for a different purpose during that time wherein the pin is utilized to measure current when a main power transistor of a voltage converter is ON and used for driving an auxiliary or active-clamp when the main power transistor is OFF or used for generating a flag signal when the power transistor is OFF In addition, the integrated circuit (IC) could have a pin utilized for a first purpose to measure current during a first time when a power transistor of a voltage converter is ON and being utilized for a second purpose during the first time.

Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.

Abstract: A system includes a first phase-locked loop (PLL) circuit, a slew rate limiter and a second PLL. The first PLL is configured to receive an input signal, generate a first output identifying a frequency associated with the input signal, and generate a second output identifying phase information associated with the input signal. The slew rate limiter is configured to receive the first output from the first PLL, determine whether the frequency of the first output is changing at greater than a predetermined rate, and generate a first signal indicating whether the frequency is changing at greater than the predetermined rate. The second PLL is configured to receive the first signal from the slew rate limiter, receive the second output from the first PLL, and generate an output signal identifying an angle or phase information based on the first signal and the second output.

Abstract: An electronic device includes a clock configured to transmit a first clock signal and a second clock signal for operation of the electronic device; a duty cycle corrector coupled to the clock to correct a duty cycle of the first and second clock signals, the duty cycle corrector being configured to: assign and store a first duty cycle correction code in response to the first clock signal; assign and store a second duty cycle correction code in response to the second clock signal; calculate an offset code based on the first and second duty cycle correction codes; and negate the offset code from results of duty cycle correction operations.

Abstract: Disclosed herein is a semiconductor device that includes a first circuit comprising a plurality of first logic elements coupled in cascade and configured, in response to first and second clock signals and a control signal, to produce control information that indicates a first number of the first logic elements through which the control signal has been propagated during a period defined by a first change in logic level of the first clock signal and by a second change in logic level of the second clock signal, the first and second changes occurring adjacently to each other in same directions as each other, and a second circuit comprising a delay circuit configured to receive the first clock signal and the control information and to produce a third clock signal by delaying the first clock signal by an amount responsive to the control information.

Abstract: A duty correction circuit includes a duty ratio control unit suitable for generating an output clock by adjusting the duty ratio of an input clock, a code generation unit suitable for detecting a duty of the output clock and generating a first duty ratio control code based on the detection result, and a code filter unit suitable for providing the duty ratio control unit with a second duty ratio control code corresponding to a target value when a value of the first duty ratio control code is within a predetermined critical range adjacent to the target value.

Abstract: A semiconductor device includes a receiver configured to receive a reference voltage via a first input terminal, receive an input signal via a second input terminal, and generate an output signal by comparing the reference voltage to the input signal with each other. A termination circuit associated with the input signal terminal may be adjusted and a logic threshold voltage may be adjusted to accommodate the adjustment in the termination circuit.

Abstract: An integrated circuit and an operation method thereof are provided. The integrated circuit includes a voltage detecting unit, a central processing unit, a memory unit and a control unit. The voltage detecting unit detects a system voltage and correspondingly outputs a voltage state signal. The central processing unit has at least one register. When the system voltage is downed to a voltage level lower than or equal to a brown-out voltage and greater than a reset low voltage, the control unit stores values of the registers into the memory unit.

Abstract: An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a control register associated with each of the I/O terminals, a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal. The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory.

Abstract: Apparatuses and method for controlling delay circuits during an idle state to reduce degradation of an electrical characteristic is disclosed. An example apparatus includes a delay line circuit including a plurality of delay stages, and further includes a delay line control circuit coupled to the delay line circuit. The delay line control circuit is configured to enable delay stages of the plurality of delay stages, and is further configured to control enabled delay stages of the plurality of delay stages to provide a respective output clock signal having a high logic level during an idle state.

Abstract: An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.

Abstract: A circuit is described that includes a voltage follower device and a feed-forward device. In an implementation, the circuit includes a voltage follower device that includes an input and an output. The voltage follower device is configured to transfer a voltage signal at least substantially unchanged from the input to the output of the voltage follower device. The circuit also includes a feed-forward device that includes an input and an output. The input of the feed-forward device is connected to the input of the voltage follower device and the output of the feed-forward device is connected to the output of the voltage follower device. The feed-forward device is configured to output the voltage signal to the output of the voltage follower device.

Abstract: A level shifter applied in a driving circuit of a display is disclosed. The level shifter includes a first stage of level shifting unit and a second stage of level shifting unit and used to convert an input voltage signal with low voltage level into an output voltage signal with high voltage level. In one example, the total number of the transistors needed by the level shifter is much fewer than that of the prior art, and additional voltage sources are not needed to provide middle voltages. The manufacturing cost of the exemplary level shifter can be reduced and the signal level shifting efficiency of multi-power domain can be enhanced.

Abstract: A circuit is described that includes a switch, a switchable clamping element coupled to the switch, and a driver configured to control the switch based at least in part on a driver control signal. The driver is further configured to enable or disable the switchable clamping element. The switchable clamping element is configured to clamp a voltage across the switch when the switchable clamping element is enabled by the driver and when the voltage across the switch or a current at the switch satisfies a threshold for activating the switchable clamping element.

Abstract: A switch device for producing one or more electrical signals in response to mechanical force includes a body-part (101) and one or more electric transducers (102-105) connected to the body-part and arranged to produce the one or more electrical signals in response to mechanical force directed to the body-part. The body-part includes a cavity (106), and a wall constituting the bottom of the cavity is capable of being bent by mechanical force directed to the wall from the opposite side with respect to the cavity. The one or more electric transducers are located in the cavity and arranged to produce the one or more electrical signals when the bottom of the cavity is bent. The switch device can be built, for example, into a working plane of an electrical instrument so that a plate constituting the working plane constitutes also the body-part of the switch device.

Abstract: Manufacturing a DC-DC converter on a chip includes: providing a die having a p-type top side and an n-type bottom side; removing an interior portion, creating a hole; flipping the interior portion; inserting the interior portion into the hole; fabricating high-side switch cells in the interior portion's top side and low-side switch cells in the exterior portion's top side; sputtering a magnetic material on the entire top side; burrowing tunnels into the magnetic material; and applying conductive material on the magnetic material and within the tunnels, electrically coupling pairs of high-side and low-side switches, with each pair forming a micro-power-switching phase, where the conductive material forms an output node of the phase, and the conductive material in the burrowed tunnels forms, in each phase, a torodial inductor with a single loop coil and, for the plurality of phases, a directly coupled inductor.

Abstract: A differential circuit system is provided. The differential circuit system includes: a different circuit set including a plurality of differential circuits, a voltage regulator, and a current drainage circuit set. The differential circuits are electrically connected between a first node and a second node, and each differential circuit generates a current flowing from the first node to the second node. A high voltage is provided to the first node and a low voltage is provided to the second node. The first node receives an external voltage. According to the first voltage, the voltage regulator generates the low voltage. The low voltage is provided to the second node. The current drainage circuit set generates a drainage current in between the second node and a ground voltage. A superposed current flowing to the voltage regulator is difference of the summation of currents minus the conducting current.

Abstract: A gate control circuit for controlling gates of at least a half side of an H-bridge circuit includes: an input terminal configured to connect to a PWM signal; a power terminal configured to connect to a voltage source that supplies a positive voltage; a ground terminal configured to connect to a ground reference; and a control circuit connected with the input terminal, the power terminal, and the ground terminal. The control circuit includes: two high side switches configured to be connected with the voltage source respectively through the power terminal; two low side switches configured to be connected with the ground reference respectively through the ground terminal; a first inverter connecting the two high side switches; a second inverter connecting the two low side switches; and a first resistor and a second resistor connecting the two high side switches to the two low side switches respectively.

Abstract: A distortion compensation apparatus includes a pre-distorter, a gain control unit, and a learning unit. The pre-distorter adds distortion according to compensation coefficients to individual input signals prior to the input signals being input to a power amplifier. The gain control unit applies gain control to individual feedback signals fed back from the power amplifier according to a maximum level of the feedback signals within a time frame. The learning unit updates the compensation coefficients used by the pre-distorter, using the feedback signals subjected to the gain control by the gain control unit.

Abstract: An amplifier includes two input terminals to receive a differential, two-tone transmission signal; two output terminals; a coil having terminals connected with the input terminals respectively, and a center tap; a first transistor having the gate connected with one terminal of the coil, and the output terminal connected with one output terminal; a second transistor having the gate connected with the other terminal of the coil, end the output terminal connected with the other output terminal; a diode having a terminal connected with the center tap; and a bias circuit connected with the other terminal of the diode to output a gate voltage to turn on the first and second transistors. The diode adjusts the terminal voltage depending on a signal level of a double harmonic wave of the transmission signal supplied to the terminal of the diode from the center tap.

Abstract: An arrangement and a method for improving the efficiency of a multistage switching amplifier using a resonant circuit element is presented. The multistage amplifier comprises a pre-diver amplifier, a final stage amplifier and a series L-C arrangement coupled between the pre-driver amplifier and the final stage amplifier. The series L-C arrangement forms a parallel L-C resonant circuit with a gate to source capacitor of an input transistor of the final stage amplifier. An oscillation of energy takes place between the gate to source capacitor of the input transistor of the final stage amplifier and the series L-C arrangement. This oscillation of energy provides the final stage amplifier with driving current and improves efficiency of the overall multistage amplifier arrangement.

Abstract: A CMOS transmission gate that is compensated for lost current to parasitic capacitance. Parasitic capacitance current is detected by an amplifier and fed back in-phase to the input of the CMOS transmission gate with the gain of the amplifier set to avoid circuit instability. In a first example a transconductance amplifier detects a voltage drop across a resistor in and RC network and the resulting current applied to the input of the transmission gate. A second example uses a current amplifier to detect gate current of the N-channel and P-channel transistors of the transmission gate, and an output current is fed back in phase to the input of the CMOS transmission gate.

Abstract: An amplifier circuit has: a main amplifier connected between an input terminal and an output terminal, the main amplifier amplifying an input signal input to the input terminal and outputting an amplified signal to the output terminal; a compensation circuit comprising a variable delay circuit and a variable gain inverting circuit, the variable delay circuit receiving the input signal and outputting a delay signal with a delay time from the input signal, the variable gain inverting amplifier inverting and amplifying the delay signal with a gain and outputting a compensation signal to the output terminal; and a controller configured to control the gain of the pre-emphasis circuit and the delay time of the variable delay circuit to compensate a response of the main amplifier in a first frequency band lower than a base frequency of a target signal of compensation and in a low frequency band higher than zero Hertz.

Abstract: A device includes an amplifier having a first path and a second path and a first variable attenuator connected to the first path. The device includes a controller coupled to the first variable attenuator. The controller is configured to determine a magnitude of an input signal to the amplifier. When the magnitude of the input signal is below a threshold, the controller is configured to set an attenuation of the first variable attenuator to a first attenuation value. When the magnitude of the input signal is above the threshold, the controller is configured to set the attenuation of the first variable attenuator to a second attenuation value. The second attenuation value is less than the first attenuation value.

Abstract: Methods and systems for reducing parasitic loading on a power supply output in RF amplifier arrangements used in multiband and/or multitude RF circuits are presented. Such RF circuits can comprise a plurality of RF amplifiers of which only one is activated for a given desired transmission mode and/or band.

Abstract: Methods and apparatus, including computer program products, are provided for hybrid DC-DC converters. In one aspect, there is provided a method. The method may include tracking, by an envelope detector, an envelope of a signal being amplified by an amplifier. The method may further include supplying, by a first direct-current to direct-current converter, power to the amplifier, the power supplied by the first direct-current to direct-current converter including one or more high-frequency components of the envelope tracked by the envelope detector. The method may further include supplying, by a second direct-current to direct-current converter, power to the amplifier, the power supplied by the second direct-current to direct-current converter including one or more low-frequency components of the envelope tracked by the envelope detector. Related systems, apparatuses, and computer program products are also disclosed.

Abstract: A method for setting adjusting frequency of an electric oscillating circuit of a corona ignition device. The circuit is excited with a starting value (f1) of the excitation frequency and a reference value (IR) of a frequency-dependent variable is measured. The excitation frequency is incrementally changed. After every increment a value (I) of the frequency-dependent variable is measured and it is determined whether the measured value (I) deviates significantly from the reference value (IR). Depending upon the measured value (I) relative to the reference value, the value (f) of the excitation frequency is either set as the new starting value (f1) or stored as a boundary value. Further incremental changes to the excitation frequency are made in one of two directions and further comparisons of the values I and IR are performed. Ultimately, the excitation frequency can be set to a mean value between first and second boundary values.

Abstract: A clock generation system provides a low power approach for generating clock signals. The clock generation system may use a free running clock and, at intervals, maintain the accuracy of the free running clock. The free running clock may be the source of other system clocks, such as a 32 KHz clock for system timing and a 13 MHz clock to facilitate audio playback, e.g., MP3 decoding and playback. The clock generation system eliminates the need for two different crystal oscillators and a complex PLL for generating the low frequency clock.

Abstract: Clock synchronization error is corrected or minimized by fitting a parabolic f(T) function to the crystal's data, and compensating for sampling period drift in an Analog to Digital Converter (ADC) at various temperatures.

Abstract: A ring oscillator comprising three or more delay cells, each of which comprises a plurality of differential input leads and a differential output lead, wherein each of the plurality of differential input leads comprises one or more inverters, wherein the three or more delay cells are inter-connected forming a plurality of loop paths, wherein each loop path connects the differential output lead of each delay cell to a corresponding differential input lead of another delay cell, wherein each loop path provides an inverter strength determined by a number of inverters in a corresponding differential input lead of each delay cell, wherein the plurality of loop paths are configured to generate an oscillating signal with an operating frequency, and wherein the operating frequency is tunable by digitally adjusting one or more inverter strengths in one or more of the plurality of loop paths.

Abstract: A method includes generation of a first current proportional to absolute temperature and formation of a second current representative of the temperature variation of the threshold voltages of the transistors of the inverter and limited to a fraction of the first current. This fraction is less than one. The inverter is supplied with a supply current equal to the first current minus the limited second current.

Abstract: A crystal oscillator is configured by accommodating a crystal blank that functions as a crystal unit and an IC chip that includes at least an oscillator circuit using the crystal blank into a container in an integrated manner. In the IC chip, the oscillator circuit is connected to the crystal unit via a pair of crystal connecting terminals, an output from the oscillator circuit is supplied to a plurality of output buffers. In relation to the crystal connecting terminal having a phase opposite to that of an output from the on/off controllable output buffer, an output terminal of this output buffer is disposed farther than an output terminal of the output buffer that is not subjected to the on/off control.

Abstract: A MEMS vibrator includes: a base portion; a plurality of vibration reeds which extends from the base portion; a supporting portion which extends from a vibration node portion of the base portion; a fixing portion which is connected with the supporting portion; and a substrate in which the fixing portion is disposed on a main surface. The plurality of vibration reeds is separated from the substrate.

Abstract: Embodiments are directed to a transition structure for interfacing an integrated circuit chip and a substrate, comprising: a co-planar waveguide (CPW) structure formed based on ground-signal-ground (GSG) pads on the integrated circuit chip, a grounded co-planar waveguide (CPWG) structure coupled to the GSG pads, and a microstrip coupled to the CPWG structure.

Abstract: Embodiments are directed to a structure comprising: a first substrate section having a first thickness, a second substrate section having a second thickness different from the first thickness, a plurality of vias configured to couple a first ground plane associated with the first substrate section and a second ground plane associated with the second substrate section, and a microstrip comprising: a first section associated with the first substrate section and having a first width, a second section associated with the second substrate section and having a second width different from the first width, and a taper between the first width and the second width.

Abstract: A piezoelectric multiplexer includes an actuator and multiple piezo-morph beams. The actuator includes an actuator conducting head and an actuator stem, and each piezo-morph beam includes a conducting beam contact head and a beam stem manufactured out of piezo-morph material. A control voltage is selectively applied to electrical contacts coupled to the beam stems to create a piezoelectric effect that bends the selected piezo-morph beam and creates an electrical connection between its contact head and the conducting head of the actuator. A control circuit with a controller signals which piezo-morph beam to connect to the actuator. This multi-piezo-morph-beam piezoelectric multiplexer can be affixed to the electrical terminals of different electrical components (e.g., a transistor) to create an electrical cell that can be manufactured on a semiconductor chip or in a microelectromechanical system (MEMS) device.

Abstract: A method for generating a variable delay in an electromagnetic signal that crosses a main transmission line includes: coupling to the main transmission line a secondary transmission line terminated at both ends by respective variable-reactance circuit elements, wherein the main transmission line and the secondary transmission line are immersed in the same dielectric medium at a distance from each other; simultaneously varying a reactance value of the variable-reactance circuit elements; selecting the reactance value by varying physical and electrical parameters of the main transmission line and of the secondary transmission line, so as to obtain, on the main transmission line, an absorption peak at an absorption frequency higher than a predetermined working frequency of the main transmission line, and an adaptation peak at a frequency lower than the transmission frequency, the adaptation peak corresponding to the predetermined working frequency.

Abstract: In one example embodiment, a programmable filter is provided, including a plurality of variable-inductance networks and a plurality of variable-capacitance networks. The programmable filter may be implemented in a classical filter topology, with variable-capacitance networks replacing discrete capacitors and variable-inductance networks replacing discrete inductors. An example variable-inductance network comprises a primary inductor with an intermediate tap, and secondary inductor connected at the intermediate tap, with switches for selecting an inductance.

Abstract: An acoustic filter includes a signal input port, a ladder-type filter, a first branch ladder-type filter, a second branch ladder-type filter, and a signal output port. The first branch ladder-type filter and the second branch ladder-type filter are connected in parallel to each other. The signal input port is connected to the ladder-type filter. The ladder-type filter circuit is connected in series to the first branch ladder-type filter and the second branch ladder-type filter. The first branch ladder-type filter circuit and the second branch ladder-type filter are connected to the signal output port.

Abstract: The disclosure relates to a harmonic oscillator and a preparation method thereof, a filtering device and an electromagnetic wave device. The harmonic oscillator includes at least one dielectric slab and response units attached on one surface of the at least one dielectric slab, where the response units are structures manufactured by conductive material and provided with geometric patterns. According to the technical solution of the disclosure, the filtering device and the electromagnetic wave device with the harmonic oscillator are good in structure stability. Swinging of a harmonic oscillator sheet layer is low in loss. The Q value of the harmonic oscillator prepared by the disclosure is high; and loss of a resonant cavity, the filtering device and a microwave device with the harmonic oscillator is obviously reduced.

Abstract: A semiconductor transmission line substructure and methods of transmitting RF signals are described. The semiconductor transmission line substructure can include a substrate; a first signal line over the substrate; a first ground line over the substrate; and a second semiconductor substrate over the substrate. The first signal line, the first ground line and the second semiconductor substrate are each vertically spaced apart from one another and can be separated from one another by at least one electrically insulating layer.

Abstract: A switch assembly includes a circuit board mounted in the housing of an electric tool and carrying multiple magnetic sensor components, a first button having hooks slidably coupled to the circuit board and a press portion exposed to the outside of the housing for pressing by a user and a first magnetic member mounted at the press portion and movable with the first button relative to the housing to induce and change the magnetic flux of one magnetic sensor component, and a second button mounted in the housing and movable back and forth relative to the housing and carrying a second magnetic member that is movable with the second button to induce and change the magnetic flux of the other magnetic sensor component.

Abstract: Provided is a combined type RFeB-based magnet, including: two or more unit magnets; and an interface material that bonds bonding surfaces of the unit magnets adjacent to each other, in which each of the unit magnets is an RFeB-based magnet containing a light rare earth element RL that is at least one element selected from the group consisting of Nd and Pr, Fe, and B, in which the interface material contains at least one compound selected from the group consisting of a carbide, a hydroxide, and an oxide of the light rare earth element RL, and in which the combined type RFeB-based magnet contains at least one element selected from the group consisting of Dy, Ho and Tb, and has a nonplanar surface.

Abstract: Provided is a combined type RFeB-based magnet, including: a first unit magnet; a second unit magnet; and an interface material that bonds the first unit magnet and the second unit magnet, in which the first unit magnet and the second unit magnet are RFeB-based magnets containing a light rare earth element RL that is at least one element selected from the group consisting of Nd and Pr, Fe, and B, in which the interface material contains at least one compound selected from the group consisting of a carbide, a hydroxide, and an oxide of the light rare earth element RL, and in which an amount of a heavy rare earth element RH that is at least one element selected from the group consisting of Dy, Tb and Ho in the second unit magnet is more than that in the first unit magnet.