Abstract: A job profile is received that includes characteristics of a job to be executed, where the characteristics of the job profile relate to map tasks and reduce tasks of the job. The map tasks produce intermediate results based on input data, and the reduce tasks produce an output based on the intermediate results. The characteristics of the job profile include at least one particular characteristic that varies according to a size of data to be processed. The at least one particular characteristic of the job profile is set based on the size of the data to be processed.

Abstract: A method and apparatus are described for performing sprinting in a processor. An analyzer in the processor may monitor thermal capacity remaining in the processor while not sprinting. When the remaining thermal capacity is sufficient to support sprinting, the analyzer may perform sprinting of a new workload when a benefit derived by sprinting the new workload exceeds a threshold and does not cause the remaining thermal capacity in the processor to be exhausted. The analyzer may perform sprinting of the new workload in accordance with sprinting parameters determined for the new workload. The analyzer may continue to monitor the remaining thermal capacity while not sprinting when the benefit derived by sprinting the new workload does not exceed the threshold.

Abstract: Computer-implemented systems and methods regulate access to a plurality of resources in a pool of resources without requiring individual locks associated with each resource. Access to one of the plurality of resources is requested, where a resource queue for managing threads waiting to access a resource is associated with each of the plurality of resources. A resource queue lock associated with the resource is acquired, where a resource queue lock is associated with multiple resources.

Abstract: A Java applet program loaded initially from a remote server is configured to receive additional user annotations for data displayed in an already opened applet window located at the user's client system. The user is permitted to preserve/capture, the modified applet window containing any such input or modifications to the applet window data. The updated applet window data cannot be written to the user's client system, instead, the modified window data is converted to a standard compressed graphics file format and then uploaded to the remote server. From there the applet can then open another applet window within a browser program pointing to the location of such file on the remote server. At that point, the user can then perform any desired operation on the file since the browser has access to the local system resources.

Abstract: A storage system and method for identifying a faulty link the storage system is disclosed. The storage system includes a plurality of target devices and at least one expander configured to communicatively couple a plurality of initiators to the plurality of target devices. Each initiator of the plurality of initiators monitors occurrences of link disruptions independently, wherein upon detecting occurrences of a predetermined number of link disruptions within a predetermined time period, a reporting initiator reports a detection of a faulty link in the multi-initiator topology and requests an arbitrator to identify at least one peer initiator in the multi-initiator topology that shares at least one shared link with the reporting initiator. This reporting initiator and its peer initiators then jointly execute a common diagnostic process to identify the faulty link in the multi-initiator topology.

Abstract: Methods, systems, and computer program products for intelligent monitoring services are provided. A method includes sampling data over a defined time period and calculating a normative value for the defined time period based on the sampled data. The method also includes monitoring incoming data, comparing a monitored value for the incoming data to the normative value, and generating a responsive action when the monitored value deviates from the normative value.

Abstract: Techniques are provided for monitoring and diagnosis of a network comprising one or more devices. In some embodiments, techniques are provided for gathering network information, analyzing the gathered information to identify correlations, and for diagnosing a problem based upon the correlations. The diagnosis may identify a root cause of the problem. In certain embodiments, a computing device may be configurable to determine a first event from information, allocate a first event to a first cluster, the first cluster is from one or more clusters of events, based on a set of attributes for the first event, and determine a set of attributes for the first cluster, and rank the first cluster against the other clusters from the one or more clusters of events based on the set of attributes for the first cluster. The set of attributes may be indicative of the relationship between events in the cluster.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: Semiconductor memory device and method of operating same includes reading data stored in memory cells of a page; performing an error correction loop (ECC loop) including performing an error checking and correcting operation (ECC) on the read data; determining a number of bit errors in the read data; and when the number of bit errors is greater than a maximum number of correctable bits, incrementing the number of ECC iterations (ECC count) and increasing the maximum number of correctable bits; storing the ECC count until the number of bit errors is less than the maximum number of correctable bits; and programming corrected data to the memory cells when the stored ECC count is more than preset number.

Abstract: A low density parity check (LDPC) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The LDPC decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells. The first-type cells may be a first one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO. The second-type cells may be a second one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO.

Abstract: An adaptive logical storage element comprises a plurality of solid-state storage elements accessible in parallel. The logical storage element includes logical storage units, which may include logical page, logical storage divisions (erase blocks), and so on. Each logical storage unit comprises a plurality of physical storage units. A logical storage unit may include one or more physical storage units that are out-of-service (OOS). The OOS status of logical storage units is tracked by OOS metadata. When data is stored on the logical storage element, padding data is provided to physical storage units that are OOS, and valid and/or parity data is provided to in-service physical storage units. A write data pipeline accesses the OOS metadata to insert padding data, and a read data pipeline accesses the OOS metadata to strip padding data.

Abstract: Receive a request to write a unit of data, having a first half of bits and a second half of bits, to an index of a ternary content addressable memory (TCAM). Generate a first error-correcting code (ECC) codeword for first bits of the first half of bits of the unit of data and first bits of the second half of bits of the unit of data. Generate a second error-correcting code (ECC) codeword for second bits of the first half of bits of the unit of data and second bits of the second half of bits of the unit of data. Store the first half of bits of the unit of data in the first row of the index. Store the second half of bits of the unit of data in the second row of the index.

Abstract: Receive a request to write a unit of data, having a first half of bits and a second half of bits, to an index of a ternary content addressable memory (TCAM). Generate a first error-correcting code (ECC) codeword for first bits of the first half of bits of the unit of data and first bits of the second half of bits of the unit of data. Generate a second error-correcting code (ECC) codeword for second bits of the first half of bits of the unit of data and second bits of the second half of bits of the unit of data. Store the first half of bits of the unit of data in the first row of the index. Store the second half of bits of the unit of data in the second row of the index.

Abstract: A memory storage device, a memory controller thereof, and a method for programming data thereof are provided. The memory storage device having an error checking and correcting (ECC) circuit and a rewritable non-volatile memory chip is coupled to a host system. The method includes determining whether write data to be written into the rewritable non-volatile memory chip belongs to a specific type. The method also includes generating at least one first type ECC code with a first length by the ECC circuit according to the write data if the write data belongs to the specific type. The method further includes generating at least one second type ECC code with a second length by the ECC circuit according to the write data if the write data does not belong to the specific type. In which, the first length is longer than the second length.

Abstract: A nonvolatile memory device includes a nonvolatile memory, a buffer memory configured to store a plurality of read data transmitted from the nonvolatile memory, an error detection and correction circuit configured to detect an error in partial data of each of the plurality of read data and judging whether the partial data is correctable or not on the basis of the detected error, and a controller configured to analyze the uncorrectable partial data with respect to the plurality of read data to determine a representative value, and to transmit the representative value to the error detection and correction circuit. The plurality of read data is read through a read operation with respect to a same page.

Abstract: An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters.

Abstract: An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract: Approaches are presented for adaptively re-compacting data when errors are found during a post-write verify in a non-volatile memory system, such as flash NAND memory. In one example, user data along with corresponding parity data is written into a block of non-volatile memory. After writing in the user data, but prior to writing the corresponding parity data, the user data is checked. For any word lines that fail this post-write verify, the parity data for the block is adjusted to remove the contribution of any failed word lines before this modified parity data is written into the block. The data corresponding to the failed word lines can then be written elsewhere in the memory system.

Abstract: An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states.

Abstract: In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.

Abstract: A semiconductor memory controlling device includes a write control unit that writes a predetermined number of pieces of first data and redundant information calculated by using the predetermined number of pieces of the first data and used for correcting an error in the first data into different semiconductor storage drives, respectively; a constructing unit that constructs a storage area for storing therein a table by using driver information, the table showing an association between a logical address and a physical address of the first data and identification information for associating the predetermined number of pieces of first data with the redundant information; and a table controlling unit that stores, into the storage area, the table associated with the identification information, the physical address and the logical address of the predetermined number of pieces of the first data, and a physical address of the redundant information.

Abstract: Disclosed in some examples is a method of media repair in an IMS based network, the method includes communicating with an IMS network using SIP to setup a download session with a BMSC over a MBMS bearer; responsive to determining that one or more received encoding symbols of media downloaded using the established MBMS bearer cannot be decoded: requesting a file repair procedure from the IMS network component using a SIP re-invite request, the SIP re-invite request including an address of an HTTP repair server indicated by the IMS network component during the MBMS bearer setup; responsive to receiving a SIP acknowledgement indicating that the request was successful, requesting an HTTP connection with the HTTP server to re-download the one or more encoding symbols of the media that could not be decoded; and receiving the one or more encoding symbols from the HTTP server.

Abstract: An image rescue system includes an application program for communication with a mass storage device, the application program being in communication with an operating system layer for accessing the mass storage device to read and write information. The image rescue system further includes a device driver in communication with the application program, the operating system layer and the mass storage device, the device driver for allowing the application program to access the mass storage device to read and write information by bypassing the operating system layer, the device driver for communicating with the mass storage device to allow the application program to access information in the mass storage device considered damaged by the operating system layer, the damaged information being inaccessible to the operating system layer, wherein the image rescue system accesses the mass storage device to retrieve and recover information accessible and inaccessible to the operating system layer.

Abstract: Systems, methods, and media for synthesizing a view of a file system are provided herein. Methods may include receiving a request to obtain a view of at least a portion of a file system backup for a device, responsive to the request, mounting one or more backup files for the device on a backup node, generating a view of the at least a portion of a file system created from the one or more mounted backup files, the view being accessible via the intermediary node that is communicatively coupled with the backup node.

Abstract: A computer system includes a simultaneous multi-threading processor and memory in operable communication with the processor. The processor is configured to perform a method including running multiple threads simultaneously, detecting a hardware error in one or more hardware structures of the processing circuit, and identifying one or more victim threads of the multiple threads. The processor is further configured to identify a plurality of hardware structures associated with execution of the one or more victim threads, isolate the one or more victim threads from the rest of the multiple threads by preventing access to the plurality of hardware structures by the multiple threads, flush the one or more victim threads by resetting hardware states of the plurality of hardware structures, and restore the one or more victim threads by restoring the plurality of hardware structures to a known safe state.

Abstract: A system is described that includes a network interface attached to a persistent memory unit. The persistent memory unit is configured to receive checkpoint data from a primary process, and to provide access to the checkpoint data for use in a backup process, which provides recovery capability in the event of a failure of the primary process. The network interface is configured to provide address translation information between virtual and physical addresses in the persistent memory unit. In other embodiments, the persistent memory unit is capable of storing multiple updates to the checkpoint state. The checkpoint state and the updates to the checkpoint state, if any, can be retrieved by the backup process periodically, or all at once upon failure of the primary process.

Abstract: An array can include a controller and multiple storage devices of a first type. When a storage device of the first type is replaced by a replacement storage device of a second type, and other storage devices of the first type remain in the array, the controller instructs the replacement storage device to configure itself as a storage device of the first type. When the last storage device of the first type in the array is replaced by a replacement storage device of the second type, the controller instructs all the storage devices of the array to configure themselves as storage devices of the second type.

Abstract: A storage system including a first boot drive configured to store an operating system, one or more data drives configured to store user data, the one or more data drives distinct from the first boot drive, and a controller configured to detect when a second boot drive is added to the storage system, and automatically configure the first boot drive and the second boot drive in a redundant array of independent disks (“RAID”) configuration when the controller detects that the second boot drive is added to the storage system.

Abstract: In a system and method for a storage area network (SAN), a first controller receives a write request for a SAN and communicates with a first nested storage array module (NSAM), the first NSAM manages storage of data onto a shelf and presents the shelf as a logical unit, a buffer stores a portion of a write request from the first controller and aggregates data from the write request for the shelf, from a shelf with a second NSAM, the second NSAM provides a portion of data from the buffer to a third NSAM, the third NSAM manages storage of the portion of data from the buffer to a physical storage unit, and a second controller coupled to the first controller handles requests for the SAN in response to a failure of the first controller.

Abstract: A system and method are provided for test program generation using key enumeration and string replacement. A system includes a test program generator and a tester. The tester receives a test program from the test program generator and tests one or more products according to the test program. The test program generator receives a seed file from a seed file database and a configuration file from a configuration file database. The test program generator iterates over enumeration keys in the configuration file and, for each key, apply to the seed file one or more rules in the configuration file keyed to the enumeration key. Applying a rule includes replacing in the seed file one or more occurrences of a predicate value of the rule with a transformation value of the rule. The test program generator also outputs to the tester the modified first seed file as the test program.

Abstract: To test a software application, a method submits an electronic board including a component implementing an application to a laser radiation generated in test equipment. The component is excited with laser pulses having very short durations distributed during complex operational phases of the component for running the application, and the reaction of the component and the application are observed.

Abstract: An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.

Abstract: A segmented subsystem, for use within an automated test platform, includes a first subsystem segment configured to execute one or more instructions within the first subsystem segment. A second subsystem segment is configured to execute one or more instructions within the second subsystem segment. The first subsystem segment includes: a first functionality, a second functionality, and a status polling engine. The status polling engine is configured to: determine a first status for the first functionality and a second status for the second functionality, and generate a consolidated status indicator for the first subsystem segment based, at least in part, upon the first status for the first functionality and the second status for the second functionality.

Abstract: In an error response circuit an analysis circuit unit analyzes a command transmitted from a first circuit section to a second circuit section, and detects a status of data transfer between the first circuit section and the second circuit section. A response circuit unit generates an error signal in accordance with the detected status of the data transfer in response to the second circuit section changing from a first power consumption state to a second power consumption state in which power consumption is lower than power consumption in the first power consumption state. A switching circuit unit transmits the error signal to the first circuit section in place of a response signal that is responsive to the command and transmitted from the second circuit section to the first circuit section.

Abstract: The present disclosure provides storage management systems and methods. A hierarchical configuration information process includes accessing information regarding hierarchical relationships of components associated with a storage environment. A storage resource consumption detection process includes detecting consumption of storage resources included in the storage environment. A coordinated consumption analysis process is coordinated across multiple levels of an active spindle hierarchy. A reaction process includes performing an automated consumption notification process and an automated reclamation process based upon results of the storage resource consumption detection process.

Abstract: Algorithm selection for collective operations in a parallel computer that includes a plurality of compute nodes may include: profiling a plurality of algorithms for each of a set of collective operations, including for each collective operation: executing the operation a plurality times with each execution varying one or more of: geometry, message size, data type, and algorithm to effect the collective operation, thereby generating performance metrics for each execution; storing the performance metrics in a performance profile; at load time of a parallel application including a plurality of parallel processes configured in a particular geometry, filtering the performance profile in dependence upon the particular geometry; during run-time of the parallel application, selecting, for at least one collective operation, an algorithm to effect the operation in dependence upon characteristics of the parallel application and the performance profile; and executing the operation using the selected algorithm.

Abstract: Certain example embodiments relate to a method of monitoring a message object sent from a client to invoke an operation on a server in a distributed computing environment. Upon receipt of the message object at a measurement point, measurement data is produced. The measurement data is inserted into the message object.

Abstract: Methods, systems, and computer program products for administering event pools for relevant event analysis are provided. Embodiments include assigning, by an incident analyzer, a plurality of events to an events pool; determining, by the incident analyzer, an event suppression duration; determining, by the incident analyzer in dependence upon event analysis rules, to suppress events having particular attributes indicating the events occurred during the event suppression duration; and suppressing, by the incident analyzer, each event assigned to the events pool having the particular attributes indicating the events occurred during the event suppression duration.

Abstract: A method of receiving a stack trace, where the stack trace refers to executed code that crashed; identifying one or more lines of the executed code that caused the executed code to crash; identifying, from a code repository, contact information of a developer from a plurality of developers that are responsible for the executed code, where the developer is responsible for a code commit that refers to the one or more lines of the executed code; and notifying, through the contact information, the developer that the one or more lines caused the executed code to crash.

Abstract: A technique that supports improved debugging of kernel loadable modules (KLMs) that involves allocating a first portion of a memory and detecting a first kernel loadable module (KLM) requesting an allocation of at least a portion of the memory. The first KLM is then loaded into the first portion of the memory and a first identifier is associated with the first KLM and the first portion. The access of a second portion of the memory by the first KLM, the second portion being distinct from the first portion is detected and an indication that the first KLM has accessed the second portion is generated.

Abstract: A development environment provides warnings based on one or more application categories set for an application. Each warning has a trigger threshold and a warning action. Different application categories have different warnings. The development environment proactively tests for trigger conditions and provides triggered warnings within a workflow that includes application designing, code editing, building, and running. For instance, a Social Networking application whose start-up time is greater than desired for Social Networking applications will trigger a warning. Password Manager or Finance applications that should use a more secure approach to store user data will trigger a warning not given to applications in other categories. A News application may trigger a warning from the development environment that application content is not easily readable if a user switches to a light color theme on a device. The application category is selected by the developer or set proactively by the development environment.

Abstract: The disclosed embodiments provide a system that performs automated user-interface layout testing. During operation, the system executes a pre-defined set of operations for a program. After these operations have executed, the system then stores a representation (e.g., a snapshot) of the program user interface. The system then compares this representation against a validated representation that was previously stored for the pre-defined set of operations to determine a difference between the representations. This process facilitates detecting changes to the program (and/or the environment in which the program executes) that affect the user interface that is presented to a user.

Abstract: A data capture system includes a processor instructed by configuration data that indicates a trigger event and data identifiers, a volatile memory that stores data based upon the data identifiers, and a non-volatile memory that stores contents of the volatile memory based upon detection of the trigger event by the processor. The data identifiers indicate data elements to be stored.

Abstract: A main memory (10) comprises a plurality of physical blocks of memory locations. The main memory (10) supports erasing of at least a physical block at a time. Pointer information is stored in a subset (40, 42) of the blocks for use to identify respective ones of the physical blocks that are assigned to respective functions. Successive versions of the pointing information are stored at mutually different memory locations initially in a first block (40) in the subset (40, 42). A subsequent version of the pointing information that is more recent than the successive versions is stored in a second block (42) of the subset (40, 42) at least after the first block (40) has been filled. The first block (40) is erased after storing the subsequent version. On start up of the main memory the pointing information is recovered by testing which of the blocks of the subset (40, 42) contains a most recent version of the pointing information.

Abstract: A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates through a variety of mechanisms, including determinations that the data is not likely to be read back from the storage device within a time period that justifies its storage in the cache, compressing data prior to its storage in the cache, precluding storage of sequentially-accessed data in the cache, and/or throttling storage of data to the cache within predetermined write periods and/or according to user instruction.

Abstract: A block management method for a rewritable non-volatile memory module having a plurality of physical blocks, and a memory controller and memory storage apparatus using the same are provided. The method includes logically grouping the physical blocks at least into a data area, a free area and a replacement area and configuring a plurality of logical blocks for mapping to the physical blocks of the data area. The method also includes assigning bad physical blocks into the data area and marking the logical blocks mapping to the bad physical blocks as bad logical addresses, thereby forbidding the access of the logical blocks mapping to the bad physical blocks. According, the method can effectively use the rewritable non-volatile memory module having too many bad physical blocks to store data.

Abstract: An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

Abstract: A data processing method for a re-writable non-volatile memory module is provided. The method includes receiving a write data stream associating to a logical access address of a logical programming unit; selecting a physical programming unit; and determining whether the write data stream associates with a kind of pattern. The method includes, if the write data stream associates with the kind of pattern, setting identification information corresponding to the logical access address as an identification value corresponding to the pattern, and storing the identification information corresponding to the logical access address into a predetermined area, wherein the write data stream is not programmed into the selected physical programming unit. The method further includes mapping the logical programming unit to the physical programming unit. Accordingly, the method can effectively shorten the time for writing data into the re-writable non-volatile memory module.

Abstract: System and methods are provided for storing address-mapping data from a storage device on a processing system. Address-mapping data is stored on a non-volatile memory of a storage device, the address-mapping data indicating mapping from logical addresses to physical addresses of the non-volatile memory of the storage device. The address-mapping data is transmitted from the non-volatile memory to a processing system. In response to a request to access a logical address of the non-volatile memory, part of the address-mapping data is transferred from the processing system to a volatile memory of the storage device, the part of the address-mapping data being associated with a mapping from the logical address to a physical address of the non-volatile memory.

Abstract: A method of associating a logical block address with a physical location in a non-volatile memory includes (A) in response to a write request comprising a respective logical block address in a logical block address space and respective data to be written to the non-volatile memory, determining a physical location in the non-volatile memory to store the respective data of the write request, (B) adding an entry to a journal, such that the added entry trails any entries already in the journal and the added entry has a respective logical block address field set to the respective logical block address of the write request and a respective physical location field set to the determined physical location, and (C) updating one of a plurality of second-level map pages in a two-level map according to the respective logical block address of the write request with the determined physical location.